2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 #include "ao_product.h"
26 #define USB_DEBUG_DATA 0
29 #ifndef AO_PA11_PA12_RMP
30 #error "must define AO_PA11_PA12_RMP"
33 #ifndef AO_POWER_MANAGEMENT
34 #define AO_POWER_MANAGEMENT 0
38 #define USE_USB_STDIO 1
42 #define AO_USB_OUT_SLEEP_ADDR (&ao_stdin_ready)
44 #define AO_USB_OUT_SLEEP_ADDR (&ao_usb_out_avail)
48 #define debug(format, args...) printf(format, ## args);
50 #define debug(format, args...)
54 #define debug_data(format, args...) printf(format, ## args);
56 #define debug_data(format, args...)
60 uint8_t dir_type_recip;
67 static uint8_t ao_usb_ep0_state;
69 /* Pending EP0 IN data */
70 static const uint8_t *ao_usb_ep0_in_data; /* Remaining data */
71 static uint8_t ao_usb_ep0_in_len; /* Remaining amount */
73 /* Temp buffer for smaller EP0 in data */
74 static uint8_t ao_usb_ep0_in_buf[2];
76 /* Pending EP0 OUT data */
77 static uint8_t *ao_usb_ep0_out_data;
78 static uint8_t ao_usb_ep0_out_len;
81 * Objects allocated in special USB memory
84 /* Buffer description tables */
85 static union stm_usb_bdt *ao_usb_bdt;
86 /* USB address of end of allocated storage */
88 static uint16_t ao_usb_sram_addr;
91 /* Pointer to ep0 tx/rx buffers in USB memory */
92 static uint16_t *ao_usb_ep0_tx_buffer;
93 static uint16_t *ao_usb_ep0_rx_buffer;
96 /* Pointer to interrupt buffer in USB memory */
97 static uint16_t ao_usb_int_tx_offset;
100 /* Pointer to bulk data tx/rx buffers in USB memory */
102 static uint16_t ao_usb_in_tx_offset[2];
103 static uint16_t *ao_usb_in_tx_buffer[2];
104 static uint8_t ao_usb_in_tx_which;
105 static uint8_t ao_usb_tx_count;
109 static uint16_t ao_usb_out_rx_offset[2];
110 static uint16_t *ao_usb_out_rx_buffer[2];
111 static uint8_t ao_usb_out_rx_which;
112 static uint8_t ao_usb_rx_count, ao_usb_rx_pos;
116 static uint16_t ao_usb_in2_tx_offset[2];
117 static uint16_t *ao_usb_in2_tx_buffer[2];
118 static uint8_t ao_usb_in_tx2_which;
119 static uint8_t ao_usb_tx2_count;
123 * End point register indices
126 #define AO_USB_CONTROL_EPR 0
127 #define AO_USB_INT_EPR 1
128 #define AO_USB_OUT_EPR 2
129 #define AO_USB_IN_EPR 3
130 #define AO_USB_IN2_EPR 4
132 /* Marks when we don't need to send an IN packet.
133 * This happens only when the last IN packet is not full,
134 * otherwise the host will expect to keep seeing packets.
135 * Send a zero-length packet as required
137 static uint8_t ao_usb_in_flushed;
139 /* Marks when we have delivered an IN packet to the hardware
140 * and it has not been received yet. ao_sleep on this address
141 * to wait for it to be delivered.
143 static uint8_t ao_usb_in_pending;
146 /* Marks when we have delivered an IN packet to the hardware
147 * and it has not been received yet. ao_sleep on this address
148 * to wait for it to be delivered.
150 static uint8_t ao_usb_in2_pending;
151 static uint16_t in2_count;
152 static uint8_t ao_usb_in2_flushed;
155 /* Marks when an OUT packet has been received by the hardware
156 * but not pulled to the shadow buffer.
158 static uint8_t ao_usb_out_avail;
159 uint8_t ao_usb_running;
160 static uint8_t ao_usb_configuration;
162 #define AO_USB_EP0_GOT_SETUP 1
163 #define AO_USB_EP0_GOT_RX_DATA 2
164 #define AO_USB_EP0_GOT_TX_ACK 4
166 static uint8_t ao_usb_ep0_receive;
167 static uint8_t ao_usb_address;
168 static uint8_t ao_usb_address_pending;
170 static inline uint32_t set_toggle(uint32_t current_value,
172 uint32_t desired_value)
174 return (current_value ^ desired_value) & mask;
177 static inline uint16_t *ao_usb_packet_buffer_addr(uint16_t sram_addr)
179 return (uint16_t *) (void *) (stm_usb_sram + sram_addr);
182 static inline uint16_t ao_usb_packet_buffer_offset(uint16_t *addr)
184 return (uint16_t) ((uint8_t *) addr - stm_usb_sram);
187 static inline uint32_t ao_usb_epr_stat_rx(uint32_t epr) {
188 return (epr >> STM_USB_EPR_STAT_RX) & STM_USB_EPR_STAT_RX_MASK;
191 static inline uint32_t ao_usb_epr_stat_tx(uint32_t epr) {
192 return (epr >> STM_USB_EPR_STAT_TX) & STM_USB_EPR_STAT_TX_MASK;
195 static inline uint32_t ao_usb_epr_ctr_rx(uint32_t epr) {
196 return (epr >> STM_USB_EPR_CTR_RX) & 1;
199 static inline uint32_t ao_usb_epr_ctr_tx(uint32_t epr) {
200 return (epr >> STM_USB_EPR_CTR_TX) & 1;
203 static inline uint32_t ao_usb_epr_setup(uint32_t epr) {
204 return (epr >> STM_USB_EPR_SETUP) & 1;
207 static inline uint32_t ao_usb_epr_dtog_rx(uint32_t epr) {
208 return (epr >> STM_USB_EPR_DTOG_RX) & 1;
211 static inline uint32_t ao_usb_epr_sw_buf_tx(uint32_t epr) {
212 return (epr >> STM_USB_EPR_SW_BUF_TX) & 1;
215 static inline uint32_t ao_usb_epr_dtog_tx(uint32_t epr) {
216 return (epr >> STM_USB_EPR_DTOG_TX) & 1;
219 static inline uint32_t ao_usb_epr_sw_buf_rx(uint32_t epr) {
220 return (epr >> STM_USB_EPR_SW_BUF_RX) & 1;
224 * Set current device address and mark the
225 * interface as active
228 ao_usb_set_address(uint8_t address)
230 debug("ao_usb_set_address %02x\n", address);
231 stm_usb.daddr = (1 << STM_USB_DADDR_EF) | address;
232 ao_usb_address_pending = 0;
236 * Write these values to preserve register contents under HW changes
239 #define STM_USB_EPR_INVARIANT ((1 << STM_USB_EPR_CTR_RX) | \
240 (STM_USB_EPR_DTOG_RX_WRITE_INVARIANT << STM_USB_EPR_DTOG_RX) | \
241 (STM_USB_EPR_STAT_RX_WRITE_INVARIANT << STM_USB_EPR_STAT_RX) | \
242 (1 << STM_USB_EPR_CTR_TX) | \
243 (STM_USB_EPR_DTOG_TX_WRITE_INVARIANT << STM_USB_EPR_DTOG_TX) | \
244 (STM_USB_EPR_STAT_TX_WRITE_INVARIANT << STM_USB_EPR_STAT_TX))
246 #define STM_USB_EPR_INVARIANT_MASK ((1 << STM_USB_EPR_CTR_RX) | \
247 (STM_USB_EPR_DTOG_RX_MASK << STM_USB_EPR_DTOG_RX) | \
248 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) | \
249 (1 << STM_USB_EPR_CTR_TX) | \
250 (STM_USB_EPR_DTOG_TX_MASK << STM_USB_EPR_DTOG_TX) | \
251 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX))
254 * These bits are purely under sw control, so preserve them in the
255 * register by re-writing what was read
257 #define STM_USB_EPR_PRESERVE_MASK ((STM_USB_EPR_EP_TYPE_MASK << STM_USB_EPR_EP_TYPE) | \
258 (1 << STM_USB_EPR_EP_KIND) | \
259 (STM_USB_EPR_EA_MASK << STM_USB_EPR_EA))
265 #define _tx_dbg0(msg) _dbg(__LINE__,msg,0)
266 #define _tx_dbg1(msg,value) _dbg(__LINE__,msg,value)
268 #define _tx_dbg0(msg)
269 #define _tx_dbg1(msg,value)
273 #define _rx_dbg0(msg) _dbg(__LINE__,msg,0)
274 #define _rx_dbg1(msg,value) _dbg(__LINE__,msg,value)
276 #define _rx_dbg0(msg)
277 #define _rx_dbg1(msg,value)
281 static void _dbg(int line, char *msg, uint32_t value);
285 * Set the state of the specified endpoint register to a new
286 * value. This is tricky because the bits toggle where the new
287 * value is one, and we need to write invariant values in other
288 * spots of the register. This hardware is strange...
291 _ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
293 uint16_t epr_write, epr_old;
295 _tx_dbg1("set_stat_tx top", stat_tx);
296 epr_old = epr_write = stm_usb.epr[ep].r;
297 epr_write &= STM_USB_EPR_PRESERVE_MASK;
298 epr_write |= STM_USB_EPR_INVARIANT;
299 epr_write |= set_toggle(epr_old,
300 STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX,
301 stat_tx << STM_USB_EPR_STAT_TX);
302 stm_usb.epr[ep].r = epr_write;
303 _tx_dbg1("set_stat_tx bottom", epr_write);
307 ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
309 ao_arch_block_interrupts();
310 _ao_usb_set_stat_tx(ep, stat_tx);
311 ao_arch_release_interrupts();
315 _ao_usb_toggle_dtog(int ep, uint32_t dtog_rx, uint32_t dtog_tx)
319 _tx_dbg1("toggle_dtog top", dtog_rx);
320 epr_write = stm_usb.epr[ep].r;
321 epr_write &= STM_USB_EPR_PRESERVE_MASK;
322 epr_write |= STM_USB_EPR_INVARIANT;
323 epr_write |= ((dtog_rx << STM_USB_EPR_DTOG_RX) |
324 (dtog_tx << STM_USB_EPR_DTOG_TX));
325 stm_usb.epr[ep].r = epr_write;
326 _tx_dbg1("toggle_dtog bottom", epr_write);
330 _ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
331 uint16_t epr_write, epr_old;
333 epr_write = epr_old = stm_usb.epr[ep].r;
334 epr_write &= STM_USB_EPR_PRESERVE_MASK;
335 epr_write |= STM_USB_EPR_INVARIANT;
336 epr_write |= set_toggle(epr_old,
337 STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX,
338 stat_rx << STM_USB_EPR_STAT_RX);
339 stm_usb.epr[ep].r = epr_write;
343 ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
344 ao_arch_block_interrupts();
345 _ao_usb_set_stat_rx(ep, stat_rx);
346 ao_arch_release_interrupts();
350 * Initialize an entpoint
354 ao_usb_init_ep(uint8_t ep, uint16_t addr, uint16_t type,
355 uint16_t stat_rx, uint16_t stat_tx,
357 uint16_t dtog_rx, uint16_t dtog_tx)
361 ao_arch_block_interrupts();
362 epr = stm_usb.epr[ep].r;
363 epr = ((0 << STM_USB_EPR_CTR_RX) |
364 (type << STM_USB_EPR_EP_TYPE) |
365 (kind << STM_USB_EPR_EP_KIND) |
366 (0 << STM_USB_EPR_CTR_TX) |
367 (addr << STM_USB_EPR_EA) |
370 (1 << STM_USB_EPR_DTOG_RX) |
371 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) |
372 (1 << STM_USB_EPR_DTOG_TX) |
373 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX),
375 (dtog_rx << STM_USB_EPR_DTOG_RX) |
376 (stat_rx << STM_USB_EPR_STAT_RX) |
377 (dtog_tx << STM_USB_EPR_DTOG_TX) |
378 (stat_tx << STM_USB_EPR_STAT_TX)));
379 stm_usb.epr[ep].r = epr;
380 ao_arch_release_interrupts();
381 debug ("writing epr[%d] 0x%04x wrote 0x%04x\n",
382 ep, epr, stm_usb.epr[ep].r);
386 ao_usb_alloc_buffers(void)
388 uint16_t sram_addr = 0;
390 ao_usb_bdt = (void *) stm_usb_sram;
391 sram_addr += 8 * STM_USB_BDT_SIZE;
393 ao_usb_ep0_tx_buffer = ao_usb_packet_buffer_addr(sram_addr);
394 sram_addr += AO_USB_CONTROL_SIZE;
396 ao_usb_ep0_rx_buffer = ao_usb_packet_buffer_addr(sram_addr);
397 sram_addr += AO_USB_CONTROL_SIZE;
401 sram_addr += (sram_addr & 1);
402 ao_usb_int_tx_offset = sram_addr;
403 sram_addr += AO_USB_INT_SIZE;
407 sram_addr += (sram_addr & 1);
408 ao_usb_out_rx_buffer[0] = ao_usb_packet_buffer_addr(sram_addr);
409 ao_usb_out_rx_offset[0] = sram_addr;
410 sram_addr += AO_USB_OUT_SIZE;
411 sram_addr += (sram_addr & 1);
412 ao_usb_out_rx_buffer[1] = ao_usb_packet_buffer_addr(sram_addr);
413 ao_usb_out_rx_offset[1] = sram_addr;
414 sram_addr += AO_USB_OUT_SIZE;
415 ao_usb_out_rx_which = 1;
419 sram_addr += (sram_addr & 1);
420 ao_usb_in_tx_buffer[0] = ao_usb_packet_buffer_addr(sram_addr);
421 ao_usb_in_tx_offset[0] = sram_addr;
422 sram_addr += AO_USB_IN_SIZE;
423 ao_usb_in_tx_buffer[1] = ao_usb_packet_buffer_addr(sram_addr);
424 ao_usb_in_tx_offset[1] = sram_addr;
425 sram_addr += AO_USB_IN_SIZE;
426 ao_usb_in_tx_which = 0;
430 sram_addr += (sram_addr & 1);
431 ao_usb_in2_tx_buffer[0] = ao_usb_packet_buffer_addr(sram_addr);
432 ao_usb_in2_tx_offset[0] = sram_addr;
433 sram_addr += AO_USB_IN_SIZE;
435 sram_addr += (sram_addr & 1);
436 ao_usb_in2_tx_buffer[1] = ao_usb_packet_buffer_addr(sram_addr);
437 ao_usb_in2_tx_offset[1] = sram_addr;
438 sram_addr += AO_USB_IN_SIZE;
439 ao_usb_in2_tx_which = 0;
443 sram_addr += (sram_addr & 1);
444 ao_usb_sram_addr = sram_addr;
449 ao_usb_init_btable(void)
451 /* Set up EP 0 - a Control end point with 32 bytes of in and out buffers */
453 ao_usb_bdt[0].single.addr_tx = ao_usb_packet_buffer_offset(ao_usb_ep0_tx_buffer);
454 ao_usb_bdt[0].single.count_tx = 0;
456 ao_usb_bdt[0].single.addr_rx = ao_usb_packet_buffer_offset(ao_usb_ep0_rx_buffer);
457 ao_usb_bdt[0].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
458 (((AO_USB_CONTROL_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
466 ao_usb_init_btable();
468 /* buffer table is at the start of USB memory */
471 ao_usb_init_ep(AO_USB_CONTROL_EPR, AO_USB_CONTROL_EP,
472 STM_USB_EPR_EP_TYPE_CONTROL,
473 STM_USB_EPR_STAT_RX_VALID,
474 STM_USB_EPR_STAT_TX_NAK,
475 STM_USB_EPR_EP_KIND_NO_STATUS_OUT, 0, 0);
477 /* Clear all of the other endpoints */
478 for (e = 1; e < 8; e++) {
480 STM_USB_EPR_EP_TYPE_CONTROL,
481 STM_USB_EPR_STAT_RX_DISABLED,
482 STM_USB_EPR_STAT_TX_DISABLED,
483 STM_USB_EPR_EP_KIND_SNGL_BUF, 0, 0);
486 ao_usb_set_address(0);
490 /* Reset our internal state
493 ao_usb_ep0_state = AO_USB_EP0_IDLE;
495 ao_usb_ep0_in_data = NULL;
496 ao_usb_ep0_in_len = 0;
498 ao_usb_ep0_out_data = 0;
499 ao_usb_ep0_out_len = 0;
503 ao_usb_set_configuration(void)
505 debug ("ao_usb_set_configuration\n");
508 /* Set up the INT end point */
509 ao_usb_bdt[AO_USB_INT_EPR].single.addr_tx = ao_usb_int_tx_offset;
510 ao_usb_bdt[AO_USB_INT_EPR].single.count_tx = 0;
512 ao_usb_init_ep(AO_USB_INT_EPR,
514 STM_USB_EPR_EP_TYPE_INTERRUPT,
515 STM_USB_EPR_STAT_RX_DISABLED,
516 STM_USB_EPR_STAT_TX_NAK,
517 STM_USB_EPR_EP_KIND_SNGL_BUF, 0, 0);
521 /* Set up the OUT end point */
522 ao_usb_bdt[AO_USB_OUT_EPR].double_rx[0].addr = ao_usb_out_rx_offset[0];
523 ao_usb_bdt[AO_USB_OUT_EPR].double_rx[0].count = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
524 (((AO_USB_OUT_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
526 ao_usb_bdt[AO_USB_OUT_EPR].double_rx[1].addr = ao_usb_out_rx_offset[1];
527 ao_usb_bdt[AO_USB_OUT_EPR].double_rx[1].count = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
528 (((AO_USB_OUT_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
530 /* set 'our' buffer to one, and the device buffer to 0 */
531 ao_usb_init_ep(AO_USB_OUT_EPR,
533 STM_USB_EPR_EP_TYPE_BULK,
534 STM_USB_EPR_STAT_RX_VALID,
535 STM_USB_EPR_STAT_TX_DISABLED,
536 STM_USB_EPR_EP_KIND_DBL_BUF, 0, 1);
540 /* Set up the IN end point */
541 ao_usb_bdt[AO_USB_IN_EPR].double_tx[0].addr = ao_usb_in_tx_offset[0];
542 ao_usb_bdt[AO_USB_IN_EPR].double_tx[0].count = 0;
543 ao_usb_bdt[AO_USB_IN_EPR].double_tx[1].addr = ao_usb_in_tx_offset[1];
544 ao_usb_bdt[AO_USB_IN_EPR].double_tx[1].count = 0;
546 /* set 'our' buffer to 0, and the device buffer to 1 */
547 ao_usb_init_ep(AO_USB_IN_EPR,
549 STM_USB_EPR_EP_TYPE_BULK,
550 STM_USB_EPR_STAT_RX_DISABLED,
551 STM_USB_EPR_STAT_TX_NAK,
552 STM_USB_EPR_EP_KIND_DBL_BUF,
557 /* Set up the IN2 end point */
558 ao_usb_bdt[AO_USB_IN2_EPR].single.addr_tx = 0;
559 ao_usb_bdt[AO_USB_IN2_EPR].single.count_tx = 0;
561 ao_usb_init_ep(AO_USB_IN2_EPR,
563 STM_USB_EPR_EP_TYPE_BULK,
564 STM_USB_EPR_STAT_RX_DISABLED,
565 STM_USB_EPR_STAT_TX_NAK,
566 STM_USB_EPR_EP_KIND_DBL_BUF,
570 ao_usb_in_flushed = 0;
571 ao_usb_in_pending = 0;
572 ao_wakeup(&ao_usb_in_pending);
574 ao_usb_in2_flushed = 0;
575 ao_usb_in2_pending = 0;
576 ao_wakeup(&ao_usb_in2_pending);
579 ao_usb_out_avail = 0;
580 ao_usb_configuration = 0;
582 ao_wakeup(AO_USB_OUT_SLEEP_ADDR);
586 ao_wakeup(&ao_usb_running);
591 static uint16_t control_count;
592 static uint16_t int_count;
593 static uint16_t in_count;
594 static uint16_t out_count;
595 static uint16_t reset_count;
598 /* The USB memory must be accessed in 16-bit units
602 ao_usb_copy_tx(const uint8_t *src, uint16_t *base, uint16_t bytes)
605 *base++ = src[0] | (src[1] << 8);
614 ao_usb_copy_rx(uint8_t *dst, uint16_t *base, uint16_t bytes)
617 uint16_t s = *base++;
628 ao_usb_tx_byte(uint16_t *base, uint8_t tx_count, char byte)
631 base[tx_count >> 1] |= ((uint16_t) byte) << 8;
633 base[tx_count >> 1] = (uint16_t) (uint8_t) byte;
637 ao_usb_rx_byte(uint16_t *base, uint8_t rx_count)
640 return (char) (base[rx_count>>1] >> 8);
642 return (char) base[rx_count>>1];
645 /* Send an IN data packet */
647 ao_usb_ep0_flush(void)
651 /* Check to see if the endpoint is still busy */
652 if (ao_usb_epr_stat_tx(stm_usb.epr[0].r) == STM_USB_EPR_STAT_TX_VALID) {
653 debug("EP0 not accepting IN data\n");
657 this_len = ao_usb_ep0_in_len;
658 if (this_len > AO_USB_CONTROL_SIZE)
659 this_len = AO_USB_CONTROL_SIZE;
661 if (this_len < AO_USB_CONTROL_SIZE)
662 ao_usb_ep0_state = AO_USB_EP0_IDLE;
664 ao_usb_ep0_in_len -= this_len;
666 debug_data ("Flush EP0 len %d:", this_len);
667 ao_usb_copy_tx(ao_usb_ep0_in_data, ao_usb_ep0_tx_buffer, this_len);
669 ao_usb_ep0_in_data += this_len;
671 /* Mark the endpoint as TX valid to send the packet */
672 ao_usb_bdt[AO_USB_CONTROL_EPR].single.count_tx = this_len;
673 ao_usb_set_stat_tx(AO_USB_CONTROL_EPR, STM_USB_EPR_STAT_TX_VALID);
674 debug ("queue tx. epr 0 now %08x\n", stm_usb.epr[AO_USB_CONTROL_EPR]);
677 /* Read data from the ep0 OUT fifo */
679 ao_usb_ep0_fill(void)
681 uint16_t len = ao_usb_bdt[0].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
683 if (len > ao_usb_ep0_out_len)
684 len = ao_usb_ep0_out_len;
685 ao_usb_ep0_out_len -= len;
687 /* Pull all of the data out of the packet */
688 debug_data ("Fill EP0 len %d:", len);
689 ao_usb_copy_rx(ao_usb_ep0_out_data, ao_usb_ep0_rx_buffer, len);
691 ao_usb_ep0_out_data += len;
694 ao_usb_set_stat_rx(0, STM_USB_EPR_STAT_RX_VALID);
698 ao_usb_ep0_in_reset(void)
700 ao_usb_ep0_in_data = ao_usb_ep0_in_buf;
701 ao_usb_ep0_in_len = 0;
705 ao_usb_ep0_in_queue_byte(uint8_t a)
707 if (ao_usb_ep0_in_len < sizeof (ao_usb_ep0_in_buf))
708 ao_usb_ep0_in_buf[ao_usb_ep0_in_len++] = a;
712 ao_usb_ep0_in_set(const uint8_t *data, uint8_t len)
714 ao_usb_ep0_in_data = data;
715 ao_usb_ep0_in_len = len;
719 ao_usb_ep0_out_set(uint8_t *data, uint8_t len)
721 ao_usb_ep0_out_data = data;
722 ao_usb_ep0_out_len = len;
726 ao_usb_ep0_in_start(uint16_t max)
728 /* Don't send more than asked for */
729 if (ao_usb_ep0_in_len > max)
730 ao_usb_ep0_in_len = max;
734 struct ao_usb_line_coding ao_usb_line_coding = {115200, 0, 0, 8};
736 #if AO_USB_DEVICE_ID_SERIAL
737 static uint8_t ao_usb_serial[2 + 48];
739 /* Convert a 32-bit value to 8 hexidecimal UCS2 characters */
741 hex_to_ucs2(uint32_t in, uint8_t *out)
745 for (i = 28; i >= 0; i -= 4) {
746 uint8_t bits = (in >> i) & 0xf;
747 *out++ = ((bits < 10) ? '0' : ('a' - 10)) + bits;
752 /* Encode the device ID (96 bits) in hexidecimal to use as a device
756 ao_usb_serial_init(void)
758 ao_usb_serial[0] = 50; /* length */
759 ao_usb_serial[1] = AO_USB_DESC_STRING;
760 hex_to_ucs2(stm_device_id.u_id0, ao_usb_serial + 2 + 0);
761 hex_to_ucs2(stm_device_id.u_id1, ao_usb_serial + 2 + 16);
762 hex_to_ucs2(stm_device_id.u_id2, ao_usb_serial + 2 + 32);
766 /* Walk through the list of descriptors and find a match
769 ao_usb_get_descriptor(uint16_t value, uint16_t length)
771 const uint8_t *descriptor;
772 uint8_t type = value >> 8;
773 uint8_t index = value;
775 descriptor = ao_usb_descriptors;
776 while (descriptor[0] != 0) {
777 if (descriptor[1] == type && index-- == 0) {
779 if (type == AO_USB_DESC_CONFIGURATION)
783 #if AO_USB_DEVICE_ID_SERIAL
784 /* Slightly hacky - the serial number is string 3 */
785 if (type == AO_USB_DESC_STRING && (value & 0xff) == 3) {
786 descriptor = ao_usb_serial;
787 len = sizeof (ao_usb_serial);
792 ao_usb_ep0_in_set(descriptor, len);
795 descriptor += descriptor[0];
800 ao_usb_ep0_setup(void)
802 /* Pull the setup packet out of the fifo */
803 ao_usb_ep0_out_set((uint8_t *) &ao_usb_setup, 8);
805 if (ao_usb_ep0_out_len != 0) {
806 debug ("invalid setup packet length\n");
810 if ((ao_usb_setup.dir_type_recip & AO_USB_DIR_IN) || ao_usb_setup.length == 0)
811 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
813 ao_usb_ep0_state = AO_USB_EP0_DATA_OUT;
815 ao_usb_ep0_in_reset();
817 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_TYPE_MASK) {
818 case AO_USB_TYPE_STANDARD:
819 debug ("Standard setup packet\n");
820 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_RECIP_MASK) {
821 case AO_USB_RECIP_DEVICE:
822 debug ("Device setup packet\n");
823 switch(ao_usb_setup.request) {
824 case AO_USB_REQ_GET_STATUS:
825 debug ("get status\n");
826 ao_usb_ep0_in_queue_byte(0);
827 ao_usb_ep0_in_queue_byte(0);
829 case AO_USB_REQ_SET_ADDRESS:
830 debug ("set address %d\n", ao_usb_setup.value);
831 ao_usb_address = ao_usb_setup.value;
832 ao_usb_address_pending = 1;
834 case AO_USB_REQ_GET_DESCRIPTOR:
835 debug ("get descriptor %d\n", ao_usb_setup.value);
836 ao_usb_get_descriptor(ao_usb_setup.value, ao_usb_setup.length);
838 case AO_USB_REQ_GET_CONFIGURATION:
839 debug ("get configuration %d\n", ao_usb_configuration);
840 ao_usb_ep0_in_queue_byte(ao_usb_configuration);
842 case AO_USB_REQ_SET_CONFIGURATION:
843 ao_usb_configuration = ao_usb_setup.value;
844 debug ("set configuration %d\n", ao_usb_configuration);
845 ao_usb_set_configuration();
849 case AO_USB_RECIP_INTERFACE:
850 debug ("Interface setup packet\n");
851 switch(ao_usb_setup.request) {
852 case AO_USB_REQ_GET_STATUS:
853 ao_usb_ep0_in_queue_byte(0);
854 ao_usb_ep0_in_queue_byte(0);
856 case AO_USB_REQ_GET_INTERFACE:
857 ao_usb_ep0_in_queue_byte(0);
859 case AO_USB_REQ_SET_INTERFACE:
863 case AO_USB_RECIP_ENDPOINT:
864 debug ("Endpoint setup packet\n");
865 switch(ao_usb_setup.request) {
866 case AO_USB_REQ_GET_STATUS:
867 ao_usb_ep0_in_queue_byte(0);
868 ao_usb_ep0_in_queue_byte(0);
874 case AO_USB_TYPE_CLASS:
875 debug ("Class setup packet\n");
876 switch (ao_usb_setup.request) {
877 case AO_USB_SET_LINE_CODING:
878 debug ("set line coding\n");
879 ao_usb_ep0_out_set((uint8_t *) &ao_usb_line_coding, 7);
881 case AO_USB_GET_LINE_CODING:
882 debug ("get line coding\n");
883 ao_usb_ep0_in_set((const uint8_t *) &ao_usb_line_coding, 7);
885 case AO_USB_SET_CONTROL_LINE_STATE:
891 /* If we're not waiting to receive data from the host,
892 * queue an IN response
894 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
895 ao_usb_ep0_in_start(ao_usb_setup.length);
899 ao_usb_ep0_handle(uint8_t receive)
901 ao_usb_ep0_receive = 0;
902 if (receive & AO_USB_EP0_GOT_SETUP) {
906 if (receive & AO_USB_EP0_GOT_RX_DATA) {
907 debug ("\tgot rx data\n");
908 if (ao_usb_ep0_state == AO_USB_EP0_DATA_OUT) {
910 if (ao_usb_ep0_out_len == 0) {
911 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
912 ao_usb_ep0_in_start(0);
916 if (receive & AO_USB_EP0_GOT_TX_ACK) {
917 debug ("\tgot tx ack\n");
919 #if HAS_FLIGHT && AO_USB_FORCE_IDLE
920 ao_flight_force_idle = 1;
922 /* Wait until the IN packet is received from addr 0
923 * before assigning our local address
925 if (ao_usb_address_pending)
926 ao_usb_set_address(ao_usb_address);
927 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
932 #if AO_POWER_MANAGEMENT
936 stm_usb.cntr |= (1 << STM_USB_CNTR_FSUSP);
938 stm_usb.cntr |= (1 << STM_USB_CNTR_LP_MODE);
946 stm_usb.cntr &= ~(1 << STM_USB_CNTR_FSUSP);
954 uint32_t istr = stm_usb.istr;
956 stm_usb.istr = ~istr;
957 if (istr & (1 << STM_USB_ISTR_CTR)) {
958 uint8_t ep = istr & STM_USB_ISTR_EP_ID_MASK;
959 uint16_t epr, epr_write;
961 /* Preserve the SW write bits, don't mess with most HW writable bits,
962 * clear the CTR_RX and CTR_TX bits
964 epr = stm_usb.epr[ep].r;
966 epr_write &= STM_USB_EPR_PRESERVE_MASK;
967 epr_write |= STM_USB_EPR_INVARIANT;
968 epr_write &= ~(1 << STM_USB_EPR_CTR_RX);
969 epr_write &= ~(1 << STM_USB_EPR_CTR_TX);
970 stm_usb.epr[ep].r = epr_write;
977 if (ao_usb_epr_ctr_rx(epr)) {
978 if (ao_usb_epr_setup(epr))
979 ao_usb_ep0_receive |= AO_USB_EP0_GOT_SETUP;
981 ao_usb_ep0_receive |= AO_USB_EP0_GOT_RX_DATA;
983 if (ao_usb_epr_ctr_tx(epr))
984 ao_usb_ep0_receive |= AO_USB_EP0_GOT_TX_ACK;
985 ao_usb_ep0_handle(ao_usb_ep0_receive);
991 if (ao_usb_epr_ctr_rx(epr)) {
992 _rx_dbg1("RX ISR", epr);
993 ao_usb_out_avail = 1;
994 _rx_dbg0("out avail set");
995 ao_wakeup(AO_USB_OUT_SLEEP_ADDR);
996 _rx_dbg0("stdin awoken");
1003 _tx_dbg1("TX ISR", epr);
1004 if (ao_usb_epr_ctr_tx(epr)) {
1005 ao_usb_in_pending = 0;
1006 ao_wakeup(&ao_usb_in_pending);
1010 case AO_USB_IN2_EPR:
1012 _tx_dbg1("TX2 ISR", epr);
1013 if (ao_usb_epr_ctr_tx(epr)) {
1014 ao_usb_in2_pending = 0;
1015 ao_wakeup(&ao_usb_in2_pending);
1019 case AO_USB_INT_EPR:
1023 if (ao_usb_epr_ctr_tx(epr))
1024 _ao_usb_set_stat_tx(AO_USB_INT_EPR, STM_USB_EPR_STAT_TX_NAK);
1030 if (istr & (1 << STM_USB_ISTR_RESET)) {
1034 debug ("\treset\n");
1037 #if AO_POWER_MANAGEMENT
1038 if (istr & (1 << STM_USB_ISTR_SUSP)) {
1039 debug ("\tsuspend\n");
1042 if (istr & (1 << STM_USB_ISTR_WKUP)) {
1043 debug ("\twakeup\n");
1050 /* Queue the current IN buffer for transmission */
1052 _ao_usb_in_send(void)
1054 _tx_dbg0("in_send start");
1055 debug ("send %d\n", ao_usb_tx_count);
1056 while (ao_usb_in_pending)
1057 ao_sleep(&ao_usb_in_pending);
1058 ao_usb_in_pending = 1;
1059 if (ao_usb_tx_count != AO_USB_IN_SIZE)
1060 ao_usb_in_flushed = 1;
1061 ao_usb_bdt[AO_USB_IN_EPR].double_tx[ao_usb_in_tx_which].count = ao_usb_tx_count;
1062 ao_usb_tx_count = 0;
1064 /* Toggle our usage */
1065 ao_usb_in_tx_which = 1 - ao_usb_in_tx_which;
1067 /* Toggle the SW_BUF flag */
1068 _ao_usb_toggle_dtog(AO_USB_IN_EPR, 1, 0);
1070 /* Mark the outgoing buffer as valid */
1071 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
1073 _tx_dbg0("in_send end");
1076 /* Wait for a free IN buffer. Interrupts are blocked */
1078 _ao_usb_in_wait(void)
1081 /* Check if the current buffer is writable */
1082 if (ao_usb_tx_count < AO_USB_IN_SIZE)
1085 _tx_dbg0("in_wait top");
1086 /* Wait for an IN buffer to be ready */
1087 while (ao_usb_in_pending)
1088 ao_sleep(&ao_usb_in_pending);
1089 _tx_dbg0("in_wait bottom");
1096 if (!ao_usb_running)
1099 /* Anytime we've sent a character since
1100 * the last time we flushed, we'll need
1101 * to send a packet -- the only other time
1102 * we would send a packet is when that
1103 * packet was full, in which case we now
1104 * want to send an empty packet
1106 ao_arch_block_interrupts();
1107 while (!ao_usb_in_flushed) {
1108 _tx_dbg0("flush top");
1110 _tx_dbg0("flush end");
1112 ao_arch_release_interrupts();
1116 ao_usb_putchar(char c)
1118 if (!ao_usb_running)
1121 ao_arch_block_interrupts();
1124 ao_usb_in_flushed = 0;
1125 ao_usb_tx_byte(ao_usb_in_tx_buffer[ao_usb_in_tx_which], ao_usb_tx_count++, c);
1127 /* Send the packet when full */
1128 if (ao_usb_tx_count == AO_USB_IN_SIZE) {
1129 _tx_dbg0("putchar full");
1131 _tx_dbg0("putchar flushed");
1133 ao_arch_release_interrupts();
1138 /* Queue the current IN buffer for transmission */
1140 _ao_usb_in2_send(void)
1142 _tx_dbg0("in2_send start");
1143 debug ("send2 %d\n", ao_usb_tx_count);
1144 while (ao_usb_in2_pending)
1145 ao_sleep(&ao_usb_in2_pending);
1146 ao_usb_in2_pending = 1;
1147 if (ao_usb_tx2_count != AO_USB_IN_SIZE)
1148 ao_usb_in2_flushed = 1;
1149 ao_usb_bdt[AO_USB_IN2_EPR].single.addr_tx = ao_usb_in2_tx_offset[ao_usb_in2_tx_which];
1150 ao_usb_bdt[AO_USB_IN2_EPR].single.count_tx = ao_usb_tx2_count;
1151 ao_usb_tx2_count = 0;
1152 ao_usb_in2_tx_which = 1 - ao_usb_in2_tx_which;
1153 _ao_usb_set_stat_tx(AO_USB_IN2_EPR, STM_USB_EPR_STAT_TX_VALID);
1154 _tx_dbg0("in2_send end");
1157 /* Wait for a free IN buffer. Interrupts are blocked */
1159 _ao_usb_in2_wait(void)
1162 /* Check if the current buffer is writable */
1163 if (ao_usb_tx2_count < AO_USB_IN_SIZE)
1166 _tx_dbg0("in2_wait top");
1167 /* Wait for an IN buffer to be ready */
1168 while (ao_usb_in2_pending)
1169 ao_sleep(&ao_usb_in2_pending);
1170 _tx_dbg0("in_wait bottom");
1177 if (!ao_usb_running)
1180 /* Anytime we've sent a character since
1181 * the last time we flushed, we'll need
1182 * to send a packet -- the only other time
1183 * we would send a packet is when that
1184 * packet was full, in which case we now
1185 * want to send an empty packet
1187 ao_arch_block_interrupts();
1188 while (!ao_usb_in2_flushed) {
1189 _tx_dbg0("flush2 top");
1191 _tx_dbg0("flush2 end");
1193 ao_arch_release_interrupts();
1197 ao_usb_putchar2(char c)
1199 if (!ao_usb_running)
1202 ao_arch_block_interrupts();
1205 ao_usb_in2_flushed = 0;
1206 ao_usb_tx_byte(ao_usb_in2_tx_buffer[ao_usb_in2_tx_which], ao_usb_tx2_count, c);
1209 /* Send the packet when full */
1210 if (ao_usb_tx2_count == AO_USB_IN_SIZE) {
1211 _tx_dbg0("putchar2 full");
1213 _tx_dbg0("putchar2 flushed");
1215 ao_arch_release_interrupts();
1221 _ao_usb_out_recv(void)
1223 _rx_dbg1("out_recv top", stm_usb.epr[AO_USB_OUT_EPR].r);
1225 /* Clear packet available field until we get another interrupt */
1226 ao_usb_out_avail = 0;
1228 /* Switch to new buffer */
1229 ao_usb_out_rx_which = 1 - ao_usb_out_rx_which;
1231 ao_usb_rx_count = ao_usb_bdt[AO_USB_OUT_EPR].double_rx[ao_usb_out_rx_which].count & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
1234 /* Toggle the SW_BUF_RX bit */
1235 _ao_usb_toggle_dtog(AO_USB_OUT_EPR, 0, 1);
1237 // /* Ack the packet */
1238 // _ao_usb_set_stat_rx(AO_USB_OUT_EPR, STM_USB_EPR_STAT_RX_VALID);
1240 _rx_dbg1("out_recv count", ao_usb_rx_count);
1244 _ao_usb_pollchar(void)
1248 if (!ao_usb_running)
1249 return AO_READ_AGAIN;
1252 if (ao_usb_rx_pos != ao_usb_rx_count)
1255 // _rx_dbg0("poll check");
1256 /* Check to see if a packet has arrived */
1257 if (!ao_usb_out_avail) {
1258 // _rx_dbg0("poll none");
1259 return AO_READ_AGAIN;
1264 /* Pull a character out of the fifo */
1265 c = ao_usb_rx_byte(ao_usb_out_rx_buffer[ao_usb_out_rx_which], ao_usb_rx_pos++);
1266 _rx_dbg1("char", c);
1271 ao_usb_getchar(void)
1275 ao_arch_block_interrupts();
1276 while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN)
1277 ao_sleep(AO_USB_OUT_SLEEP_ADDR);
1278 ao_arch_release_interrupts();
1289 buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
1290 ao_usb_sram_addr += AO_USB_IN_SIZE;
1295 ao_usb_write(uint16_t *buffer, uint16_t len)
1297 ao_arch_block_interrupts();
1299 /* Wait for everything to be ready at the same time */
1301 /* Make sure USB is connected */
1302 if (!ao_usb_running) {
1303 ao_sleep(&ao_usb_running);
1307 /* Flush any pending regular I/O */
1308 if (ao_usb_tx_count) {
1313 /* Wait for an idle IN buffer */
1314 if (ao_usb_in_pending) {
1315 ao_sleep(&ao_usb_in_pending);
1321 ao_usb_in_pending = 1;
1322 ao_usb_in_flushed = (len != AO_USB_IN_SIZE);
1323 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_packet_buffer_offset(buffer);
1324 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = len;
1325 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
1326 ao_arch_release_interrupts();
1331 ao_usb_write2(uint16_t *buffer, uint16_t len)
1333 ao_arch_block_interrupts();
1335 /* Wait for everything to be ready at the same time */
1337 /* Make sure USB is connected */
1338 if (!ao_usb_running) {
1339 ao_sleep(&ao_usb_running);
1343 /* Flush any pending regular I/O */
1344 if (ao_usb_tx2_count) {
1349 /* Wait for an idle IN buffer */
1350 if (ao_usb_in2_pending) {
1351 ao_sleep(&ao_usb_in2_pending);
1357 ao_usb_in2_pending = 1;
1358 ao_usb_in2_flushed = (len != AO_USB_IN_SIZE);
1359 ao_usb_bdt[AO_USB_IN2_EPR].single.addr_tx = ao_usb_packet_buffer_offset(buffer);
1360 ao_usb_bdt[AO_USB_IN2_EPR].single.count_tx = len;
1361 _ao_usb_set_stat_tx(AO_USB_IN2_EPR, STM_USB_EPR_STAT_TX_VALID);
1362 ao_arch_release_interrupts();
1368 ao_usb_disable(void)
1370 ao_arch_block_interrupts();
1371 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1374 /* Disable USB pull-up */
1375 stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
1377 /* Switch off the device */
1378 stm_usb.cntr = (1 << STM_USB_CNTR_PDWN) | (1 << STM_USB_CNTR_FRES);
1380 /* Disable the interface */
1381 stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_USBEN);
1382 ao_arch_release_interrupts();
1390 /* Select HSI48 as USB clock source */
1391 stm_rcc.cfgr3 &= ~(1 << STM_RCC_CFGR3_USBSW);
1393 /* Enable USB device */
1394 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USBEN);
1396 /* Clear reset condition */
1397 stm_rcc.apb1rstr &= ~(1 << STM_RCC_APB1RSTR_USBRST);
1399 /* Disable USB pull-up */
1400 stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
1402 /* Do not touch the GPIOA configuration; USB takes priority
1403 * over GPIO on pins A11 and A12, but if you select alternate
1404 * input 10 (the documented correct selection), then USB is
1405 * pulled low and doesn't work at all
1408 ao_arch_block_interrupts();
1410 /* Route interrupts */
1411 stm_nvic_set_enable(STM_ISR_USB_POS);
1412 stm_nvic_set_priority(STM_ISR_USB_POS, 3);
1414 ao_usb_configuration = 0;
1416 /* Set up buffer descriptors */
1417 ao_usb_init_btable();
1419 /* Reset the USB controller */
1420 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1422 /* Clear the reset bit */
1425 /* Clear any spurious interrupts */
1430 debug ("ao_usb_enable\n");
1432 /* Enable interrupts */
1433 stm_usb.cntr = ((1 << STM_USB_CNTR_CTRM) |
1434 (0 << STM_USB_CNTR_PMAOVRM) |
1435 (0 << STM_USB_CNTR_ERRM) |
1436 (AO_POWER_MANAGEMENT << STM_USB_CNTR_WKUPM) |
1437 (AO_POWER_MANAGEMENT << STM_USB_CNTR_SUSPM) |
1438 (1 << STM_USB_CNTR_RESETM) |
1439 (0 << STM_USB_CNTR_SOFM) |
1440 (0 << STM_USB_CNTR_ESOFM) |
1441 (0 << STM_USB_CNTR_RESUME) |
1442 (0 << STM_USB_CNTR_FSUSP) |
1443 (0 << STM_USB_CNTR_LP_MODE) |
1444 (0 << STM_USB_CNTR_PDWN) |
1445 (0 << STM_USB_CNTR_FRES));
1447 ao_arch_release_interrupts();
1449 for (t = 0; t < 1000; t++)
1452 /* Enable USB pull-up */
1453 stm_usb.bcdr |= (1 << STM_USB_BCDR_DPPU);
1457 struct ao_task ao_usb_echo_task;
1465 c = ao_usb_getchar();
1476 printf ("control: %d out: %d in: %d int: %d reset: %d\n",
1477 control_count, out_count, in_count, int_count, reset_count);
1480 __code struct ao_cmds ao_usb_cmds[] = {
1481 { ao_usb_irq, "I\0Show USB interrupt counts" },
1489 /* Turn on syscfg */
1490 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
1492 /* Set PA11/PA12 remapping bit */
1493 stm_syscfg.cfgr1 |= (AO_PA11_PA12_RMP << STM_SYSCFG_CFGR1_PA11_PA12_RMP);
1495 #ifndef AO_USB_START_DISABLED
1499 #if AO_USB_DEVICE_ID_SERIAL
1500 ao_usb_serial_init();
1503 debug ("ao_usb_init\n");
1504 ao_usb_ep0_state = AO_USB_EP0_IDLE;
1506 ao_usb_alloc_buffers();
1509 ao_add_task(&ao_usb_echo_task, ao_usb_echo, "usb echo");
1512 ao_cmd_register(&ao_usb_cmds[0]);
1516 ao_add_stdio(_ao_usb_pollchar, ao_usb_putchar, ao_usb_flush);
1521 #if TX_DBG || RX_DBG
1531 uint32_t in_pending;
1533 uint32_t in_flushed;
1543 #define NUM_USB_DBG 128
1545 struct ao_usb_dbg dbg[128];
1548 static void _dbg(int line, char *msg, uint32_t value)
1551 dbg[dbg_i].line = line;
1552 dbg[dbg_i].msg = msg;
1553 dbg[dbg_i].value = value;
1554 asm("mrs %0,primask" : "=&r" (primask));
1555 dbg[dbg_i].primask = primask;
1557 dbg[dbg_i].in_count = in_count;
1558 dbg[dbg_i].in_epr = stm_usb.epr[AO_USB_IN_EPR];
1559 dbg[dbg_i].in_pending = ao_usb_in_pending;
1560 dbg[dbg_i].tx_count = ao_usb_tx_count;
1561 dbg[dbg_i].in_flushed = ao_usb_in_flushed;
1564 dbg[dbg_i].rx_count = ao_usb_rx_count;
1565 dbg[dbg_i].rx_pos = ao_usb_rx_pos;
1566 dbg[dbg_i].out_avail = ao_usb_out_avail;
1567 dbg[dbg_i].out_epr = stm_usb.epr[AO_USB_OUT_EPR].r;
1569 if (++dbg_i == NUM_USB_DBG)