2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 #include "ao_product.h"
23 #define USB_DEBUG_DATA 0
27 #define USE_USB_STDIO 1
31 #define AO_USB_OUT_SLEEP_ADDR (&ao_stdin_ready)
33 #define AO_USB_OUT_SLEEP_ADDR (&ao_usb_out_avail)
37 #define debug(format, args...) printf(format, ## args);
39 #define debug(format, args...)
43 #define debug_data(format, args...) printf(format, ## args);
45 #define debug_data(format, args...)
49 uint8_t dir_type_recip;
56 static uint8_t ao_usb_ep0_state;
58 /* Pending EP0 IN data */
59 static const uint8_t *ao_usb_ep0_in_data; /* Remaining data */
60 static uint8_t ao_usb_ep0_in_len; /* Remaining amount */
62 /* Temp buffer for smaller EP0 in data */
63 static uint8_t ao_usb_ep0_in_buf[2];
65 /* Pending EP0 OUT data */
66 static uint8_t *ao_usb_ep0_out_data;
67 static uint8_t ao_usb_ep0_out_len;
70 * Objects allocated in special USB memory
73 /* Buffer description tables */
74 static union stm_usb_bdt *ao_usb_bdt;
75 /* USB address of end of allocated storage */
76 static uint16_t ao_usb_sram_addr;
78 /* Pointer to ep0 tx/rx buffers in USB memory */
79 static uint16_t *ao_usb_ep0_tx_buffer;
80 static uint16_t *ao_usb_ep0_rx_buffer;
82 /* Pointer to bulk data tx/rx buffers in USB memory */
83 static uint16_t *ao_usb_in_tx_buffer;
84 static uint16_t *ao_usb_out_rx_buffer;
86 /* System ram shadow of USB buffer; writing individual bytes is
87 * too much of a pain (sigh) */
88 static uint8_t ao_usb_tx_buffer[AO_USB_IN_SIZE];
89 static uint8_t ao_usb_tx_count;
91 static uint8_t ao_usb_rx_buffer[AO_USB_OUT_SIZE];
92 static uint8_t ao_usb_rx_count, ao_usb_rx_pos;
95 * End point register indices
98 #define AO_USB_CONTROL_EPR 0
99 #define AO_USB_INT_EPR 1
100 #define AO_USB_OUT_EPR 2
101 #define AO_USB_IN_EPR 3
103 /* Marks when we don't need to send an IN packet.
104 * This happens only when the last IN packet is not full,
105 * otherwise the host will expect to keep seeing packets.
106 * Send a zero-length packet as required
108 static uint8_t ao_usb_in_flushed;
110 /* Marks when we have delivered an IN packet to the hardware
111 * and it has not been received yet. ao_sleep on this address
112 * to wait for it to be delivered.
114 static uint8_t ao_usb_in_pending;
116 /* Marks when an OUT packet has been received by the hardware
117 * but not pulled to the shadow buffer.
119 static uint8_t ao_usb_out_avail;
120 uint8_t ao_usb_running;
121 static uint8_t ao_usb_configuration;
123 #define AO_USB_EP0_GOT_RESET 1
124 #define AO_USB_EP0_GOT_SETUP 2
125 #define AO_USB_EP0_GOT_RX_DATA 4
126 #define AO_USB_EP0_GOT_TX_ACK 8
128 static uint8_t ao_usb_ep0_receive;
129 static uint8_t ao_usb_address;
130 static uint8_t ao_usb_address_pending;
132 static inline uint32_t set_toggle(uint32_t current_value,
134 uint32_t desired_value)
136 return (current_value ^ desired_value) & mask;
139 static inline uint16_t *ao_usb_packet_buffer_addr(uint16_t sram_addr)
141 return (uint16_t *) (stm_usb_sram + sram_addr);
144 static inline uint32_t ao_usb_epr_stat_rx(uint32_t epr) {
145 return (epr >> STM_USB_EPR_STAT_RX) & STM_USB_EPR_STAT_RX_MASK;
148 static inline uint32_t ao_usb_epr_stat_tx(uint32_t epr) {
149 return (epr >> STM_USB_EPR_STAT_TX) & STM_USB_EPR_STAT_TX_MASK;
152 static inline uint32_t ao_usb_epr_ctr_rx(uint32_t epr) {
153 return (epr >> STM_USB_EPR_CTR_RX) & 1;
156 static inline uint32_t ao_usb_epr_ctr_tx(uint32_t epr) {
157 return (epr >> STM_USB_EPR_CTR_TX) & 1;
160 static inline uint32_t ao_usb_epr_setup(uint32_t epr) {
161 return (epr >> STM_USB_EPR_SETUP) & 1;
164 static inline uint32_t ao_usb_epr_dtog_rx(uint32_t epr) {
165 return (epr >> STM_USB_EPR_DTOG_RX) & 1;
168 static inline uint32_t ao_usb_epr_dtog_tx(uint32_t epr) {
169 return (epr >> STM_USB_EPR_DTOG_TX) & 1;
173 * Set current device address and mark the
174 * interface as active
177 ao_usb_set_address(uint8_t address)
179 debug("ao_usb_set_address %02x\n", address);
180 stm_usb.daddr = (1 << STM_USB_DADDR_EF) | address;
181 ao_usb_address_pending = 0;
185 * Write these values to preserve register contents under HW changes
188 #define STM_USB_EPR_INVARIANT ((1 << STM_USB_EPR_CTR_RX) | \
189 (STM_USB_EPR_DTOG_RX_WRITE_INVARIANT << STM_USB_EPR_DTOG_RX) | \
190 (STM_USB_EPR_STAT_RX_WRITE_INVARIANT << STM_USB_EPR_STAT_RX) | \
191 (1 << STM_USB_EPR_CTR_TX) | \
192 (STM_USB_EPR_DTOG_TX_WRITE_INVARIANT << STM_USB_EPR_DTOG_TX) | \
193 (STM_USB_EPR_STAT_TX_WRITE_INVARIANT << STM_USB_EPR_STAT_TX))
195 #define STM_USB_EPR_INVARIANT_MASK ((1 << STM_USB_EPR_CTR_RX) | \
196 (STM_USB_EPR_DTOG_RX_MASK << STM_USB_EPR_DTOG_RX) | \
197 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) | \
198 (1 << STM_USB_EPR_CTR_TX) | \
199 (STM_USB_EPR_DTOG_TX_MASK << STM_USB_EPR_DTOG_TX) | \
200 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX))
203 * These bits are purely under sw control, so preserve them in the
204 * register by re-writing what was read
206 #define STM_USB_EPR_PRESERVE_MASK ((STM_USB_EPR_EP_TYPE_MASK << STM_USB_EPR_EP_TYPE) | \
207 (1 << STM_USB_EPR_EP_KIND) | \
208 (STM_USB_EPR_EA_MASK << STM_USB_EPR_EA))
214 #define _tx_dbg0(msg) _dbg(__LINE__,msg,0)
215 #define _tx_dbg1(msg,value) _dbg(__LINE__,msg,value)
217 #define _tx_dbg0(msg)
218 #define _tx_dbg1(msg,value)
222 #define _rx_dbg0(msg) _dbg(__LINE__,msg,0)
223 #define _rx_dbg1(msg,value) _dbg(__LINE__,msg,value)
225 #define _rx_dbg0(msg)
226 #define _rx_dbg1(msg,value)
230 static void _dbg(int line, char *msg, uint32_t value);
234 * Set the state of the specified endpoint register to a new
235 * value. This is tricky because the bits toggle where the new
236 * value is one, and we need to write invariant values in other
237 * spots of the register. This hardware is strange...
240 _ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
242 uint16_t epr_write, epr_old;
244 _tx_dbg1("set_stat_tx top", stat_tx);
245 epr_old = epr_write = stm_usb.epr[ep].r;
246 epr_write &= STM_USB_EPR_PRESERVE_MASK;
247 epr_write |= STM_USB_EPR_INVARIANT;
248 epr_write |= set_toggle(epr_old,
249 STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX,
250 stat_tx << STM_USB_EPR_STAT_TX);
251 stm_usb.epr[ep].r = epr_write;
252 _tx_dbg1("set_stat_tx bottom", epr_write);
256 ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
258 ao_arch_block_interrupts();
259 _ao_usb_set_stat_tx(ep, stat_tx);
260 ao_arch_release_interrupts();
264 _ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
265 uint16_t epr_write, epr_old;
267 epr_write = epr_old = stm_usb.epr[ep].r;
268 epr_write &= STM_USB_EPR_PRESERVE_MASK;
269 epr_write |= STM_USB_EPR_INVARIANT;
270 epr_write |= set_toggle(epr_old,
271 STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX,
272 stat_rx << STM_USB_EPR_STAT_RX);
273 stm_usb.epr[ep].r = epr_write;
277 ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
278 ao_arch_block_interrupts();
279 _ao_usb_set_stat_rx(ep, stat_rx);
280 ao_arch_release_interrupts();
284 * Set just endpoint 0, for use during startup
288 ao_usb_init_ep(uint8_t ep, uint32_t addr, uint32_t type, uint32_t stat_rx, uint32_t stat_tx)
292 ao_arch_block_interrupts();
293 epr = stm_usb.epr[ep].r;
294 epr = ((0 << STM_USB_EPR_CTR_RX) |
295 (epr & (1 << STM_USB_EPR_DTOG_RX)) |
297 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX),
298 (stat_rx << STM_USB_EPR_STAT_RX)) |
299 (type << STM_USB_EPR_EP_TYPE) |
300 (0 << STM_USB_EPR_EP_KIND) |
301 (0 << STM_USB_EPR_CTR_TX) |
302 (epr & (1 << STM_USB_EPR_DTOG_TX)) |
304 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX),
305 (stat_tx << STM_USB_EPR_STAT_TX)) |
306 (addr << STM_USB_EPR_EA));
307 stm_usb.epr[ep].r = epr;
308 ao_arch_release_interrupts();
309 debug ("writing epr[%d] 0x%04x wrote 0x%04x\n",
310 ep, epr, stm_usb.epr[ep].r);
314 ao_usb_init_btable(void)
316 ao_usb_sram_addr = 0;
318 ao_usb_bdt = (void *) stm_usb_sram;
320 ao_usb_sram_addr += 8 * STM_USB_BDT_SIZE;
322 /* Set up EP 0 - a Control end point with 32 bytes of in and out buffers */
324 ao_usb_bdt[0].single.addr_tx = ao_usb_sram_addr;
325 ao_usb_bdt[0].single.count_tx = 0;
326 ao_usb_ep0_tx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
327 ao_usb_sram_addr += AO_USB_CONTROL_SIZE;
329 ao_usb_bdt[0].single.addr_rx = ao_usb_sram_addr;
330 ao_usb_bdt[0].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
331 (((AO_USB_CONTROL_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
332 ao_usb_ep0_rx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
333 ao_usb_sram_addr += AO_USB_CONTROL_SIZE;
342 ao_usb_init_btable();
344 /* buffer table is at the start of USB memory */
347 ao_usb_init_ep(AO_USB_CONTROL_EPR, AO_USB_CONTROL_EP,
348 STM_USB_EPR_EP_TYPE_CONTROL,
349 STM_USB_EPR_STAT_RX_VALID,
350 STM_USB_EPR_STAT_TX_NAK);
352 /* Clear all of the other endpoints */
353 for (e = 1; e < 8; e++) {
355 STM_USB_EPR_EP_TYPE_CONTROL,
356 STM_USB_EPR_STAT_RX_DISABLED,
357 STM_USB_EPR_STAT_TX_DISABLED);
360 ao_usb_set_address(0);
364 ao_usb_set_configuration(void)
366 debug ("ao_usb_set_configuration\n");
368 /* Set up the INT end point */
369 ao_usb_bdt[AO_USB_INT_EPR].single.addr_tx = ao_usb_sram_addr;
370 ao_usb_bdt[AO_USB_INT_EPR].single.count_tx = 0;
371 ao_usb_in_tx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
372 ao_usb_sram_addr += AO_USB_INT_SIZE;
374 ao_usb_init_ep(AO_USB_INT_EPR,
376 STM_USB_EPR_EP_TYPE_INTERRUPT,
377 STM_USB_EPR_STAT_RX_DISABLED,
378 STM_USB_EPR_STAT_TX_NAK);
380 /* Set up the OUT end point */
381 ao_usb_bdt[AO_USB_OUT_EPR].single.addr_rx = ao_usb_sram_addr;
382 ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
383 (((AO_USB_OUT_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
384 ao_usb_out_rx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
385 ao_usb_sram_addr += AO_USB_OUT_SIZE;
387 ao_usb_init_ep(AO_USB_OUT_EPR,
389 STM_USB_EPR_EP_TYPE_BULK,
390 STM_USB_EPR_STAT_RX_VALID,
391 STM_USB_EPR_STAT_TX_DISABLED);
393 /* Set up the IN end point */
394 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_sram_addr;
395 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = 0;
396 ao_usb_in_tx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
397 ao_usb_sram_addr += AO_USB_IN_SIZE;
399 ao_usb_init_ep(AO_USB_IN_EPR,
401 STM_USB_EPR_EP_TYPE_BULK,
402 STM_USB_EPR_STAT_RX_DISABLED,
403 STM_USB_EPR_STAT_TX_NAK);
408 static uint16_t control_count;
409 static uint16_t int_count;
410 static uint16_t in_count;
411 static uint16_t out_count;
412 static uint16_t reset_count;
414 /* The USB memory must be accessed in 16-bit units
418 ao_usb_write(const uint8_t *src, uint16_t *base, uint16_t bytes)
421 *base++ = src[0] | (src[1] << 8);
430 ao_usb_read(uint8_t *dst, uint16_t *base, uint16_t bytes)
433 uint16_t s = *base++;
443 /* Send an IN data packet */
445 ao_usb_ep0_flush(void)
449 /* Check to see if the endpoint is still busy */
450 if (ao_usb_epr_stat_tx(stm_usb.epr[0].r) == STM_USB_EPR_STAT_TX_VALID) {
451 debug("EP0 not accepting IN data\n");
455 this_len = ao_usb_ep0_in_len;
456 if (this_len > AO_USB_CONTROL_SIZE)
457 this_len = AO_USB_CONTROL_SIZE;
459 if (this_len < AO_USB_CONTROL_SIZE)
460 ao_usb_ep0_state = AO_USB_EP0_IDLE;
462 ao_usb_ep0_in_len -= this_len;
464 debug_data ("Flush EP0 len %d:", this_len);
465 ao_usb_write(ao_usb_ep0_in_data, ao_usb_ep0_tx_buffer, this_len);
467 ao_usb_ep0_in_data += this_len;
469 /* Mark the endpoint as TX valid to send the packet */
470 ao_usb_bdt[AO_USB_CONTROL_EPR].single.count_tx = this_len;
471 ao_usb_set_stat_tx(AO_USB_CONTROL_EPR, STM_USB_EPR_STAT_TX_VALID);
472 debug ("queue tx. epr 0 now %08x\n", stm_usb.epr[AO_USB_CONTROL_EPR]);
475 /* Read data from the ep0 OUT fifo */
477 ao_usb_ep0_fill(void)
479 uint16_t len = ao_usb_bdt[0].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
481 if (len > ao_usb_ep0_out_len)
482 len = ao_usb_ep0_out_len;
483 ao_usb_ep0_out_len -= len;
485 /* Pull all of the data out of the packet */
486 debug_data ("Fill EP0 len %d:", len);
487 ao_usb_read(ao_usb_ep0_out_data, ao_usb_ep0_rx_buffer, len);
489 ao_usb_ep0_out_data += len;
492 ao_usb_set_stat_rx(0, STM_USB_EPR_STAT_RX_VALID);
496 ao_usb_ep0_in_reset(void)
498 ao_usb_ep0_in_data = ao_usb_ep0_in_buf;
499 ao_usb_ep0_in_len = 0;
503 ao_usb_ep0_in_queue_byte(uint8_t a)
505 if (ao_usb_ep0_in_len < sizeof (ao_usb_ep0_in_buf))
506 ao_usb_ep0_in_buf[ao_usb_ep0_in_len++] = a;
510 ao_usb_ep0_in_set(const uint8_t *data, uint8_t len)
512 ao_usb_ep0_in_data = data;
513 ao_usb_ep0_in_len = len;
517 ao_usb_ep0_out_set(uint8_t *data, uint8_t len)
519 ao_usb_ep0_out_data = data;
520 ao_usb_ep0_out_len = len;
524 ao_usb_ep0_in_start(uint16_t max)
526 /* Don't send more than asked for */
527 if (ao_usb_ep0_in_len > max)
528 ao_usb_ep0_in_len = max;
532 static struct ao_usb_line_coding ao_usb_line_coding = {115200, 0, 0, 8};
534 /* Walk through the list of descriptors and find a match
537 ao_usb_get_descriptor(uint16_t value)
539 const uint8_t *descriptor;
540 uint8_t type = value >> 8;
541 uint8_t index = value;
543 descriptor = ao_usb_descriptors;
544 while (descriptor[0] != 0) {
545 if (descriptor[1] == type && index-- == 0) {
547 if (type == AO_USB_DESC_CONFIGURATION)
551 ao_usb_ep0_in_set(descriptor, len);
554 descriptor += descriptor[0];
559 ao_usb_ep0_setup(void)
561 /* Pull the setup packet out of the fifo */
562 ao_usb_ep0_out_set((uint8_t *) &ao_usb_setup, 8);
564 if (ao_usb_ep0_out_len != 0) {
565 debug ("invalid setup packet length\n");
569 if ((ao_usb_setup.dir_type_recip & AO_USB_DIR_IN) || ao_usb_setup.length == 0)
570 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
572 ao_usb_ep0_state = AO_USB_EP0_DATA_OUT;
574 ao_usb_ep0_in_reset();
576 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_TYPE_MASK) {
577 case AO_USB_TYPE_STANDARD:
578 debug ("Standard setup packet\n");
579 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_RECIP_MASK) {
580 case AO_USB_RECIP_DEVICE:
581 debug ("Device setup packet\n");
582 switch(ao_usb_setup.request) {
583 case AO_USB_REQ_GET_STATUS:
584 debug ("get status\n");
585 ao_usb_ep0_in_queue_byte(0);
586 ao_usb_ep0_in_queue_byte(0);
588 case AO_USB_REQ_SET_ADDRESS:
589 debug ("set address %d\n", ao_usb_setup.value);
590 ao_usb_address = ao_usb_setup.value;
591 ao_usb_address_pending = 1;
593 case AO_USB_REQ_GET_DESCRIPTOR:
594 debug ("get descriptor %d\n", ao_usb_setup.value);
595 ao_usb_get_descriptor(ao_usb_setup.value);
597 case AO_USB_REQ_GET_CONFIGURATION:
598 debug ("get configuration %d\n", ao_usb_configuration);
599 ao_usb_ep0_in_queue_byte(ao_usb_configuration);
601 case AO_USB_REQ_SET_CONFIGURATION:
602 ao_usb_configuration = ao_usb_setup.value;
603 debug ("set configuration %d\n", ao_usb_configuration);
604 ao_usb_set_configuration();
608 case AO_USB_RECIP_INTERFACE:
609 debug ("Interface setup packet\n");
610 switch(ao_usb_setup.request) {
611 case AO_USB_REQ_GET_STATUS:
612 ao_usb_ep0_in_queue_byte(0);
613 ao_usb_ep0_in_queue_byte(0);
615 case AO_USB_REQ_GET_INTERFACE:
616 ao_usb_ep0_in_queue_byte(0);
618 case AO_USB_REQ_SET_INTERFACE:
622 case AO_USB_RECIP_ENDPOINT:
623 debug ("Endpoint setup packet\n");
624 switch(ao_usb_setup.request) {
625 case AO_USB_REQ_GET_STATUS:
626 ao_usb_ep0_in_queue_byte(0);
627 ao_usb_ep0_in_queue_byte(0);
633 case AO_USB_TYPE_CLASS:
634 debug ("Class setup packet\n");
635 switch (ao_usb_setup.request) {
636 case AO_USB_SET_LINE_CODING:
637 debug ("set line coding\n");
638 ao_usb_ep0_out_set((uint8_t *) &ao_usb_line_coding, 7);
640 case AO_USB_GET_LINE_CODING:
641 debug ("get line coding\n");
642 ao_usb_ep0_in_set((const uint8_t *) &ao_usb_line_coding, 7);
644 case AO_USB_SET_CONTROL_LINE_STATE:
650 /* If we're not waiting to receive data from the host,
651 * queue an IN response
653 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
654 ao_usb_ep0_in_start(ao_usb_setup.length);
658 ao_usb_ep0_handle(uint8_t receive)
660 ao_usb_ep0_receive = 0;
661 if (receive & AO_USB_EP0_GOT_RESET) {
666 if (receive & AO_USB_EP0_GOT_SETUP) {
670 if (receive & AO_USB_EP0_GOT_RX_DATA) {
671 debug ("\tgot rx data\n");
672 if (ao_usb_ep0_state == AO_USB_EP0_DATA_OUT) {
674 if (ao_usb_ep0_out_len == 0) {
675 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
676 ao_usb_ep0_in_start(0);
680 if (receive & AO_USB_EP0_GOT_TX_ACK) {
681 debug ("\tgot tx ack\n");
683 #if HAS_FLIGHT && AO_USB_FORCE_IDLE
684 ao_flight_force_idle = 1;
686 /* Wait until the IN packet is received from addr 0
687 * before assigning our local address
689 if (ao_usb_address_pending)
690 ao_usb_set_address(ao_usb_address);
691 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
699 uint32_t istr = stm_usb.istr;
701 stm_usb.istr = ~istr;
702 if (istr & (1 << STM_USB_ISTR_CTR)) {
703 uint8_t ep = istr & STM_USB_ISTR_EP_ID_MASK;
704 uint16_t epr, epr_write;
706 /* Preserve the SW write bits, don't mess with most HW writable bits,
707 * clear the CTR_RX and CTR_TX bits
709 epr = stm_usb.epr[ep].r;
711 epr_write &= STM_USB_EPR_PRESERVE_MASK;
712 epr_write |= STM_USB_EPR_INVARIANT;
713 epr_write &= ~(1 << STM_USB_EPR_CTR_RX);
714 epr_write &= ~(1 << STM_USB_EPR_CTR_TX);
715 stm_usb.epr[ep].r = epr_write;
720 if (ao_usb_epr_ctr_rx(epr)) {
721 if (ao_usb_epr_setup(epr))
722 ao_usb_ep0_receive |= AO_USB_EP0_GOT_SETUP;
724 ao_usb_ep0_receive |= AO_USB_EP0_GOT_RX_DATA;
726 if (ao_usb_epr_ctr_tx(epr))
727 ao_usb_ep0_receive |= AO_USB_EP0_GOT_TX_ACK;
728 ao_usb_ep0_handle(ao_usb_ep0_receive);
732 if (ao_usb_epr_ctr_rx(epr)) {
733 _rx_dbg1("RX ISR", epr);
734 ao_usb_out_avail = 1;
735 _rx_dbg0("out avail set");
736 ao_wakeup(AO_USB_OUT_SLEEP_ADDR);
737 _rx_dbg0("stdin awoken");
742 _tx_dbg1("TX ISR", epr);
743 if (ao_usb_epr_ctr_tx(epr)) {
744 ao_usb_in_pending = 0;
745 ao_wakeup(&ao_usb_in_pending);
750 if (ao_usb_epr_ctr_tx(epr))
751 _ao_usb_set_stat_tx(AO_USB_INT_EPR, STM_USB_EPR_STAT_TX_NAK);
757 if (istr & (1 << STM_USB_ISTR_RESET)) {
759 ao_usb_ep0_receive |= AO_USB_EP0_GOT_RESET;
760 ao_usb_ep0_handle(ao_usb_ep0_receive);
765 /* Queue the current IN buffer for transmission */
767 _ao_usb_in_send(void)
769 _tx_dbg0("in_send start");
770 debug ("send %d\n", ao_usb_tx_count);
771 while (ao_usb_in_pending)
772 ao_sleep(&ao_usb_in_pending);
773 ao_usb_in_pending = 1;
774 if (ao_usb_tx_count != AO_USB_IN_SIZE)
775 ao_usb_in_flushed = 1;
776 ao_usb_write(ao_usb_tx_buffer, ao_usb_in_tx_buffer, ao_usb_tx_count);
777 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = ao_usb_tx_count;
779 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
780 _tx_dbg0("in_send end");
783 /* Wait for a free IN buffer. Interrupts are blocked */
785 _ao_usb_in_wait(void)
788 /* Check if the current buffer is writable */
789 if (ao_usb_tx_count < AO_USB_IN_SIZE)
792 _tx_dbg0("in_wait top");
793 /* Wait for an IN buffer to be ready */
794 while (ao_usb_in_pending)
795 ao_sleep(&ao_usb_in_pending);
796 _tx_dbg0("in_wait bottom");
806 /* Anytime we've sent a character since
807 * the last time we flushed, we'll need
808 * to send a packet -- the only other time
809 * we would send a packet is when that
810 * packet was full, in which case we now
811 * want to send an empty packet
813 ao_arch_block_interrupts();
814 while (!ao_usb_in_flushed) {
815 _tx_dbg0("flush top");
817 _tx_dbg0("flush end");
819 ao_arch_release_interrupts();
823 ao_usb_putchar(char c)
828 ao_arch_block_interrupts();
831 ao_usb_in_flushed = 0;
832 ao_usb_tx_buffer[ao_usb_tx_count++] = (uint8_t) c;
834 /* Send the packet when full */
835 if (ao_usb_tx_count == AO_USB_IN_SIZE) {
836 _tx_dbg0("putchar full");
838 _tx_dbg0("putchar flushed");
840 ao_arch_release_interrupts();
844 _ao_usb_out_recv(void)
846 _rx_dbg0("out_recv top");
847 ao_usb_out_avail = 0;
849 ao_usb_rx_count = ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
851 _rx_dbg1("out_recv count", ao_usb_rx_count);
852 debug ("recv %d\n", ao_usb_rx_count);
853 debug_data("Fill OUT len %d:", ao_usb_rx_count);
854 ao_usb_read(ao_usb_rx_buffer, ao_usb_out_rx_buffer, ao_usb_rx_count);
859 _ao_usb_set_stat_rx(AO_USB_OUT_EPR, STM_USB_EPR_STAT_RX_VALID);
863 _ao_usb_pollchar(void)
868 return AO_READ_AGAIN;
871 if (ao_usb_rx_pos != ao_usb_rx_count)
874 _rx_dbg0("poll check");
875 /* Check to see if a packet has arrived */
876 if (!ao_usb_out_avail) {
877 _rx_dbg0("poll none");
878 return AO_READ_AGAIN;
883 /* Pull a character out of the fifo */
884 c = ao_usb_rx_buffer[ao_usb_rx_pos++];
893 ao_arch_block_interrupts();
894 while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN)
895 ao_sleep(AO_USB_OUT_SLEEP_ADDR);
896 ao_arch_release_interrupts();
903 ao_arch_block_interrupts();
904 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
907 /* Disable USB pull-up */
908 stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
910 /* Switch off the device */
911 stm_usb.cntr = (1 << STM_USB_CNTR_PDWN) | (1 << STM_USB_CNTR_FRES);
913 /* Disable the interface */
914 stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_USBEN);
915 ao_arch_release_interrupts();
923 /* Select HSI48 as USB clock source */
924 stm_rcc.cfgr3 &= ~(1 << STM_RCC_CFGR3_USBSW);
926 /* Enable USB device */
927 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USBEN);
929 /* Clear reset condition */
930 stm_rcc.apb1rstr &= ~(1 << STM_RCC_APB1RSTR_USBRST);
932 /* Disable USB pull-up */
933 stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
935 /* Do not touch the GPIOA configuration; USB takes priority
936 * over GPIO on pins A11 and A12, but if you select alternate
937 * input 10 (the documented correct selection), then USB is
938 * pulled low and doesn't work at all
941 ao_arch_block_interrupts();
943 /* Route interrupts */
944 stm_nvic_set_enable(STM_ISR_USB_POS);
945 stm_nvic_set_priority(STM_ISR_USB_POS, 3);
947 ao_usb_configuration = 0;
949 /* Set up buffer descriptors */
950 ao_usb_init_btable();
952 /* Reset the USB controller */
953 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
955 /* Clear the reset bit */
958 /* Clear any spurious interrupts */
963 debug ("ao_usb_enable\n");
965 /* Enable interrupts */
966 stm_usb.cntr = ((1 << STM_USB_CNTR_CTRM) |
967 (0 << STM_USB_CNTR_PMAOVRM) |
968 (0 << STM_USB_CNTR_ERRM) |
969 (0 << STM_USB_CNTR_WKUPM) |
970 (0 << STM_USB_CNTR_SUSPM) |
971 (1 << STM_USB_CNTR_RESETM) |
972 (0 << STM_USB_CNTR_SOFM) |
973 (0 << STM_USB_CNTR_ESOFM) |
974 (0 << STM_USB_CNTR_RESUME) |
975 (0 << STM_USB_CNTR_FSUSP) |
976 (0 << STM_USB_CNTR_LP_MODE) |
977 (0 << STM_USB_CNTR_PDWN) |
978 (0 << STM_USB_CNTR_FRES));
980 ao_arch_release_interrupts();
982 for (t = 0; t < 1000; t++)
985 /* Enable USB pull-up */
986 stm_usb.bcdr |= (1 << STM_USB_BCDR_DPPU);
990 struct ao_task ao_usb_echo_task;
998 c = ao_usb_getchar();
1009 printf ("control: %d out: %d in: %d int: %d reset: %d\n",
1010 control_count, out_count, in_count, int_count, reset_count);
1013 __code struct ao_cmds ao_usb_cmds[] = {
1014 { ao_usb_irq, "I\0Show USB interrupt counts" },
1024 debug ("ao_usb_init\n");
1025 ao_usb_ep0_state = AO_USB_EP0_IDLE;
1027 ao_add_task(&ao_usb_echo_task, ao_usb_echo, "usb echo");
1030 ao_cmd_register(&ao_usb_cmds[0]);
1034 ao_add_stdio(_ao_usb_pollchar, ao_usb_putchar, ao_usb_flush);
1039 #if TX_DBG || RX_DBG
1049 uint32_t in_pending;
1051 uint32_t in_flushed;
1061 #define NUM_USB_DBG 128
1063 static struct ao_usb_dbg dbg[128];
1066 static void _dbg(int line, char *msg, uint32_t value)
1069 dbg[dbg_i].line = line;
1070 dbg[dbg_i].msg = msg;
1071 dbg[dbg_i].value = value;
1072 asm("mrs %0,primask" : "=&r" (primask));
1073 dbg[dbg_i].primask = primask;
1075 dbg[dbg_i].in_count = in_count;
1076 dbg[dbg_i].in_epr = stm_usb.epr[AO_USB_IN_EPR];
1077 dbg[dbg_i].in_pending = ao_usb_in_pending;
1078 dbg[dbg_i].tx_count = ao_usb_tx_count;
1079 dbg[dbg_i].in_flushed = ao_usb_in_flushed;
1082 dbg[dbg_i].rx_count = ao_usb_rx_count;
1083 dbg[dbg_i].rx_pos = ao_usb_rx_pos;
1084 dbg[dbg_i].out_avail = ao_usb_out_avail;
1085 dbg[dbg_i].out_epr = stm_usb.epr[AO_USB_OUT_EPR];
1087 if (++dbg_i == NUM_USB_DBG)