2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 #include "ao_product.h"
25 #define USB_DEBUG_DATA 0
28 #ifndef AO_PA11_PA12_RMP
29 #error "must define AO_PA11_PA12_RMP"
32 #ifndef AO_POWER_MANAGEMENT
33 #define AO_POWER_MANAGEMENT 0
37 #define USE_USB_STDIO 1
41 #define AO_USB_OUT_SLEEP_ADDR (&ao_stdin_ready)
43 #define AO_USB_OUT_SLEEP_ADDR (&ao_usb_out_avail)
47 #define debug(format, args...) printf(format, ## args);
49 #define debug(format, args...)
53 #define debug_data(format, args...) printf(format, ## args);
55 #define debug_data(format, args...)
59 uint8_t dir_type_recip;
66 static uint8_t ao_usb_ep0_state;
68 /* Pending EP0 IN data */
69 static const uint8_t *ao_usb_ep0_in_data; /* Remaining data */
70 static uint8_t ao_usb_ep0_in_len; /* Remaining amount */
72 /* Temp buffer for smaller EP0 in data */
73 static uint8_t ao_usb_ep0_in_buf[2];
75 /* Pending EP0 OUT data */
76 static uint8_t *ao_usb_ep0_out_data;
77 static uint8_t ao_usb_ep0_out_len;
80 * Objects allocated in special USB memory
83 /* Buffer description tables */
84 static union stm_usb_bdt *ao_usb_bdt;
85 /* USB address of end of allocated storage */
86 static uint16_t ao_usb_sram_addr;
88 /* Pointer to ep0 tx/rx buffers in USB memory */
89 static uint16_t *ao_usb_ep0_tx_buffer;
90 static uint16_t *ao_usb_ep0_rx_buffer;
92 /* Pointer to interrupt buffer in USB memory */
93 static uint16_t ao_usb_int_tx_offset;
95 /* Pointer to bulk data tx/rx buffers in USB memory */
96 static uint16_t ao_usb_in_tx_offset;
97 static uint16_t *ao_usb_in_tx_buffer;
98 static uint16_t ao_usb_out_rx_offset;
99 static uint16_t *ao_usb_out_rx_buffer;
101 /* System ram shadow of USB buffer; writing individual bytes is
102 * too much of a pain (sigh) */
103 static uint8_t ao_usb_tx_buffer[AO_USB_IN_SIZE];
104 static uint8_t ao_usb_tx_count;
106 static uint8_t ao_usb_rx_buffer[AO_USB_OUT_SIZE];
107 static uint8_t ao_usb_rx_count, ao_usb_rx_pos;
110 * End point register indices
113 #define AO_USB_CONTROL_EPR 0
114 #define AO_USB_INT_EPR 1
115 #define AO_USB_OUT_EPR 2
116 #define AO_USB_IN_EPR 3
118 /* Marks when we don't need to send an IN packet.
119 * This happens only when the last IN packet is not full,
120 * otherwise the host will expect to keep seeing packets.
121 * Send a zero-length packet as required
123 static uint8_t ao_usb_in_flushed;
125 /* Marks when we have delivered an IN packet to the hardware
126 * and it has not been received yet. ao_sleep on this address
127 * to wait for it to be delivered.
129 static uint8_t ao_usb_in_pending;
131 /* Marks when an OUT packet has been received by the hardware
132 * but not pulled to the shadow buffer.
134 static uint8_t ao_usb_out_avail;
135 uint8_t ao_usb_running;
136 static uint8_t ao_usb_configuration;
138 #define AO_USB_EP0_GOT_SETUP 1
139 #define AO_USB_EP0_GOT_RX_DATA 2
140 #define AO_USB_EP0_GOT_TX_ACK 4
142 static uint8_t ao_usb_ep0_receive;
143 static uint8_t ao_usb_address;
144 static uint8_t ao_usb_address_pending;
146 static inline uint32_t set_toggle(uint32_t current_value,
148 uint32_t desired_value)
150 return (current_value ^ desired_value) & mask;
153 static inline uint16_t *ao_usb_packet_buffer_addr(uint16_t sram_addr)
155 return (uint16_t *) (stm_usb_sram + sram_addr);
158 static inline uint16_t ao_usb_packet_buffer_offset(uint16_t *addr)
160 return (uint16_t) ((uint8_t *) addr - stm_usb_sram);
163 static inline uint32_t ao_usb_epr_stat_rx(uint32_t epr) {
164 return (epr >> STM_USB_EPR_STAT_RX) & STM_USB_EPR_STAT_RX_MASK;
167 static inline uint32_t ao_usb_epr_stat_tx(uint32_t epr) {
168 return (epr >> STM_USB_EPR_STAT_TX) & STM_USB_EPR_STAT_TX_MASK;
171 static inline uint32_t ao_usb_epr_ctr_rx(uint32_t epr) {
172 return (epr >> STM_USB_EPR_CTR_RX) & 1;
175 static inline uint32_t ao_usb_epr_ctr_tx(uint32_t epr) {
176 return (epr >> STM_USB_EPR_CTR_TX) & 1;
179 static inline uint32_t ao_usb_epr_setup(uint32_t epr) {
180 return (epr >> STM_USB_EPR_SETUP) & 1;
183 static inline uint32_t ao_usb_epr_dtog_rx(uint32_t epr) {
184 return (epr >> STM_USB_EPR_DTOG_RX) & 1;
187 static inline uint32_t ao_usb_epr_dtog_tx(uint32_t epr) {
188 return (epr >> STM_USB_EPR_DTOG_TX) & 1;
192 * Set current device address and mark the
193 * interface as active
196 ao_usb_set_address(uint8_t address)
198 debug("ao_usb_set_address %02x\n", address);
199 stm_usb.daddr = (1 << STM_USB_DADDR_EF) | address;
200 ao_usb_address_pending = 0;
204 * Write these values to preserve register contents under HW changes
207 #define STM_USB_EPR_INVARIANT ((1 << STM_USB_EPR_CTR_RX) | \
208 (STM_USB_EPR_DTOG_RX_WRITE_INVARIANT << STM_USB_EPR_DTOG_RX) | \
209 (STM_USB_EPR_STAT_RX_WRITE_INVARIANT << STM_USB_EPR_STAT_RX) | \
210 (1 << STM_USB_EPR_CTR_TX) | \
211 (STM_USB_EPR_DTOG_TX_WRITE_INVARIANT << STM_USB_EPR_DTOG_TX) | \
212 (STM_USB_EPR_STAT_TX_WRITE_INVARIANT << STM_USB_EPR_STAT_TX))
214 #define STM_USB_EPR_INVARIANT_MASK ((1 << STM_USB_EPR_CTR_RX) | \
215 (STM_USB_EPR_DTOG_RX_MASK << STM_USB_EPR_DTOG_RX) | \
216 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) | \
217 (1 << STM_USB_EPR_CTR_TX) | \
218 (STM_USB_EPR_DTOG_TX_MASK << STM_USB_EPR_DTOG_TX) | \
219 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX))
222 * These bits are purely under sw control, so preserve them in the
223 * register by re-writing what was read
225 #define STM_USB_EPR_PRESERVE_MASK ((STM_USB_EPR_EP_TYPE_MASK << STM_USB_EPR_EP_TYPE) | \
226 (1 << STM_USB_EPR_EP_KIND) | \
227 (STM_USB_EPR_EA_MASK << STM_USB_EPR_EA))
233 #define _tx_dbg0(msg) _dbg(__LINE__,msg,0)
234 #define _tx_dbg1(msg,value) _dbg(__LINE__,msg,value)
236 #define _tx_dbg0(msg)
237 #define _tx_dbg1(msg,value)
241 #define _rx_dbg0(msg) _dbg(__LINE__,msg,0)
242 #define _rx_dbg1(msg,value) _dbg(__LINE__,msg,value)
244 #define _rx_dbg0(msg)
245 #define _rx_dbg1(msg,value)
249 static void _dbg(int line, char *msg, uint32_t value);
253 * Set the state of the specified endpoint register to a new
254 * value. This is tricky because the bits toggle where the new
255 * value is one, and we need to write invariant values in other
256 * spots of the register. This hardware is strange...
259 _ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
261 uint16_t epr_write, epr_old;
263 _tx_dbg1("set_stat_tx top", stat_tx);
264 epr_old = epr_write = stm_usb.epr[ep].r;
265 epr_write &= STM_USB_EPR_PRESERVE_MASK;
266 epr_write |= STM_USB_EPR_INVARIANT;
267 epr_write |= set_toggle(epr_old,
268 STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX,
269 stat_tx << STM_USB_EPR_STAT_TX);
270 stm_usb.epr[ep].r = epr_write;
271 _tx_dbg1("set_stat_tx bottom", epr_write);
275 ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
277 ao_arch_block_interrupts();
278 _ao_usb_set_stat_tx(ep, stat_tx);
279 ao_arch_release_interrupts();
283 _ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
284 uint16_t epr_write, epr_old;
286 epr_write = epr_old = stm_usb.epr[ep].r;
287 epr_write &= STM_USB_EPR_PRESERVE_MASK;
288 epr_write |= STM_USB_EPR_INVARIANT;
289 epr_write |= set_toggle(epr_old,
290 STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX,
291 stat_rx << STM_USB_EPR_STAT_RX);
292 stm_usb.epr[ep].r = epr_write;
296 ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
297 ao_arch_block_interrupts();
298 _ao_usb_set_stat_rx(ep, stat_rx);
299 ao_arch_release_interrupts();
303 * Set just endpoint 0, for use during startup
307 ao_usb_init_ep(uint8_t ep, uint32_t addr, uint32_t type, uint32_t stat_rx, uint32_t stat_tx)
311 ao_arch_block_interrupts();
312 epr = stm_usb.epr[ep].r;
313 epr = ((0 << STM_USB_EPR_CTR_RX) |
314 (epr & (1 << STM_USB_EPR_DTOG_RX)) |
316 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX),
317 (stat_rx << STM_USB_EPR_STAT_RX)) |
318 (type << STM_USB_EPR_EP_TYPE) |
319 (0 << STM_USB_EPR_EP_KIND) |
320 (0 << STM_USB_EPR_CTR_TX) |
321 (epr & (1 << STM_USB_EPR_DTOG_TX)) |
323 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX),
324 (stat_tx << STM_USB_EPR_STAT_TX)) |
325 (addr << STM_USB_EPR_EA));
326 stm_usb.epr[ep].r = epr;
327 ao_arch_release_interrupts();
328 debug ("writing epr[%d] 0x%04x wrote 0x%04x\n",
329 ep, epr, stm_usb.epr[ep].r);
333 ao_usb_alloc_buffers(void)
335 ao_usb_sram_addr = 0;
337 ao_usb_bdt = (void *) stm_usb_sram;
338 ao_usb_sram_addr += 8 * STM_USB_BDT_SIZE;
340 ao_usb_ep0_tx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
341 ao_usb_sram_addr += AO_USB_CONTROL_SIZE;
343 ao_usb_ep0_rx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
344 ao_usb_sram_addr += AO_USB_CONTROL_SIZE;
346 ao_usb_int_tx_offset = ao_usb_sram_addr;
347 ao_usb_sram_addr += AO_USB_INT_SIZE;
349 ao_usb_out_rx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
350 ao_usb_out_rx_offset = ao_usb_sram_addr;
351 ao_usb_sram_addr += AO_USB_OUT_SIZE;
353 ao_usb_in_tx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
354 ao_usb_in_tx_offset = ao_usb_sram_addr;
355 ao_usb_sram_addr += AO_USB_IN_SIZE;
359 ao_usb_init_btable(void)
361 /* Set up EP 0 - a Control end point with 32 bytes of in and out buffers */
363 ao_usb_bdt[0].single.addr_tx = ao_usb_packet_buffer_offset(ao_usb_ep0_tx_buffer);
364 ao_usb_bdt[0].single.count_tx = 0;
366 ao_usb_bdt[0].single.addr_rx = ao_usb_packet_buffer_offset(ao_usb_ep0_rx_buffer);
367 ao_usb_bdt[0].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
368 (((AO_USB_CONTROL_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
376 ao_usb_init_btable();
378 /* buffer table is at the start of USB memory */
381 ao_usb_init_ep(AO_USB_CONTROL_EPR, AO_USB_CONTROL_EP,
382 STM_USB_EPR_EP_TYPE_CONTROL,
383 STM_USB_EPR_STAT_RX_VALID,
384 STM_USB_EPR_STAT_TX_NAK);
386 /* Clear all of the other endpoints */
387 for (e = 1; e < 8; e++) {
389 STM_USB_EPR_EP_TYPE_CONTROL,
390 STM_USB_EPR_STAT_RX_DISABLED,
391 STM_USB_EPR_STAT_TX_DISABLED);
394 ao_usb_set_address(0);
400 ao_usb_set_configuration(void)
402 debug ("ao_usb_set_configuration\n");
405 /* Set up the INT end point */
406 ao_usb_bdt[AO_USB_INT_EPR].single.addr_tx = ao_usb_int_tx_offset;
407 ao_usb_bdt[AO_USB_INT_EPR].single.count_tx = 0;
409 ao_usb_init_ep(AO_USB_INT_EPR,
411 STM_USB_EPR_EP_TYPE_INTERRUPT,
412 STM_USB_EPR_STAT_RX_DISABLED,
413 STM_USB_EPR_STAT_TX_NAK);
417 /* Set up the OUT end point */
418 ao_usb_bdt[AO_USB_OUT_EPR].single.addr_rx = ao_usb_out_rx_offset;
419 ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
420 (((AO_USB_OUT_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
422 ao_usb_init_ep(AO_USB_OUT_EPR,
424 STM_USB_EPR_EP_TYPE_BULK,
425 STM_USB_EPR_STAT_RX_VALID,
426 STM_USB_EPR_STAT_TX_DISABLED);
430 /* Set up the IN end point */
431 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_in_tx_offset;
432 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = 0;
434 ao_usb_init_ep(AO_USB_IN_EPR,
436 STM_USB_EPR_EP_TYPE_BULK,
437 STM_USB_EPR_STAT_RX_DISABLED,
438 STM_USB_EPR_STAT_TX_NAK);
443 ao_wakeup(&ao_usb_running);
447 static uint16_t control_count;
448 static uint16_t int_count;
449 static uint16_t in_count;
450 static uint16_t out_count;
451 static uint16_t reset_count;
453 /* The USB memory must be accessed in 16-bit units
457 ao_usb_copy_tx(const uint8_t *src, uint16_t *base, uint16_t bytes)
460 *base++ = src[0] | (src[1] << 8);
469 ao_usb_copy_rx(uint8_t *dst, uint16_t *base, uint16_t bytes)
472 uint16_t s = *base++;
482 /* Send an IN data packet */
484 ao_usb_ep0_flush(void)
488 /* Check to see if the endpoint is still busy */
489 if (ao_usb_epr_stat_tx(stm_usb.epr[0].r) == STM_USB_EPR_STAT_TX_VALID) {
490 debug("EP0 not accepting IN data\n");
494 this_len = ao_usb_ep0_in_len;
495 if (this_len > AO_USB_CONTROL_SIZE)
496 this_len = AO_USB_CONTROL_SIZE;
498 if (this_len < AO_USB_CONTROL_SIZE)
499 ao_usb_ep0_state = AO_USB_EP0_IDLE;
501 ao_usb_ep0_in_len -= this_len;
503 debug_data ("Flush EP0 len %d:", this_len);
504 ao_usb_copy_tx(ao_usb_ep0_in_data, ao_usb_ep0_tx_buffer, this_len);
506 ao_usb_ep0_in_data += this_len;
508 /* Mark the endpoint as TX valid to send the packet */
509 ao_usb_bdt[AO_USB_CONTROL_EPR].single.count_tx = this_len;
510 ao_usb_set_stat_tx(AO_USB_CONTROL_EPR, STM_USB_EPR_STAT_TX_VALID);
511 debug ("queue tx. epr 0 now %08x\n", stm_usb.epr[AO_USB_CONTROL_EPR]);
514 /* Read data from the ep0 OUT fifo */
516 ao_usb_ep0_fill(void)
518 uint16_t len = ao_usb_bdt[0].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
520 if (len > ao_usb_ep0_out_len)
521 len = ao_usb_ep0_out_len;
522 ao_usb_ep0_out_len -= len;
524 /* Pull all of the data out of the packet */
525 debug_data ("Fill EP0 len %d:", len);
526 ao_usb_copy_rx(ao_usb_ep0_out_data, ao_usb_ep0_rx_buffer, len);
528 ao_usb_ep0_out_data += len;
531 ao_usb_set_stat_rx(0, STM_USB_EPR_STAT_RX_VALID);
535 ao_usb_ep0_in_reset(void)
537 ao_usb_ep0_in_data = ao_usb_ep0_in_buf;
538 ao_usb_ep0_in_len = 0;
542 ao_usb_ep0_in_queue_byte(uint8_t a)
544 if (ao_usb_ep0_in_len < sizeof (ao_usb_ep0_in_buf))
545 ao_usb_ep0_in_buf[ao_usb_ep0_in_len++] = a;
549 ao_usb_ep0_in_set(const uint8_t *data, uint8_t len)
551 ao_usb_ep0_in_data = data;
552 ao_usb_ep0_in_len = len;
556 ao_usb_ep0_out_set(uint8_t *data, uint8_t len)
558 ao_usb_ep0_out_data = data;
559 ao_usb_ep0_out_len = len;
563 ao_usb_ep0_in_start(uint16_t max)
565 /* Don't send more than asked for */
566 if (ao_usb_ep0_in_len > max)
567 ao_usb_ep0_in_len = max;
571 static struct ao_usb_line_coding ao_usb_line_coding = {115200, 0, 0, 8};
573 /* Walk through the list of descriptors and find a match
576 ao_usb_get_descriptor(uint16_t value)
578 const uint8_t *descriptor;
579 uint8_t type = value >> 8;
580 uint8_t index = value;
582 descriptor = ao_usb_descriptors;
583 while (descriptor[0] != 0) {
584 if (descriptor[1] == type && index-- == 0) {
586 if (type == AO_USB_DESC_CONFIGURATION)
590 ao_usb_ep0_in_set(descriptor, len);
593 descriptor += descriptor[0];
598 ao_usb_ep0_setup(void)
600 /* Pull the setup packet out of the fifo */
601 ao_usb_ep0_out_set((uint8_t *) &ao_usb_setup, 8);
603 if (ao_usb_ep0_out_len != 0) {
604 debug ("invalid setup packet length\n");
608 if ((ao_usb_setup.dir_type_recip & AO_USB_DIR_IN) || ao_usb_setup.length == 0)
609 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
611 ao_usb_ep0_state = AO_USB_EP0_DATA_OUT;
613 ao_usb_ep0_in_reset();
615 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_TYPE_MASK) {
616 case AO_USB_TYPE_STANDARD:
617 debug ("Standard setup packet\n");
618 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_RECIP_MASK) {
619 case AO_USB_RECIP_DEVICE:
620 debug ("Device setup packet\n");
621 switch(ao_usb_setup.request) {
622 case AO_USB_REQ_GET_STATUS:
623 debug ("get status\n");
624 ao_usb_ep0_in_queue_byte(0);
625 ao_usb_ep0_in_queue_byte(0);
627 case AO_USB_REQ_SET_ADDRESS:
628 debug ("set address %d\n", ao_usb_setup.value);
629 ao_usb_address = ao_usb_setup.value;
630 ao_usb_address_pending = 1;
632 case AO_USB_REQ_GET_DESCRIPTOR:
633 debug ("get descriptor %d\n", ao_usb_setup.value);
634 ao_usb_get_descriptor(ao_usb_setup.value);
636 case AO_USB_REQ_GET_CONFIGURATION:
637 debug ("get configuration %d\n", ao_usb_configuration);
638 ao_usb_ep0_in_queue_byte(ao_usb_configuration);
640 case AO_USB_REQ_SET_CONFIGURATION:
641 ao_usb_configuration = ao_usb_setup.value;
642 debug ("set configuration %d\n", ao_usb_configuration);
643 ao_usb_set_configuration();
647 case AO_USB_RECIP_INTERFACE:
648 debug ("Interface setup packet\n");
649 switch(ao_usb_setup.request) {
650 case AO_USB_REQ_GET_STATUS:
651 ao_usb_ep0_in_queue_byte(0);
652 ao_usb_ep0_in_queue_byte(0);
654 case AO_USB_REQ_GET_INTERFACE:
655 ao_usb_ep0_in_queue_byte(0);
657 case AO_USB_REQ_SET_INTERFACE:
661 case AO_USB_RECIP_ENDPOINT:
662 debug ("Endpoint setup packet\n");
663 switch(ao_usb_setup.request) {
664 case AO_USB_REQ_GET_STATUS:
665 ao_usb_ep0_in_queue_byte(0);
666 ao_usb_ep0_in_queue_byte(0);
672 case AO_USB_TYPE_CLASS:
673 debug ("Class setup packet\n");
674 switch (ao_usb_setup.request) {
675 case AO_USB_SET_LINE_CODING:
676 debug ("set line coding\n");
677 ao_usb_ep0_out_set((uint8_t *) &ao_usb_line_coding, 7);
679 case AO_USB_GET_LINE_CODING:
680 debug ("get line coding\n");
681 ao_usb_ep0_in_set((const uint8_t *) &ao_usb_line_coding, 7);
683 case AO_USB_SET_CONTROL_LINE_STATE:
689 /* If we're not waiting to receive data from the host,
690 * queue an IN response
692 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
693 ao_usb_ep0_in_start(ao_usb_setup.length);
697 ao_usb_ep0_handle(uint8_t receive)
699 ao_usb_ep0_receive = 0;
700 if (receive & AO_USB_EP0_GOT_SETUP) {
704 if (receive & AO_USB_EP0_GOT_RX_DATA) {
705 debug ("\tgot rx data\n");
706 if (ao_usb_ep0_state == AO_USB_EP0_DATA_OUT) {
708 if (ao_usb_ep0_out_len == 0) {
709 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
710 ao_usb_ep0_in_start(0);
714 if (receive & AO_USB_EP0_GOT_TX_ACK) {
715 debug ("\tgot tx ack\n");
717 #if HAS_FLIGHT && AO_USB_FORCE_IDLE
718 ao_flight_force_idle = 1;
720 /* Wait until the IN packet is received from addr 0
721 * before assigning our local address
723 if (ao_usb_address_pending)
724 ao_usb_set_address(ao_usb_address);
725 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
730 #if AO_POWER_MANAGEMENT
734 stm_usb.cntr |= (1 << STM_USB_CNTR_FSUSP);
736 stm_usb.cntr |= (1 << STM_USB_CNTR_LP_MODE);
744 stm_usb.cntr &= ~(1 << STM_USB_CNTR_FSUSP);
752 uint32_t istr = stm_usb.istr;
754 stm_usb.istr = ~istr;
755 if (istr & (1 << STM_USB_ISTR_CTR)) {
756 uint8_t ep = istr & STM_USB_ISTR_EP_ID_MASK;
757 uint16_t epr, epr_write;
759 /* Preserve the SW write bits, don't mess with most HW writable bits,
760 * clear the CTR_RX and CTR_TX bits
762 epr = stm_usb.epr[ep].r;
764 epr_write &= STM_USB_EPR_PRESERVE_MASK;
765 epr_write |= STM_USB_EPR_INVARIANT;
766 epr_write &= ~(1 << STM_USB_EPR_CTR_RX);
767 epr_write &= ~(1 << STM_USB_EPR_CTR_TX);
768 stm_usb.epr[ep].r = epr_write;
773 if (ao_usb_epr_ctr_rx(epr)) {
774 if (ao_usb_epr_setup(epr))
775 ao_usb_ep0_receive |= AO_USB_EP0_GOT_SETUP;
777 ao_usb_ep0_receive |= AO_USB_EP0_GOT_RX_DATA;
779 if (ao_usb_epr_ctr_tx(epr))
780 ao_usb_ep0_receive |= AO_USB_EP0_GOT_TX_ACK;
781 ao_usb_ep0_handle(ao_usb_ep0_receive);
785 if (ao_usb_epr_ctr_rx(epr)) {
786 _rx_dbg1("RX ISR", epr);
787 ao_usb_out_avail = 1;
788 _rx_dbg0("out avail set");
789 ao_wakeup(AO_USB_OUT_SLEEP_ADDR);
790 _rx_dbg0("stdin awoken");
795 _tx_dbg1("TX ISR", epr);
796 if (ao_usb_epr_ctr_tx(epr)) {
797 ao_usb_in_pending = 0;
798 ao_wakeup(&ao_usb_in_pending);
803 if (ao_usb_epr_ctr_tx(epr))
804 _ao_usb_set_stat_tx(AO_USB_INT_EPR, STM_USB_EPR_STAT_TX_NAK);
810 if (istr & (1 << STM_USB_ISTR_RESET)) {
815 #if AO_POWER_MANAGEMENT
816 if (istr & (1 << STM_USB_ISTR_SUSP)) {
817 debug ("\tsuspend\n");
820 if (istr & (1 << STM_USB_ISTR_WKUP)) {
821 debug ("\twakeup\n");
827 /* Queue the current IN buffer for transmission */
829 _ao_usb_in_send(void)
831 _tx_dbg0("in_send start");
832 debug ("send %d\n", ao_usb_tx_count);
833 while (ao_usb_in_pending)
834 ao_sleep(&ao_usb_in_pending);
835 ao_usb_in_pending = 1;
836 if (ao_usb_tx_count != AO_USB_IN_SIZE)
837 ao_usb_in_flushed = 1;
838 ao_usb_copy_tx(ao_usb_tx_buffer, ao_usb_in_tx_buffer, ao_usb_tx_count);
839 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_in_tx_offset;
840 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = ao_usb_tx_count;
842 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
843 _tx_dbg0("in_send end");
846 /* Wait for a free IN buffer. Interrupts are blocked */
848 _ao_usb_in_wait(void)
851 /* Check if the current buffer is writable */
852 if (ao_usb_tx_count < AO_USB_IN_SIZE)
855 _tx_dbg0("in_wait top");
856 /* Wait for an IN buffer to be ready */
857 while (ao_usb_in_pending)
858 ao_sleep(&ao_usb_in_pending);
859 _tx_dbg0("in_wait bottom");
869 /* Anytime we've sent a character since
870 * the last time we flushed, we'll need
871 * to send a packet -- the only other time
872 * we would send a packet is when that
873 * packet was full, in which case we now
874 * want to send an empty packet
876 ao_arch_block_interrupts();
877 while (!ao_usb_in_flushed) {
878 _tx_dbg0("flush top");
880 _tx_dbg0("flush end");
882 ao_arch_release_interrupts();
886 ao_usb_putchar(char c)
891 ao_arch_block_interrupts();
894 ao_usb_in_flushed = 0;
895 ao_usb_tx_buffer[ao_usb_tx_count++] = (uint8_t) c;
897 /* Send the packet when full */
898 if (ao_usb_tx_count == AO_USB_IN_SIZE) {
899 _tx_dbg0("putchar full");
901 _tx_dbg0("putchar flushed");
903 ao_arch_release_interrupts();
907 _ao_usb_out_recv(void)
909 _rx_dbg0("out_recv top");
910 ao_usb_out_avail = 0;
912 ao_usb_rx_count = ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
914 _rx_dbg1("out_recv count", ao_usb_rx_count);
915 debug ("recv %d\n", ao_usb_rx_count);
916 debug_data("Fill OUT len %d:", ao_usb_rx_count);
917 ao_usb_copy_rx(ao_usb_rx_buffer, ao_usb_out_rx_buffer, ao_usb_rx_count);
922 _ao_usb_set_stat_rx(AO_USB_OUT_EPR, STM_USB_EPR_STAT_RX_VALID);
926 _ao_usb_pollchar(void)
931 return AO_READ_AGAIN;
934 if (ao_usb_rx_pos != ao_usb_rx_count)
937 _rx_dbg0("poll check");
938 /* Check to see if a packet has arrived */
939 if (!ao_usb_out_avail) {
940 _rx_dbg0("poll none");
941 return AO_READ_AGAIN;
946 /* Pull a character out of the fifo */
947 c = ao_usb_rx_buffer[ao_usb_rx_pos++];
956 ao_arch_block_interrupts();
957 while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN)
958 ao_sleep(AO_USB_OUT_SLEEP_ADDR);
959 ao_arch_release_interrupts();
969 buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
970 ao_usb_sram_addr += AO_USB_IN_SIZE;
975 ao_usb_free(uint16_t *addr)
977 uint16_t offset = ao_usb_packet_buffer_offset(addr);
978 if (offset < ao_usb_sram_addr)
979 ao_usb_sram_addr = offset;
983 ao_usb_write(uint16_t *buffer, uint16_t len)
985 ao_arch_block_interrupts();
987 /* Wait for everything to be ready at the same time */
989 /* Make sure USB is connected */
990 if (!ao_usb_running) {
991 ao_sleep(&ao_usb_running);
995 /* Flush any pending regular I/O */
996 if (ao_usb_tx_count) {
1001 /* Wait for an idle IN buffer */
1002 if (ao_usb_in_pending) {
1003 ao_sleep(&ao_usb_in_pending);
1009 ao_usb_in_pending = 1;
1010 ao_usb_in_flushed = (len != AO_USB_IN_SIZE);
1011 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_packet_buffer_offset(buffer);
1012 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = len;
1013 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
1014 ao_arch_release_interrupts();
1019 ao_usb_disable(void)
1021 ao_arch_block_interrupts();
1022 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1025 /* Disable USB pull-up */
1026 stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
1028 /* Switch off the device */
1029 stm_usb.cntr = (1 << STM_USB_CNTR_PDWN) | (1 << STM_USB_CNTR_FRES);
1031 /* Disable the interface */
1032 stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_USBEN);
1033 ao_arch_release_interrupts();
1041 /* Select HSI48 as USB clock source */
1042 stm_rcc.cfgr3 &= ~(1 << STM_RCC_CFGR3_USBSW);
1044 /* Enable USB device */
1045 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USBEN);
1047 /* Clear reset condition */
1048 stm_rcc.apb1rstr &= ~(1 << STM_RCC_APB1RSTR_USBRST);
1050 /* Disable USB pull-up */
1051 stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
1053 /* Do not touch the GPIOA configuration; USB takes priority
1054 * over GPIO on pins A11 and A12, but if you select alternate
1055 * input 10 (the documented correct selection), then USB is
1056 * pulled low and doesn't work at all
1059 ao_arch_block_interrupts();
1061 /* Route interrupts */
1062 stm_nvic_set_enable(STM_ISR_USB_POS);
1063 stm_nvic_set_priority(STM_ISR_USB_POS, 3);
1065 ao_usb_configuration = 0;
1067 /* Set up buffer descriptors */
1068 ao_usb_init_btable();
1070 /* Reset the USB controller */
1071 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1073 /* Clear the reset bit */
1076 /* Clear any spurious interrupts */
1081 debug ("ao_usb_enable\n");
1083 /* Enable interrupts */
1084 stm_usb.cntr = ((1 << STM_USB_CNTR_CTRM) |
1085 (0 << STM_USB_CNTR_PMAOVRM) |
1086 (0 << STM_USB_CNTR_ERRM) |
1087 (AO_POWER_MANAGEMENT << STM_USB_CNTR_WKUPM) |
1088 (AO_POWER_MANAGEMENT << STM_USB_CNTR_SUSPM) |
1089 (1 << STM_USB_CNTR_RESETM) |
1090 (0 << STM_USB_CNTR_SOFM) |
1091 (0 << STM_USB_CNTR_ESOFM) |
1092 (0 << STM_USB_CNTR_RESUME) |
1093 (0 << STM_USB_CNTR_FSUSP) |
1094 (0 << STM_USB_CNTR_LP_MODE) |
1095 (0 << STM_USB_CNTR_PDWN) |
1096 (0 << STM_USB_CNTR_FRES));
1098 ao_arch_release_interrupts();
1100 for (t = 0; t < 1000; t++)
1103 /* Enable USB pull-up */
1104 stm_usb.bcdr |= (1 << STM_USB_BCDR_DPPU);
1108 struct ao_task ao_usb_echo_task;
1116 c = ao_usb_getchar();
1127 printf ("control: %d out: %d in: %d int: %d reset: %d\n",
1128 control_count, out_count, in_count, int_count, reset_count);
1131 __code struct ao_cmds ao_usb_cmds[] = {
1132 { ao_usb_irq, "I\0Show USB interrupt counts" },
1140 /* Turn on syscfg */
1141 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
1143 /* Set PA11/PA12 remapping bit */
1144 stm_syscfg.cfgr1 |= (AO_PA11_PA12_RMP << STM_SYSCFG_CFGR1_PA11_PA12_RMP);
1148 debug ("ao_usb_init\n");
1149 ao_usb_ep0_state = AO_USB_EP0_IDLE;
1151 ao_usb_alloc_buffers();
1154 ao_add_task(&ao_usb_echo_task, ao_usb_echo, "usb echo");
1157 ao_cmd_register(&ao_usb_cmds[0]);
1161 ao_add_stdio(_ao_usb_pollchar, ao_usb_putchar, ao_usb_flush);
1166 #if TX_DBG || RX_DBG
1176 uint32_t in_pending;
1178 uint32_t in_flushed;
1188 #define NUM_USB_DBG 128
1190 static struct ao_usb_dbg dbg[128];
1193 static void _dbg(int line, char *msg, uint32_t value)
1196 dbg[dbg_i].line = line;
1197 dbg[dbg_i].msg = msg;
1198 dbg[dbg_i].value = value;
1199 asm("mrs %0,primask" : "=&r" (primask));
1200 dbg[dbg_i].primask = primask;
1202 dbg[dbg_i].in_count = in_count;
1203 dbg[dbg_i].in_epr = stm_usb.epr[AO_USB_IN_EPR];
1204 dbg[dbg_i].in_pending = ao_usb_in_pending;
1205 dbg[dbg_i].tx_count = ao_usb_tx_count;
1206 dbg[dbg_i].in_flushed = ao_usb_in_flushed;
1209 dbg[dbg_i].rx_count = ao_usb_rx_count;
1210 dbg[dbg_i].rx_pos = ao_usb_rx_pos;
1211 dbg[dbg_i].out_avail = ao_usb_out_avail;
1212 dbg[dbg_i].out_epr = stm_usb.epr[AO_USB_OUT_EPR];
1214 if (++dbg_i == NUM_USB_DBG)