2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 #include "ao_product.h"
26 #define USB_DEBUG_DATA 0
29 #ifndef AO_PA11_PA12_RMP
30 #error "must define AO_PA11_PA12_RMP"
33 #ifndef AO_POWER_MANAGEMENT
34 #define AO_POWER_MANAGEMENT 0
38 #define USE_USB_STDIO 1
42 #define AO_USB_OUT_SLEEP_ADDR (&ao_stdin_ready)
44 #define AO_USB_OUT_SLEEP_ADDR (&ao_usb_out_avail)
48 #define debug(format, args...) printf(format, ## args);
50 #define debug(format, args...)
54 #define debug_data(format, args...) printf(format, ## args);
56 #define debug_data(format, args...)
60 uint8_t dir_type_recip;
67 static uint8_t ao_usb_ep0_state;
69 /* Pending EP0 IN data */
70 static const uint8_t *ao_usb_ep0_in_data; /* Remaining data */
71 static uint8_t ao_usb_ep0_in_len; /* Remaining amount */
73 /* Temp buffer for smaller EP0 in data */
74 static uint8_t ao_usb_ep0_in_buf[2];
76 /* Pending EP0 OUT data */
77 static uint8_t *ao_usb_ep0_out_data;
78 static uint8_t ao_usb_ep0_out_len;
81 * Objects allocated in special USB memory
84 /* Buffer description tables */
85 static union stm_usb_bdt *ao_usb_bdt;
86 /* USB address of end of allocated storage */
88 static uint16_t ao_usb_sram_addr;
91 /* Pointer to ep0 tx/rx buffers in USB memory */
92 static uint16_t *ao_usb_ep0_tx_buffer;
93 static uint16_t *ao_usb_ep0_rx_buffer;
96 /* Pointer to interrupt buffer in USB memory */
97 static uint16_t ao_usb_int_tx_offset;
100 /* Pointer to bulk data tx/rx buffers in USB memory */
102 static uint16_t ao_usb_in_tx_offset;
103 static uint16_t *ao_usb_in_tx_buffer;
105 /* System ram shadow of USB buffer; writing individual bytes is
106 * too much of a pain (sigh) */
107 static uint8_t ao_usb_tx_buffer[AO_USB_IN_SIZE];
108 static uint8_t ao_usb_tx_count;
112 static uint16_t ao_usb_out_rx_offset;
113 static uint16_t *ao_usb_out_rx_buffer;
115 /* System ram shadow of USB buffer; writing individual bytes is
116 * too much of a pain (sigh) */
117 static uint8_t ao_usb_rx_buffer[AO_USB_OUT_SIZE];
118 static uint8_t ao_usb_rx_count, ao_usb_rx_pos;
122 static uint16_t ao_usb_in2_tx_offset;
123 static uint16_t *ao_usb_in2_tx_buffer;
125 /* System ram shadow of USB buffer; writing individual bytes is
126 * too much of a pain (sigh) */
127 static uint8_t ao_usb_tx2_buffer[AO_USB_IN_SIZE];
128 static uint8_t ao_usb_tx2_count;
132 * End point register indices
135 #define AO_USB_CONTROL_EPR 0
136 #define AO_USB_INT_EPR 1
137 #define AO_USB_OUT_EPR 2
138 #define AO_USB_IN_EPR 3
139 #define AO_USB_IN2_EPR 4
141 /* Marks when we don't need to send an IN packet.
142 * This happens only when the last IN packet is not full,
143 * otherwise the host will expect to keep seeing packets.
144 * Send a zero-length packet as required
146 static uint8_t ao_usb_in_flushed;
148 /* Marks when we have delivered an IN packet to the hardware
149 * and it has not been received yet. ao_sleep on this address
150 * to wait for it to be delivered.
152 static uint8_t ao_usb_in_pending;
155 /* Marks when we have delivered an IN packet to the hardware
156 * and it has not been received yet. ao_sleep on this address
157 * to wait for it to be delivered.
159 static uint8_t ao_usb_in2_pending;
160 static uint16_t in2_count;
161 static uint8_t ao_usb_in2_flushed;
164 /* Marks when an OUT packet has been received by the hardware
165 * but not pulled to the shadow buffer.
167 static uint8_t ao_usb_out_avail;
168 uint8_t ao_usb_running;
169 static uint8_t ao_usb_configuration;
171 #define AO_USB_EP0_GOT_SETUP 1
172 #define AO_USB_EP0_GOT_RX_DATA 2
173 #define AO_USB_EP0_GOT_TX_ACK 4
175 static uint8_t ao_usb_ep0_receive;
176 static uint8_t ao_usb_address;
177 static uint8_t ao_usb_address_pending;
179 static inline uint32_t set_toggle(uint32_t current_value,
181 uint32_t desired_value)
183 return (current_value ^ desired_value) & mask;
186 static inline uint16_t *ao_usb_packet_buffer_addr(uint16_t sram_addr)
188 return (uint16_t *) (void *) (stm_usb_sram + sram_addr);
191 static inline uint16_t ao_usb_packet_buffer_offset(uint16_t *addr)
193 return (uint16_t) ((uint8_t *) addr - stm_usb_sram);
196 static inline uint32_t ao_usb_epr_stat_rx(uint32_t epr) {
197 return (epr >> STM_USB_EPR_STAT_RX) & STM_USB_EPR_STAT_RX_MASK;
200 static inline uint32_t ao_usb_epr_stat_tx(uint32_t epr) {
201 return (epr >> STM_USB_EPR_STAT_TX) & STM_USB_EPR_STAT_TX_MASK;
204 static inline uint32_t ao_usb_epr_ctr_rx(uint32_t epr) {
205 return (epr >> STM_USB_EPR_CTR_RX) & 1;
208 static inline uint32_t ao_usb_epr_ctr_tx(uint32_t epr) {
209 return (epr >> STM_USB_EPR_CTR_TX) & 1;
212 static inline uint32_t ao_usb_epr_setup(uint32_t epr) {
213 return (epr >> STM_USB_EPR_SETUP) & 1;
216 static inline uint32_t ao_usb_epr_dtog_rx(uint32_t epr) {
217 return (epr >> STM_USB_EPR_DTOG_RX) & 1;
220 static inline uint32_t ao_usb_epr_dtog_tx(uint32_t epr) {
221 return (epr >> STM_USB_EPR_DTOG_TX) & 1;
225 * Set current device address and mark the
226 * interface as active
229 ao_usb_set_address(uint8_t address)
231 debug("ao_usb_set_address %02x\n", address);
232 stm_usb.daddr = (1 << STM_USB_DADDR_EF) | address;
233 ao_usb_address_pending = 0;
237 * Write these values to preserve register contents under HW changes
240 #define STM_USB_EPR_INVARIANT ((1 << STM_USB_EPR_CTR_RX) | \
241 (STM_USB_EPR_DTOG_RX_WRITE_INVARIANT << STM_USB_EPR_DTOG_RX) | \
242 (STM_USB_EPR_STAT_RX_WRITE_INVARIANT << STM_USB_EPR_STAT_RX) | \
243 (1 << STM_USB_EPR_CTR_TX) | \
244 (STM_USB_EPR_DTOG_TX_WRITE_INVARIANT << STM_USB_EPR_DTOG_TX) | \
245 (STM_USB_EPR_STAT_TX_WRITE_INVARIANT << STM_USB_EPR_STAT_TX))
247 #define STM_USB_EPR_INVARIANT_MASK ((1 << STM_USB_EPR_CTR_RX) | \
248 (STM_USB_EPR_DTOG_RX_MASK << STM_USB_EPR_DTOG_RX) | \
249 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) | \
250 (1 << STM_USB_EPR_CTR_TX) | \
251 (STM_USB_EPR_DTOG_TX_MASK << STM_USB_EPR_DTOG_TX) | \
252 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX))
255 * These bits are purely under sw control, so preserve them in the
256 * register by re-writing what was read
258 #define STM_USB_EPR_PRESERVE_MASK ((STM_USB_EPR_EP_TYPE_MASK << STM_USB_EPR_EP_TYPE) | \
259 (1 << STM_USB_EPR_EP_KIND) | \
260 (STM_USB_EPR_EA_MASK << STM_USB_EPR_EA))
266 #define _tx_dbg0(msg) _dbg(__LINE__,msg,0)
267 #define _tx_dbg1(msg,value) _dbg(__LINE__,msg,value)
269 #define _tx_dbg0(msg)
270 #define _tx_dbg1(msg,value)
274 #define _rx_dbg0(msg) _dbg(__LINE__,msg,0)
275 #define _rx_dbg1(msg,value) _dbg(__LINE__,msg,value)
277 #define _rx_dbg0(msg)
278 #define _rx_dbg1(msg,value)
282 static void _dbg(int line, char *msg, uint32_t value);
286 * Set the state of the specified endpoint register to a new
287 * value. This is tricky because the bits toggle where the new
288 * value is one, and we need to write invariant values in other
289 * spots of the register. This hardware is strange...
292 _ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
294 uint16_t epr_write, epr_old;
296 _tx_dbg1("set_stat_tx top", stat_tx);
297 epr_old = epr_write = stm_usb.epr[ep].r;
298 epr_write &= STM_USB_EPR_PRESERVE_MASK;
299 epr_write |= STM_USB_EPR_INVARIANT;
300 epr_write |= set_toggle(epr_old,
301 STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX,
302 stat_tx << STM_USB_EPR_STAT_TX);
303 stm_usb.epr[ep].r = epr_write;
304 _tx_dbg1("set_stat_tx bottom", epr_write);
308 ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
310 ao_arch_block_interrupts();
311 _ao_usb_set_stat_tx(ep, stat_tx);
312 ao_arch_release_interrupts();
316 _ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
317 uint16_t epr_write, epr_old;
319 epr_write = epr_old = stm_usb.epr[ep].r;
320 epr_write &= STM_USB_EPR_PRESERVE_MASK;
321 epr_write |= STM_USB_EPR_INVARIANT;
322 epr_write |= set_toggle(epr_old,
323 STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX,
324 stat_rx << STM_USB_EPR_STAT_RX);
325 stm_usb.epr[ep].r = epr_write;
329 ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
330 ao_arch_block_interrupts();
331 _ao_usb_set_stat_rx(ep, stat_rx);
332 ao_arch_release_interrupts();
336 * Set just endpoint 0, for use during startup
340 ao_usb_init_ep(uint8_t ep, uint32_t addr, uint32_t type, uint32_t stat_rx, uint32_t stat_tx)
344 ao_arch_block_interrupts();
345 epr = stm_usb.epr[ep].r;
346 epr = ((0 << STM_USB_EPR_CTR_RX) |
347 (epr & (1 << STM_USB_EPR_DTOG_RX)) |
349 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX),
350 (stat_rx << STM_USB_EPR_STAT_RX)) |
351 (type << STM_USB_EPR_EP_TYPE) |
352 (0 << STM_USB_EPR_EP_KIND) |
353 (0 << STM_USB_EPR_CTR_TX) |
354 (epr & (1 << STM_USB_EPR_DTOG_TX)) |
356 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX),
357 (stat_tx << STM_USB_EPR_STAT_TX)) |
358 (addr << STM_USB_EPR_EA));
359 stm_usb.epr[ep].r = epr;
360 ao_arch_release_interrupts();
361 debug ("writing epr[%d] 0x%04x wrote 0x%04x\n",
362 ep, epr, stm_usb.epr[ep].r);
366 ao_usb_alloc_buffers(void)
368 uint16_t sram_addr = 0;
370 ao_usb_bdt = (void *) stm_usb_sram;
371 sram_addr += 8 * STM_USB_BDT_SIZE;
373 ao_usb_ep0_tx_buffer = ao_usb_packet_buffer_addr(sram_addr);
374 sram_addr += AO_USB_CONTROL_SIZE;
376 ao_usb_ep0_rx_buffer = ao_usb_packet_buffer_addr(sram_addr);
377 sram_addr += AO_USB_CONTROL_SIZE;
381 ao_usb_int_tx_offset = sram_addr;
382 sram_addr += AO_USB_INT_SIZE;
386 ao_usb_out_rx_buffer = ao_usb_packet_buffer_addr(sram_addr);
387 ao_usb_out_rx_offset = sram_addr;
388 sram_addr += AO_USB_OUT_SIZE;
392 ao_usb_in_tx_buffer = ao_usb_packet_buffer_addr(sram_addr);
393 ao_usb_in_tx_offset = sram_addr;
394 sram_addr += AO_USB_IN_SIZE;
398 ao_usb_in2_tx_buffer = ao_usb_packet_buffer_addr(sram_addr);
399 ao_usb_in2_tx_offset = sram_addr;
400 sram_addr += AO_USB_IN_SIZE;
404 ao_usb_sram_addr = sram_addr;
409 ao_usb_init_btable(void)
411 /* Set up EP 0 - a Control end point with 32 bytes of in and out buffers */
413 ao_usb_bdt[0].single.addr_tx = ao_usb_packet_buffer_offset(ao_usb_ep0_tx_buffer);
414 ao_usb_bdt[0].single.count_tx = 0;
416 ao_usb_bdt[0].single.addr_rx = ao_usb_packet_buffer_offset(ao_usb_ep0_rx_buffer);
417 ao_usb_bdt[0].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
418 (((AO_USB_CONTROL_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
426 ao_usb_init_btable();
428 /* buffer table is at the start of USB memory */
431 ao_usb_init_ep(AO_USB_CONTROL_EPR, AO_USB_CONTROL_EP,
432 STM_USB_EPR_EP_TYPE_CONTROL,
433 STM_USB_EPR_STAT_RX_VALID,
434 STM_USB_EPR_STAT_TX_NAK);
436 /* Clear all of the other endpoints */
437 for (e = 1; e < 8; e++) {
439 STM_USB_EPR_EP_TYPE_CONTROL,
440 STM_USB_EPR_STAT_RX_DISABLED,
441 STM_USB_EPR_STAT_TX_DISABLED);
444 ao_usb_set_address(0);
448 /* Reset our internal state
451 ao_usb_ep0_state = AO_USB_EP0_IDLE;
453 ao_usb_ep0_in_data = NULL;
454 ao_usb_ep0_in_len = 0;
456 ao_usb_ep0_out_data = 0;
457 ao_usb_ep0_out_len = 0;
461 ao_usb_set_configuration(void)
463 debug ("ao_usb_set_configuration\n");
466 /* Set up the INT end point */
467 ao_usb_bdt[AO_USB_INT_EPR].single.addr_tx = ao_usb_int_tx_offset;
468 ao_usb_bdt[AO_USB_INT_EPR].single.count_tx = 0;
470 ao_usb_init_ep(AO_USB_INT_EPR,
472 STM_USB_EPR_EP_TYPE_INTERRUPT,
473 STM_USB_EPR_STAT_RX_DISABLED,
474 STM_USB_EPR_STAT_TX_NAK);
478 /* Set up the OUT end point */
479 ao_usb_bdt[AO_USB_OUT_EPR].single.addr_rx = ao_usb_out_rx_offset;
480 ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
481 (((AO_USB_OUT_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
483 ao_usb_init_ep(AO_USB_OUT_EPR,
485 STM_USB_EPR_EP_TYPE_BULK,
486 STM_USB_EPR_STAT_RX_VALID,
487 STM_USB_EPR_STAT_TX_DISABLED);
491 /* Set up the IN end point */
492 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_in_tx_offset;
493 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = 0;
495 ao_usb_init_ep(AO_USB_IN_EPR,
497 STM_USB_EPR_EP_TYPE_BULK,
498 STM_USB_EPR_STAT_RX_DISABLED,
499 STM_USB_EPR_STAT_TX_NAK);
503 /* Set up the IN2 end point */
504 ao_usb_bdt[AO_USB_IN2_EPR].single.addr_tx = ao_usb_in2_tx_offset;
505 ao_usb_bdt[AO_USB_IN2_EPR].single.count_tx = 0;
507 ao_usb_init_ep(AO_USB_IN2_EPR,
509 STM_USB_EPR_EP_TYPE_BULK,
510 STM_USB_EPR_STAT_RX_DISABLED,
511 STM_USB_EPR_STAT_TX_NAK);
514 ao_usb_in_flushed = 0;
515 ao_usb_in_pending = 0;
516 ao_wakeup(&ao_usb_in_pending);
518 ao_usb_in2_flushed = 0;
519 ao_usb_in2_pending = 0;
520 ao_wakeup(&ao_usb_in2_pending);
523 ao_usb_out_avail = 0;
524 ao_usb_configuration = 0;
526 ao_wakeup(AO_USB_OUT_SLEEP_ADDR);
530 ao_wakeup(&ao_usb_running);
534 static uint16_t control_count;
535 static uint16_t int_count;
536 static uint16_t in_count;
537 static uint16_t out_count;
538 static uint16_t reset_count;
540 /* The USB memory must be accessed in 16-bit units
544 ao_usb_copy_tx(const uint8_t *src, uint16_t *base, uint16_t bytes)
547 *base++ = src[0] | (src[1] << 8);
556 ao_usb_copy_rx(uint8_t *dst, uint16_t *base, uint16_t bytes)
559 uint16_t s = *base++;
569 /* Send an IN data packet */
571 ao_usb_ep0_flush(void)
575 /* Check to see if the endpoint is still busy */
576 if (ao_usb_epr_stat_tx(stm_usb.epr[0].r) == STM_USB_EPR_STAT_TX_VALID) {
577 debug("EP0 not accepting IN data\n");
581 this_len = ao_usb_ep0_in_len;
582 if (this_len > AO_USB_CONTROL_SIZE)
583 this_len = AO_USB_CONTROL_SIZE;
585 if (this_len < AO_USB_CONTROL_SIZE)
586 ao_usb_ep0_state = AO_USB_EP0_IDLE;
588 ao_usb_ep0_in_len -= this_len;
590 debug_data ("Flush EP0 len %d:", this_len);
591 ao_usb_copy_tx(ao_usb_ep0_in_data, ao_usb_ep0_tx_buffer, this_len);
593 ao_usb_ep0_in_data += this_len;
595 /* Mark the endpoint as TX valid to send the packet */
596 ao_usb_bdt[AO_USB_CONTROL_EPR].single.count_tx = this_len;
597 ao_usb_set_stat_tx(AO_USB_CONTROL_EPR, STM_USB_EPR_STAT_TX_VALID);
598 debug ("queue tx. epr 0 now %08x\n", stm_usb.epr[AO_USB_CONTROL_EPR]);
601 /* Read data from the ep0 OUT fifo */
603 ao_usb_ep0_fill(void)
605 uint16_t len = ao_usb_bdt[0].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
607 if (len > ao_usb_ep0_out_len)
608 len = ao_usb_ep0_out_len;
609 ao_usb_ep0_out_len -= len;
611 /* Pull all of the data out of the packet */
612 debug_data ("Fill EP0 len %d:", len);
613 ao_usb_copy_rx(ao_usb_ep0_out_data, ao_usb_ep0_rx_buffer, len);
615 ao_usb_ep0_out_data += len;
618 ao_usb_set_stat_rx(0, STM_USB_EPR_STAT_RX_VALID);
622 ao_usb_ep0_in_reset(void)
624 ao_usb_ep0_in_data = ao_usb_ep0_in_buf;
625 ao_usb_ep0_in_len = 0;
629 ao_usb_ep0_in_queue_byte(uint8_t a)
631 if (ao_usb_ep0_in_len < sizeof (ao_usb_ep0_in_buf))
632 ao_usb_ep0_in_buf[ao_usb_ep0_in_len++] = a;
636 ao_usb_ep0_in_set(const uint8_t *data, uint8_t len)
638 ao_usb_ep0_in_data = data;
639 ao_usb_ep0_in_len = len;
643 ao_usb_ep0_out_set(uint8_t *data, uint8_t len)
645 ao_usb_ep0_out_data = data;
646 ao_usb_ep0_out_len = len;
650 ao_usb_ep0_in_start(uint16_t max)
652 /* Don't send more than asked for */
653 if (ao_usb_ep0_in_len > max)
654 ao_usb_ep0_in_len = max;
658 struct ao_usb_line_coding ao_usb_line_coding = {115200, 0, 0, 8};
660 #if AO_USB_DEVICE_ID_SERIAL
661 static uint8_t ao_usb_serial[2 + 48];
663 /* Convert a 32-bit value to 8 hexidecimal UCS2 characters */
665 hex_to_ucs2(uint32_t in, uint8_t *out)
669 for (i = 28; i >= 0; i -= 4) {
670 uint8_t bits = (in >> i) & 0xf;
671 *out++ = ((bits < 10) ? '0' : ('a' - 10)) + bits;
676 /* Encode the device ID (96 bits) in hexidecimal to use as a device
680 ao_usb_serial_init(void)
682 ao_usb_serial[0] = 50; /* length */
683 ao_usb_serial[1] = AO_USB_DESC_STRING;
684 hex_to_ucs2(stm_device_id.u_id0, ao_usb_serial + 2 + 0);
685 hex_to_ucs2(stm_device_id.u_id1, ao_usb_serial + 2 + 16);
686 hex_to_ucs2(stm_device_id.u_id2, ao_usb_serial + 2 + 32);
690 /* Walk through the list of descriptors and find a match
693 ao_usb_get_descriptor(uint16_t value, uint16_t length)
695 const uint8_t *descriptor;
696 uint8_t type = value >> 8;
697 uint8_t index = value;
699 descriptor = ao_usb_descriptors;
700 while (descriptor[0] != 0) {
701 if (descriptor[1] == type && index-- == 0) {
703 if (type == AO_USB_DESC_CONFIGURATION)
707 #if AO_USB_DEVICE_ID_SERIAL
708 /* Slightly hacky - the serial number is string 3 */
709 if (type == AO_USB_DESC_STRING && (value & 0xff) == 3) {
710 descriptor = ao_usb_serial;
711 len = sizeof (ao_usb_serial);
716 ao_usb_ep0_in_set(descriptor, len);
719 descriptor += descriptor[0];
724 ao_usb_ep0_setup(void)
726 /* Pull the setup packet out of the fifo */
727 ao_usb_ep0_out_set((uint8_t *) &ao_usb_setup, 8);
729 if (ao_usb_ep0_out_len != 0) {
730 debug ("invalid setup packet length\n");
734 if ((ao_usb_setup.dir_type_recip & AO_USB_DIR_IN) || ao_usb_setup.length == 0)
735 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
737 ao_usb_ep0_state = AO_USB_EP0_DATA_OUT;
739 ao_usb_ep0_in_reset();
741 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_TYPE_MASK) {
742 case AO_USB_TYPE_STANDARD:
743 debug ("Standard setup packet\n");
744 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_RECIP_MASK) {
745 case AO_USB_RECIP_DEVICE:
746 debug ("Device setup packet\n");
747 switch(ao_usb_setup.request) {
748 case AO_USB_REQ_GET_STATUS:
749 debug ("get status\n");
750 ao_usb_ep0_in_queue_byte(0);
751 ao_usb_ep0_in_queue_byte(0);
753 case AO_USB_REQ_SET_ADDRESS:
754 debug ("set address %d\n", ao_usb_setup.value);
755 ao_usb_address = ao_usb_setup.value;
756 ao_usb_address_pending = 1;
758 case AO_USB_REQ_GET_DESCRIPTOR:
759 debug ("get descriptor %d\n", ao_usb_setup.value);
760 ao_usb_get_descriptor(ao_usb_setup.value, ao_usb_setup.length);
762 case AO_USB_REQ_GET_CONFIGURATION:
763 debug ("get configuration %d\n", ao_usb_configuration);
764 ao_usb_ep0_in_queue_byte(ao_usb_configuration);
766 case AO_USB_REQ_SET_CONFIGURATION:
767 ao_usb_configuration = ao_usb_setup.value;
768 debug ("set configuration %d\n", ao_usb_configuration);
769 ao_usb_set_configuration();
773 case AO_USB_RECIP_INTERFACE:
774 debug ("Interface setup packet\n");
775 switch(ao_usb_setup.request) {
776 case AO_USB_REQ_GET_STATUS:
777 ao_usb_ep0_in_queue_byte(0);
778 ao_usb_ep0_in_queue_byte(0);
780 case AO_USB_REQ_GET_INTERFACE:
781 ao_usb_ep0_in_queue_byte(0);
783 case AO_USB_REQ_SET_INTERFACE:
787 case AO_USB_RECIP_ENDPOINT:
788 debug ("Endpoint setup packet\n");
789 switch(ao_usb_setup.request) {
790 case AO_USB_REQ_GET_STATUS:
791 ao_usb_ep0_in_queue_byte(0);
792 ao_usb_ep0_in_queue_byte(0);
798 case AO_USB_TYPE_CLASS:
799 debug ("Class setup packet\n");
800 switch (ao_usb_setup.request) {
801 case AO_USB_SET_LINE_CODING:
802 debug ("set line coding\n");
803 ao_usb_ep0_out_set((uint8_t *) &ao_usb_line_coding, 7);
805 case AO_USB_GET_LINE_CODING:
806 debug ("get line coding\n");
807 ao_usb_ep0_in_set((const uint8_t *) &ao_usb_line_coding, 7);
809 case AO_USB_SET_CONTROL_LINE_STATE:
815 /* If we're not waiting to receive data from the host,
816 * queue an IN response
818 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
819 ao_usb_ep0_in_start(ao_usb_setup.length);
823 ao_usb_ep0_handle(uint8_t receive)
825 ao_usb_ep0_receive = 0;
826 if (receive & AO_USB_EP0_GOT_SETUP) {
830 if (receive & AO_USB_EP0_GOT_RX_DATA) {
831 debug ("\tgot rx data\n");
832 if (ao_usb_ep0_state == AO_USB_EP0_DATA_OUT) {
834 if (ao_usb_ep0_out_len == 0) {
835 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
836 ao_usb_ep0_in_start(0);
840 if (receive & AO_USB_EP0_GOT_TX_ACK) {
841 debug ("\tgot tx ack\n");
843 #if HAS_FLIGHT && AO_USB_FORCE_IDLE
844 ao_flight_force_idle = 1;
846 /* Wait until the IN packet is received from addr 0
847 * before assigning our local address
849 if (ao_usb_address_pending)
850 ao_usb_set_address(ao_usb_address);
851 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
856 #if AO_POWER_MANAGEMENT
860 stm_usb.cntr |= (1 << STM_USB_CNTR_FSUSP);
862 stm_usb.cntr |= (1 << STM_USB_CNTR_LP_MODE);
870 stm_usb.cntr &= ~(1 << STM_USB_CNTR_FSUSP);
878 uint32_t istr = stm_usb.istr;
880 stm_usb.istr = ~istr;
881 if (istr & (1 << STM_USB_ISTR_CTR)) {
882 uint8_t ep = istr & STM_USB_ISTR_EP_ID_MASK;
883 uint16_t epr, epr_write;
885 /* Preserve the SW write bits, don't mess with most HW writable bits,
886 * clear the CTR_RX and CTR_TX bits
888 epr = stm_usb.epr[ep].r;
890 epr_write &= STM_USB_EPR_PRESERVE_MASK;
891 epr_write |= STM_USB_EPR_INVARIANT;
892 epr_write &= ~(1 << STM_USB_EPR_CTR_RX);
893 epr_write &= ~(1 << STM_USB_EPR_CTR_TX);
894 stm_usb.epr[ep].r = epr_write;
899 if (ao_usb_epr_ctr_rx(epr)) {
900 if (ao_usb_epr_setup(epr))
901 ao_usb_ep0_receive |= AO_USB_EP0_GOT_SETUP;
903 ao_usb_ep0_receive |= AO_USB_EP0_GOT_RX_DATA;
905 if (ao_usb_epr_ctr_tx(epr))
906 ao_usb_ep0_receive |= AO_USB_EP0_GOT_TX_ACK;
907 ao_usb_ep0_handle(ao_usb_ep0_receive);
911 if (ao_usb_epr_ctr_rx(epr)) {
912 _rx_dbg1("RX ISR", epr);
913 ao_usb_out_avail = 1;
914 _rx_dbg0("out avail set");
915 ao_wakeup(AO_USB_OUT_SLEEP_ADDR);
916 _rx_dbg0("stdin awoken");
921 _tx_dbg1("TX ISR", epr);
922 if (ao_usb_epr_ctr_tx(epr)) {
923 ao_usb_in_pending = 0;
924 ao_wakeup(&ao_usb_in_pending);
930 _tx_dbg1("TX2 ISR", epr);
931 if (ao_usb_epr_ctr_tx(epr)) {
932 ao_usb_in2_pending = 0;
933 ao_wakeup(&ao_usb_in2_pending);
939 if (ao_usb_epr_ctr_tx(epr))
940 _ao_usb_set_stat_tx(AO_USB_INT_EPR, STM_USB_EPR_STAT_TX_NAK);
946 if (istr & (1 << STM_USB_ISTR_RESET)) {
951 #if AO_POWER_MANAGEMENT
952 if (istr & (1 << STM_USB_ISTR_SUSP)) {
953 debug ("\tsuspend\n");
956 if (istr & (1 << STM_USB_ISTR_WKUP)) {
957 debug ("\twakeup\n");
964 /* Queue the current IN buffer for transmission */
966 _ao_usb_in_send(void)
968 _tx_dbg0("in_send start");
969 debug ("send %d\n", ao_usb_tx_count);
970 while (ao_usb_in_pending)
971 ao_sleep(&ao_usb_in_pending);
972 ao_usb_in_pending = 1;
973 if (ao_usb_tx_count != AO_USB_IN_SIZE)
974 ao_usb_in_flushed = 1;
975 ao_usb_copy_tx(ao_usb_tx_buffer, ao_usb_in_tx_buffer, ao_usb_tx_count);
976 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_in_tx_offset;
977 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = ao_usb_tx_count;
979 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
980 _tx_dbg0("in_send end");
983 /* Wait for a free IN buffer. Interrupts are blocked */
985 _ao_usb_in_wait(void)
988 /* Check if the current buffer is writable */
989 if (ao_usb_tx_count < AO_USB_IN_SIZE)
992 _tx_dbg0("in_wait top");
993 /* Wait for an IN buffer to be ready */
994 while (ao_usb_in_pending)
995 ao_sleep(&ao_usb_in_pending);
996 _tx_dbg0("in_wait bottom");
1003 if (!ao_usb_running)
1006 /* Anytime we've sent a character since
1007 * the last time we flushed, we'll need
1008 * to send a packet -- the only other time
1009 * we would send a packet is when that
1010 * packet was full, in which case we now
1011 * want to send an empty packet
1013 ao_arch_block_interrupts();
1014 while (!ao_usb_in_flushed) {
1015 _tx_dbg0("flush top");
1017 _tx_dbg0("flush end");
1019 ao_arch_release_interrupts();
1023 ao_usb_putchar(char c)
1025 if (!ao_usb_running)
1028 ao_arch_block_interrupts();
1031 ao_usb_in_flushed = 0;
1032 ao_usb_tx_buffer[ao_usb_tx_count++] = (uint8_t) c;
1034 /* Send the packet when full */
1035 if (ao_usb_tx_count == AO_USB_IN_SIZE) {
1036 _tx_dbg0("putchar full");
1038 _tx_dbg0("putchar flushed");
1040 ao_arch_release_interrupts();
1045 /* Queue the current IN buffer for transmission */
1047 _ao_usb_in2_send(void)
1049 _tx_dbg0("in2_send start");
1050 debug ("send2 %d\n", ao_usb_tx_count);
1051 while (ao_usb_in2_pending)
1052 ao_sleep(&ao_usb_in2_pending);
1053 ao_usb_in2_pending = 1;
1054 if (ao_usb_tx2_count != AO_USB_IN_SIZE)
1055 ao_usb_in2_flushed = 1;
1056 ao_usb_copy_tx(ao_usb_tx2_buffer, ao_usb_in2_tx_buffer, ao_usb_tx2_count);
1057 ao_usb_bdt[AO_USB_IN2_EPR].single.addr_tx = ao_usb_in_tx_offset;
1058 ao_usb_bdt[AO_USB_IN2_EPR].single.count_tx = ao_usb_tx_count;
1059 ao_usb_tx2_count = 0;
1060 _ao_usb_set_stat_tx(AO_USB_IN2_EPR, STM_USB_EPR_STAT_TX_VALID);
1061 _tx_dbg0("in2_send end");
1064 /* Wait for a free IN buffer. Interrupts are blocked */
1066 _ao_usb_in2_wait(void)
1069 /* Check if the current buffer is writable */
1070 if (ao_usb_tx2_count < AO_USB_IN_SIZE)
1073 _tx_dbg0("in2_wait top");
1074 /* Wait for an IN buffer to be ready */
1075 while (ao_usb_in2_pending)
1076 ao_sleep(&ao_usb_in2_pending);
1077 _tx_dbg0("in_wait bottom");
1084 if (!ao_usb_running)
1087 /* Anytime we've sent a character since
1088 * the last time we flushed, we'll need
1089 * to send a packet -- the only other time
1090 * we would send a packet is when that
1091 * packet was full, in which case we now
1092 * want to send an empty packet
1094 ao_arch_block_interrupts();
1095 while (!ao_usb_in2_flushed) {
1096 _tx_dbg0("flush2 top");
1098 _tx_dbg0("flush2 end");
1100 ao_arch_release_interrupts();
1104 ao_usb_putchar2(char c)
1106 if (!ao_usb_running)
1109 ao_arch_block_interrupts();
1112 ao_usb_in2_flushed = 0;
1113 ao_usb_tx2_buffer[ao_usb_tx2_count++] = (uint8_t) c;
1115 /* Send the packet when full */
1116 if (ao_usb_tx2_count == AO_USB_IN_SIZE) {
1117 _tx_dbg0("putchar2 full");
1119 _tx_dbg0("putchar2 flushed");
1121 ao_arch_release_interrupts();
1127 _ao_usb_out_recv(void)
1129 _rx_dbg0("out_recv top");
1130 ao_usb_out_avail = 0;
1132 ao_usb_rx_count = ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
1134 _rx_dbg1("out_recv count", ao_usb_rx_count);
1135 debug ("recv %d\n", ao_usb_rx_count);
1136 debug_data("Fill OUT len %d:", ao_usb_rx_count);
1137 ao_usb_copy_rx(ao_usb_rx_buffer, ao_usb_out_rx_buffer, ao_usb_rx_count);
1141 /* ACK the packet */
1142 _ao_usb_set_stat_rx(AO_USB_OUT_EPR, STM_USB_EPR_STAT_RX_VALID);
1146 _ao_usb_pollchar(void)
1150 if (!ao_usb_running)
1151 return AO_READ_AGAIN;
1154 if (ao_usb_rx_pos != ao_usb_rx_count)
1157 _rx_dbg0("poll check");
1158 /* Check to see if a packet has arrived */
1159 if (!ao_usb_out_avail) {
1160 _rx_dbg0("poll none");
1161 return AO_READ_AGAIN;
1166 /* Pull a character out of the fifo */
1167 c = ao_usb_rx_buffer[ao_usb_rx_pos++];
1172 ao_usb_getchar(void)
1176 ao_arch_block_interrupts();
1177 while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN)
1178 ao_sleep(AO_USB_OUT_SLEEP_ADDR);
1179 ao_arch_release_interrupts();
1190 buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
1191 ao_usb_sram_addr += AO_USB_IN_SIZE;
1196 ao_usb_write(uint16_t *buffer, uint16_t len)
1198 ao_arch_block_interrupts();
1200 /* Wait for everything to be ready at the same time */
1202 /* Make sure USB is connected */
1203 if (!ao_usb_running) {
1204 ao_sleep(&ao_usb_running);
1208 /* Flush any pending regular I/O */
1209 if (ao_usb_tx_count) {
1214 /* Wait for an idle IN buffer */
1215 if (ao_usb_in_pending) {
1216 ao_sleep(&ao_usb_in_pending);
1222 ao_usb_in_pending = 1;
1223 ao_usb_in_flushed = (len != AO_USB_IN_SIZE);
1224 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_packet_buffer_offset(buffer);
1225 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = len;
1226 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
1227 ao_arch_release_interrupts();
1232 ao_usb_write2(uint16_t *buffer, uint16_t len)
1234 ao_arch_block_interrupts();
1236 /* Wait for everything to be ready at the same time */
1238 /* Make sure USB is connected */
1239 if (!ao_usb_running) {
1240 ao_sleep(&ao_usb_running);
1244 /* Flush any pending regular I/O */
1245 if (ao_usb_tx2_count) {
1250 /* Wait for an idle IN buffer */
1251 if (ao_usb_in2_pending) {
1252 ao_sleep(&ao_usb_in2_pending);
1258 ao_usb_in2_pending = 1;
1259 ao_usb_in2_flushed = (len != AO_USB_IN_SIZE);
1260 ao_usb_bdt[AO_USB_IN2_EPR].single.addr_tx = ao_usb_packet_buffer_offset(buffer);
1261 ao_usb_bdt[AO_USB_IN2_EPR].single.count_tx = len;
1262 _ao_usb_set_stat_tx(AO_USB_IN2_EPR, STM_USB_EPR_STAT_TX_VALID);
1263 ao_arch_release_interrupts();
1269 ao_usb_disable(void)
1271 ao_arch_block_interrupts();
1272 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1275 /* Disable USB pull-up */
1276 stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
1278 /* Switch off the device */
1279 stm_usb.cntr = (1 << STM_USB_CNTR_PDWN) | (1 << STM_USB_CNTR_FRES);
1281 /* Disable the interface */
1282 stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_USBEN);
1283 ao_arch_release_interrupts();
1291 /* Select HSI48 as USB clock source */
1292 stm_rcc.cfgr3 &= ~(1 << STM_RCC_CFGR3_USBSW);
1294 /* Enable USB device */
1295 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USBEN);
1297 /* Clear reset condition */
1298 stm_rcc.apb1rstr &= ~(1 << STM_RCC_APB1RSTR_USBRST);
1300 /* Disable USB pull-up */
1301 stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
1303 /* Do not touch the GPIOA configuration; USB takes priority
1304 * over GPIO on pins A11 and A12, but if you select alternate
1305 * input 10 (the documented correct selection), then USB is
1306 * pulled low and doesn't work at all
1309 ao_arch_block_interrupts();
1311 /* Route interrupts */
1312 stm_nvic_set_enable(STM_ISR_USB_POS);
1313 stm_nvic_set_priority(STM_ISR_USB_POS, 3);
1315 ao_usb_configuration = 0;
1317 /* Set up buffer descriptors */
1318 ao_usb_init_btable();
1320 /* Reset the USB controller */
1321 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1323 /* Clear the reset bit */
1326 /* Clear any spurious interrupts */
1331 debug ("ao_usb_enable\n");
1333 /* Enable interrupts */
1334 stm_usb.cntr = ((1 << STM_USB_CNTR_CTRM) |
1335 (0 << STM_USB_CNTR_PMAOVRM) |
1336 (0 << STM_USB_CNTR_ERRM) |
1337 (AO_POWER_MANAGEMENT << STM_USB_CNTR_WKUPM) |
1338 (AO_POWER_MANAGEMENT << STM_USB_CNTR_SUSPM) |
1339 (1 << STM_USB_CNTR_RESETM) |
1340 (0 << STM_USB_CNTR_SOFM) |
1341 (0 << STM_USB_CNTR_ESOFM) |
1342 (0 << STM_USB_CNTR_RESUME) |
1343 (0 << STM_USB_CNTR_FSUSP) |
1344 (0 << STM_USB_CNTR_LP_MODE) |
1345 (0 << STM_USB_CNTR_PDWN) |
1346 (0 << STM_USB_CNTR_FRES));
1348 ao_arch_release_interrupts();
1350 for (t = 0; t < 1000; t++)
1353 /* Enable USB pull-up */
1354 stm_usb.bcdr |= (1 << STM_USB_BCDR_DPPU);
1358 struct ao_task ao_usb_echo_task;
1366 c = ao_usb_getchar();
1377 printf ("control: %d out: %d in: %d int: %d reset: %d\n",
1378 control_count, out_count, in_count, int_count, reset_count);
1381 __code struct ao_cmds ao_usb_cmds[] = {
1382 { ao_usb_irq, "I\0Show USB interrupt counts" },
1390 /* Turn on syscfg */
1391 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
1393 /* Set PA11/PA12 remapping bit */
1394 stm_syscfg.cfgr1 |= (AO_PA11_PA12_RMP << STM_SYSCFG_CFGR1_PA11_PA12_RMP);
1396 #ifndef AO_USB_START_DISABLED
1400 #if AO_USB_DEVICE_ID_SERIAL
1401 ao_usb_serial_init();
1404 debug ("ao_usb_init\n");
1405 ao_usb_ep0_state = AO_USB_EP0_IDLE;
1407 ao_usb_alloc_buffers();
1410 ao_add_task(&ao_usb_echo_task, ao_usb_echo, "usb echo");
1413 ao_cmd_register(&ao_usb_cmds[0]);
1417 ao_add_stdio(_ao_usb_pollchar, ao_usb_putchar, ao_usb_flush);
1422 #if TX_DBG || RX_DBG
1432 uint32_t in_pending;
1434 uint32_t in_flushed;
1444 #define NUM_USB_DBG 128
1446 static struct ao_usb_dbg dbg[128];
1449 static void _dbg(int line, char *msg, uint32_t value)
1452 dbg[dbg_i].line = line;
1453 dbg[dbg_i].msg = msg;
1454 dbg[dbg_i].value = value;
1455 asm("mrs %0,primask" : "=&r" (primask));
1456 dbg[dbg_i].primask = primask;
1458 dbg[dbg_i].in_count = in_count;
1459 dbg[dbg_i].in_epr = stm_usb.epr[AO_USB_IN_EPR];
1460 dbg[dbg_i].in_pending = ao_usb_in_pending;
1461 dbg[dbg_i].tx_count = ao_usb_tx_count;
1462 dbg[dbg_i].in_flushed = ao_usb_in_flushed;
1465 dbg[dbg_i].rx_count = ao_usb_rx_count;
1466 dbg[dbg_i].rx_pos = ao_usb_rx_pos;
1467 dbg[dbg_i].out_avail = ao_usb_out_avail;
1468 dbg[dbg_i].out_epr = stm_usb.epr[AO_USB_OUT_EPR];
1470 if (++dbg_i == NUM_USB_DBG)