2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 #include "ao_product.h"
23 #define USB_DEBUG_DATA 0
26 #ifndef AO_PA11_PA12_RMP
27 #error "must define AO_PA11_PA12_RMP"
31 #define USE_USB_STDIO 1
35 #define AO_USB_OUT_SLEEP_ADDR (&ao_stdin_ready)
37 #define AO_USB_OUT_SLEEP_ADDR (&ao_usb_out_avail)
41 #define debug(format, args...) printf(format, ## args);
43 #define debug(format, args...)
47 #define debug_data(format, args...) printf(format, ## args);
49 #define debug_data(format, args...)
53 uint8_t dir_type_recip;
60 static uint8_t ao_usb_ep0_state;
62 /* Pending EP0 IN data */
63 static const uint8_t *ao_usb_ep0_in_data; /* Remaining data */
64 static uint8_t ao_usb_ep0_in_len; /* Remaining amount */
66 /* Temp buffer for smaller EP0 in data */
67 static uint8_t ao_usb_ep0_in_buf[2];
69 /* Pending EP0 OUT data */
70 static uint8_t *ao_usb_ep0_out_data;
71 static uint8_t ao_usb_ep0_out_len;
74 * Objects allocated in special USB memory
77 /* Buffer description tables */
78 static union stm_usb_bdt *ao_usb_bdt;
79 /* USB address of end of allocated storage */
80 static uint16_t ao_usb_sram_addr;
82 /* Pointer to ep0 tx/rx buffers in USB memory */
83 static uint16_t *ao_usb_ep0_tx_buffer;
84 static uint16_t *ao_usb_ep0_rx_buffer;
86 /* Pointer to bulk data tx/rx buffers in USB memory */
87 static uint16_t ao_usb_in_tx_offset;
88 static uint16_t *ao_usb_in_tx_buffer;
89 static uint16_t *ao_usb_out_rx_buffer;
91 /* System ram shadow of USB buffer; writing individual bytes is
92 * too much of a pain (sigh) */
93 static uint8_t ao_usb_tx_buffer[AO_USB_IN_SIZE];
94 static uint8_t ao_usb_tx_count;
96 static uint8_t ao_usb_rx_buffer[AO_USB_OUT_SIZE];
97 static uint8_t ao_usb_rx_count, ao_usb_rx_pos;
100 * End point register indices
103 #define AO_USB_CONTROL_EPR 0
104 #define AO_USB_INT_EPR 1
105 #define AO_USB_OUT_EPR 2
106 #define AO_USB_IN_EPR 3
108 /* Marks when we don't need to send an IN packet.
109 * This happens only when the last IN packet is not full,
110 * otherwise the host will expect to keep seeing packets.
111 * Send a zero-length packet as required
113 static uint8_t ao_usb_in_flushed;
115 /* Marks when we have delivered an IN packet to the hardware
116 * and it has not been received yet. ao_sleep on this address
117 * to wait for it to be delivered.
119 static uint8_t ao_usb_in_pending;
121 /* Marks when an OUT packet has been received by the hardware
122 * but not pulled to the shadow buffer.
124 static uint8_t ao_usb_out_avail;
125 uint8_t ao_usb_running;
126 static uint8_t ao_usb_configuration;
128 #define AO_USB_EP0_GOT_RESET 1
129 #define AO_USB_EP0_GOT_SETUP 2
130 #define AO_USB_EP0_GOT_RX_DATA 4
131 #define AO_USB_EP0_GOT_TX_ACK 8
133 static uint8_t ao_usb_ep0_receive;
134 static uint8_t ao_usb_address;
135 static uint8_t ao_usb_address_pending;
137 static inline uint32_t set_toggle(uint32_t current_value,
139 uint32_t desired_value)
141 return (current_value ^ desired_value) & mask;
144 static inline uint16_t *ao_usb_packet_buffer_addr(uint16_t sram_addr)
146 return (uint16_t *) (stm_usb_sram + sram_addr);
150 static inline uint16_t ao_usb_packet_buffer_offset(uint16_t *addr)
152 return (uint16_t) ((uint8_t *) addr - stm_usb_sram);
156 static inline uint32_t ao_usb_epr_stat_rx(uint32_t epr) {
157 return (epr >> STM_USB_EPR_STAT_RX) & STM_USB_EPR_STAT_RX_MASK;
160 static inline uint32_t ao_usb_epr_stat_tx(uint32_t epr) {
161 return (epr >> STM_USB_EPR_STAT_TX) & STM_USB_EPR_STAT_TX_MASK;
164 static inline uint32_t ao_usb_epr_ctr_rx(uint32_t epr) {
165 return (epr >> STM_USB_EPR_CTR_RX) & 1;
168 static inline uint32_t ao_usb_epr_ctr_tx(uint32_t epr) {
169 return (epr >> STM_USB_EPR_CTR_TX) & 1;
172 static inline uint32_t ao_usb_epr_setup(uint32_t epr) {
173 return (epr >> STM_USB_EPR_SETUP) & 1;
176 static inline uint32_t ao_usb_epr_dtog_rx(uint32_t epr) {
177 return (epr >> STM_USB_EPR_DTOG_RX) & 1;
180 static inline uint32_t ao_usb_epr_dtog_tx(uint32_t epr) {
181 return (epr >> STM_USB_EPR_DTOG_TX) & 1;
185 * Set current device address and mark the
186 * interface as active
189 ao_usb_set_address(uint8_t address)
191 debug("ao_usb_set_address %02x\n", address);
192 stm_usb.daddr = (1 << STM_USB_DADDR_EF) | address;
193 ao_usb_address_pending = 0;
197 * Write these values to preserve register contents under HW changes
200 #define STM_USB_EPR_INVARIANT ((1 << STM_USB_EPR_CTR_RX) | \
201 (STM_USB_EPR_DTOG_RX_WRITE_INVARIANT << STM_USB_EPR_DTOG_RX) | \
202 (STM_USB_EPR_STAT_RX_WRITE_INVARIANT << STM_USB_EPR_STAT_RX) | \
203 (1 << STM_USB_EPR_CTR_TX) | \
204 (STM_USB_EPR_DTOG_TX_WRITE_INVARIANT << STM_USB_EPR_DTOG_TX) | \
205 (STM_USB_EPR_STAT_TX_WRITE_INVARIANT << STM_USB_EPR_STAT_TX))
207 #define STM_USB_EPR_INVARIANT_MASK ((1 << STM_USB_EPR_CTR_RX) | \
208 (STM_USB_EPR_DTOG_RX_MASK << STM_USB_EPR_DTOG_RX) | \
209 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) | \
210 (1 << STM_USB_EPR_CTR_TX) | \
211 (STM_USB_EPR_DTOG_TX_MASK << STM_USB_EPR_DTOG_TX) | \
212 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX))
215 * These bits are purely under sw control, so preserve them in the
216 * register by re-writing what was read
218 #define STM_USB_EPR_PRESERVE_MASK ((STM_USB_EPR_EP_TYPE_MASK << STM_USB_EPR_EP_TYPE) | \
219 (1 << STM_USB_EPR_EP_KIND) | \
220 (STM_USB_EPR_EA_MASK << STM_USB_EPR_EA))
226 #define _tx_dbg0(msg) _dbg(__LINE__,msg,0)
227 #define _tx_dbg1(msg,value) _dbg(__LINE__,msg,value)
229 #define _tx_dbg0(msg)
230 #define _tx_dbg1(msg,value)
234 #define _rx_dbg0(msg) _dbg(__LINE__,msg,0)
235 #define _rx_dbg1(msg,value) _dbg(__LINE__,msg,value)
237 #define _rx_dbg0(msg)
238 #define _rx_dbg1(msg,value)
242 static void _dbg(int line, char *msg, uint32_t value);
246 * Set the state of the specified endpoint register to a new
247 * value. This is tricky because the bits toggle where the new
248 * value is one, and we need to write invariant values in other
249 * spots of the register. This hardware is strange...
252 _ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
254 uint16_t epr_write, epr_old;
256 _tx_dbg1("set_stat_tx top", stat_tx);
257 epr_old = epr_write = stm_usb.epr[ep].r;
258 epr_write &= STM_USB_EPR_PRESERVE_MASK;
259 epr_write |= STM_USB_EPR_INVARIANT;
260 epr_write |= set_toggle(epr_old,
261 STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX,
262 stat_tx << STM_USB_EPR_STAT_TX);
263 stm_usb.epr[ep].r = epr_write;
264 _tx_dbg1("set_stat_tx bottom", epr_write);
268 ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
270 ao_arch_block_interrupts();
271 _ao_usb_set_stat_tx(ep, stat_tx);
272 ao_arch_release_interrupts();
276 _ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
277 uint16_t epr_write, epr_old;
279 epr_write = epr_old = stm_usb.epr[ep].r;
280 epr_write &= STM_USB_EPR_PRESERVE_MASK;
281 epr_write |= STM_USB_EPR_INVARIANT;
282 epr_write |= set_toggle(epr_old,
283 STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX,
284 stat_rx << STM_USB_EPR_STAT_RX);
285 stm_usb.epr[ep].r = epr_write;
289 ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
290 ao_arch_block_interrupts();
291 _ao_usb_set_stat_rx(ep, stat_rx);
292 ao_arch_release_interrupts();
296 * Set just endpoint 0, for use during startup
300 ao_usb_init_ep(uint8_t ep, uint32_t addr, uint32_t type, uint32_t stat_rx, uint32_t stat_tx)
304 ao_arch_block_interrupts();
305 epr = stm_usb.epr[ep].r;
306 epr = ((0 << STM_USB_EPR_CTR_RX) |
307 (epr & (1 << STM_USB_EPR_DTOG_RX)) |
309 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX),
310 (stat_rx << STM_USB_EPR_STAT_RX)) |
311 (type << STM_USB_EPR_EP_TYPE) |
312 (0 << STM_USB_EPR_EP_KIND) |
313 (0 << STM_USB_EPR_CTR_TX) |
314 (epr & (1 << STM_USB_EPR_DTOG_TX)) |
316 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX),
317 (stat_tx << STM_USB_EPR_STAT_TX)) |
318 (addr << STM_USB_EPR_EA));
319 stm_usb.epr[ep].r = epr;
320 ao_arch_release_interrupts();
321 debug ("writing epr[%d] 0x%04x wrote 0x%04x\n",
322 ep, epr, stm_usb.epr[ep].r);
326 ao_usb_init_btable(void)
328 ao_usb_sram_addr = 0;
330 ao_usb_bdt = (void *) stm_usb_sram;
332 ao_usb_sram_addr += 8 * STM_USB_BDT_SIZE;
334 /* Set up EP 0 - a Control end point with 32 bytes of in and out buffers */
336 ao_usb_bdt[0].single.addr_tx = ao_usb_sram_addr;
337 ao_usb_bdt[0].single.count_tx = 0;
338 ao_usb_ep0_tx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
339 ao_usb_sram_addr += AO_USB_CONTROL_SIZE;
341 ao_usb_bdt[0].single.addr_rx = ao_usb_sram_addr;
342 ao_usb_bdt[0].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
343 (((AO_USB_CONTROL_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
344 ao_usb_ep0_rx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
345 ao_usb_sram_addr += AO_USB_CONTROL_SIZE;
354 ao_usb_init_btable();
356 /* buffer table is at the start of USB memory */
359 ao_usb_init_ep(AO_USB_CONTROL_EPR, AO_USB_CONTROL_EP,
360 STM_USB_EPR_EP_TYPE_CONTROL,
361 STM_USB_EPR_STAT_RX_VALID,
362 STM_USB_EPR_STAT_TX_NAK);
364 /* Clear all of the other endpoints */
365 for (e = 1; e < 8; e++) {
367 STM_USB_EPR_EP_TYPE_CONTROL,
368 STM_USB_EPR_STAT_RX_DISABLED,
369 STM_USB_EPR_STAT_TX_DISABLED);
372 ao_usb_set_address(0);
376 ao_usb_set_configuration(void)
378 debug ("ao_usb_set_configuration\n");
380 /* Set up the INT end point */
381 ao_usb_bdt[AO_USB_INT_EPR].single.addr_tx = ao_usb_sram_addr;
382 ao_usb_bdt[AO_USB_INT_EPR].single.count_tx = 0;
383 ao_usb_sram_addr += AO_USB_INT_SIZE;
385 ao_usb_init_ep(AO_USB_INT_EPR,
387 STM_USB_EPR_EP_TYPE_INTERRUPT,
388 STM_USB_EPR_STAT_RX_DISABLED,
389 STM_USB_EPR_STAT_TX_NAK);
391 /* Set up the OUT end point */
392 ao_usb_bdt[AO_USB_OUT_EPR].single.addr_rx = ao_usb_sram_addr;
393 ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
394 (((AO_USB_OUT_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
395 ao_usb_out_rx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
396 ao_usb_sram_addr += AO_USB_OUT_SIZE;
398 ao_usb_init_ep(AO_USB_OUT_EPR,
400 STM_USB_EPR_EP_TYPE_BULK,
401 STM_USB_EPR_STAT_RX_VALID,
402 STM_USB_EPR_STAT_TX_DISABLED);
404 /* Set up the IN end point */
405 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_sram_addr;
406 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = 0;
407 ao_usb_in_tx_offset = ao_usb_sram_addr;
408 ao_usb_in_tx_buffer = ao_usb_packet_buffer_addr(ao_usb_in_tx_offset);
409 ao_usb_sram_addr += AO_USB_IN_SIZE;
411 ao_usb_init_ep(AO_USB_IN_EPR,
413 STM_USB_EPR_EP_TYPE_BULK,
414 STM_USB_EPR_STAT_RX_DISABLED,
415 STM_USB_EPR_STAT_TX_NAK);
420 static uint16_t control_count;
421 static uint16_t int_count;
422 static uint16_t in_count;
423 static uint16_t out_count;
424 static uint16_t reset_count;
426 /* The USB memory must be accessed in 16-bit units
430 ao_usb_copy_tx(const uint8_t *src, uint16_t *base, uint16_t bytes)
433 *base++ = src[0] | (src[1] << 8);
442 ao_usb_copy_rx(uint8_t *dst, uint16_t *base, uint16_t bytes)
445 uint16_t s = *base++;
455 /* Send an IN data packet */
457 ao_usb_ep0_flush(void)
461 /* Check to see if the endpoint is still busy */
462 if (ao_usb_epr_stat_tx(stm_usb.epr[0].r) == STM_USB_EPR_STAT_TX_VALID) {
463 debug("EP0 not accepting IN data\n");
467 this_len = ao_usb_ep0_in_len;
468 if (this_len > AO_USB_CONTROL_SIZE)
469 this_len = AO_USB_CONTROL_SIZE;
471 if (this_len < AO_USB_CONTROL_SIZE)
472 ao_usb_ep0_state = AO_USB_EP0_IDLE;
474 ao_usb_ep0_in_len -= this_len;
476 debug_data ("Flush EP0 len %d:", this_len);
477 ao_usb_copy_tx(ao_usb_ep0_in_data, ao_usb_ep0_tx_buffer, this_len);
479 ao_usb_ep0_in_data += this_len;
481 /* Mark the endpoint as TX valid to send the packet */
482 ao_usb_bdt[AO_USB_CONTROL_EPR].single.count_tx = this_len;
483 ao_usb_set_stat_tx(AO_USB_CONTROL_EPR, STM_USB_EPR_STAT_TX_VALID);
484 debug ("queue tx. epr 0 now %08x\n", stm_usb.epr[AO_USB_CONTROL_EPR]);
487 /* Read data from the ep0 OUT fifo */
489 ao_usb_ep0_fill(void)
491 uint16_t len = ao_usb_bdt[0].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
493 if (len > ao_usb_ep0_out_len)
494 len = ao_usb_ep0_out_len;
495 ao_usb_ep0_out_len -= len;
497 /* Pull all of the data out of the packet */
498 debug_data ("Fill EP0 len %d:", len);
499 ao_usb_copy_rx(ao_usb_ep0_out_data, ao_usb_ep0_rx_buffer, len);
501 ao_usb_ep0_out_data += len;
504 ao_usb_set_stat_rx(0, STM_USB_EPR_STAT_RX_VALID);
508 ao_usb_ep0_in_reset(void)
510 ao_usb_ep0_in_data = ao_usb_ep0_in_buf;
511 ao_usb_ep0_in_len = 0;
515 ao_usb_ep0_in_queue_byte(uint8_t a)
517 if (ao_usb_ep0_in_len < sizeof (ao_usb_ep0_in_buf))
518 ao_usb_ep0_in_buf[ao_usb_ep0_in_len++] = a;
522 ao_usb_ep0_in_set(const uint8_t *data, uint8_t len)
524 ao_usb_ep0_in_data = data;
525 ao_usb_ep0_in_len = len;
529 ao_usb_ep0_out_set(uint8_t *data, uint8_t len)
531 ao_usb_ep0_out_data = data;
532 ao_usb_ep0_out_len = len;
536 ao_usb_ep0_in_start(uint16_t max)
538 /* Don't send more than asked for */
539 if (ao_usb_ep0_in_len > max)
540 ao_usb_ep0_in_len = max;
544 static struct ao_usb_line_coding ao_usb_line_coding = {115200, 0, 0, 8};
546 /* Walk through the list of descriptors and find a match
549 ao_usb_get_descriptor(uint16_t value)
551 const uint8_t *descriptor;
552 uint8_t type = value >> 8;
553 uint8_t index = value;
555 descriptor = ao_usb_descriptors;
556 while (descriptor[0] != 0) {
557 if (descriptor[1] == type && index-- == 0) {
559 if (type == AO_USB_DESC_CONFIGURATION)
563 ao_usb_ep0_in_set(descriptor, len);
566 descriptor += descriptor[0];
571 ao_usb_ep0_setup(void)
573 /* Pull the setup packet out of the fifo */
574 ao_usb_ep0_out_set((uint8_t *) &ao_usb_setup, 8);
576 if (ao_usb_ep0_out_len != 0) {
577 debug ("invalid setup packet length\n");
581 if ((ao_usb_setup.dir_type_recip & AO_USB_DIR_IN) || ao_usb_setup.length == 0)
582 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
584 ao_usb_ep0_state = AO_USB_EP0_DATA_OUT;
586 ao_usb_ep0_in_reset();
588 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_TYPE_MASK) {
589 case AO_USB_TYPE_STANDARD:
590 debug ("Standard setup packet\n");
591 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_RECIP_MASK) {
592 case AO_USB_RECIP_DEVICE:
593 debug ("Device setup packet\n");
594 switch(ao_usb_setup.request) {
595 case AO_USB_REQ_GET_STATUS:
596 debug ("get status\n");
597 ao_usb_ep0_in_queue_byte(0);
598 ao_usb_ep0_in_queue_byte(0);
600 case AO_USB_REQ_SET_ADDRESS:
601 debug ("set address %d\n", ao_usb_setup.value);
602 ao_usb_address = ao_usb_setup.value;
603 ao_usb_address_pending = 1;
605 case AO_USB_REQ_GET_DESCRIPTOR:
606 debug ("get descriptor %d\n", ao_usb_setup.value);
607 ao_usb_get_descriptor(ao_usb_setup.value);
609 case AO_USB_REQ_GET_CONFIGURATION:
610 debug ("get configuration %d\n", ao_usb_configuration);
611 ao_usb_ep0_in_queue_byte(ao_usb_configuration);
613 case AO_USB_REQ_SET_CONFIGURATION:
614 ao_usb_configuration = ao_usb_setup.value;
615 debug ("set configuration %d\n", ao_usb_configuration);
616 ao_usb_set_configuration();
620 case AO_USB_RECIP_INTERFACE:
621 debug ("Interface setup packet\n");
622 switch(ao_usb_setup.request) {
623 case AO_USB_REQ_GET_STATUS:
624 ao_usb_ep0_in_queue_byte(0);
625 ao_usb_ep0_in_queue_byte(0);
627 case AO_USB_REQ_GET_INTERFACE:
628 ao_usb_ep0_in_queue_byte(0);
630 case AO_USB_REQ_SET_INTERFACE:
634 case AO_USB_RECIP_ENDPOINT:
635 debug ("Endpoint setup packet\n");
636 switch(ao_usb_setup.request) {
637 case AO_USB_REQ_GET_STATUS:
638 ao_usb_ep0_in_queue_byte(0);
639 ao_usb_ep0_in_queue_byte(0);
645 case AO_USB_TYPE_CLASS:
646 debug ("Class setup packet\n");
647 switch (ao_usb_setup.request) {
648 case AO_USB_SET_LINE_CODING:
649 debug ("set line coding\n");
650 ao_usb_ep0_out_set((uint8_t *) &ao_usb_line_coding, 7);
652 case AO_USB_GET_LINE_CODING:
653 debug ("get line coding\n");
654 ao_usb_ep0_in_set((const uint8_t *) &ao_usb_line_coding, 7);
656 case AO_USB_SET_CONTROL_LINE_STATE:
662 /* If we're not waiting to receive data from the host,
663 * queue an IN response
665 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
666 ao_usb_ep0_in_start(ao_usb_setup.length);
670 ao_usb_ep0_handle(uint8_t receive)
672 ao_usb_ep0_receive = 0;
673 if (receive & AO_USB_EP0_GOT_RESET) {
678 if (receive & AO_USB_EP0_GOT_SETUP) {
682 if (receive & AO_USB_EP0_GOT_RX_DATA) {
683 debug ("\tgot rx data\n");
684 if (ao_usb_ep0_state == AO_USB_EP0_DATA_OUT) {
686 if (ao_usb_ep0_out_len == 0) {
687 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
688 ao_usb_ep0_in_start(0);
692 if (receive & AO_USB_EP0_GOT_TX_ACK) {
693 debug ("\tgot tx ack\n");
695 #if HAS_FLIGHT && AO_USB_FORCE_IDLE
696 ao_flight_force_idle = 1;
698 /* Wait until the IN packet is received from addr 0
699 * before assigning our local address
701 if (ao_usb_address_pending)
702 ao_usb_set_address(ao_usb_address);
703 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
711 uint32_t istr = stm_usb.istr;
713 stm_usb.istr = ~istr;
714 if (istr & (1 << STM_USB_ISTR_CTR)) {
715 uint8_t ep = istr & STM_USB_ISTR_EP_ID_MASK;
716 uint16_t epr, epr_write;
718 /* Preserve the SW write bits, don't mess with most HW writable bits,
719 * clear the CTR_RX and CTR_TX bits
721 epr = stm_usb.epr[ep].r;
723 epr_write &= STM_USB_EPR_PRESERVE_MASK;
724 epr_write |= STM_USB_EPR_INVARIANT;
725 epr_write &= ~(1 << STM_USB_EPR_CTR_RX);
726 epr_write &= ~(1 << STM_USB_EPR_CTR_TX);
727 stm_usb.epr[ep].r = epr_write;
732 if (ao_usb_epr_ctr_rx(epr)) {
733 if (ao_usb_epr_setup(epr))
734 ao_usb_ep0_receive |= AO_USB_EP0_GOT_SETUP;
736 ao_usb_ep0_receive |= AO_USB_EP0_GOT_RX_DATA;
738 if (ao_usb_epr_ctr_tx(epr))
739 ao_usb_ep0_receive |= AO_USB_EP0_GOT_TX_ACK;
740 ao_usb_ep0_handle(ao_usb_ep0_receive);
744 if (ao_usb_epr_ctr_rx(epr)) {
745 _rx_dbg1("RX ISR", epr);
746 ao_usb_out_avail = 1;
747 _rx_dbg0("out avail set");
748 ao_wakeup(AO_USB_OUT_SLEEP_ADDR);
749 _rx_dbg0("stdin awoken");
754 _tx_dbg1("TX ISR", epr);
755 if (ao_usb_epr_ctr_tx(epr)) {
756 ao_usb_in_pending = 0;
757 ao_wakeup(&ao_usb_in_pending);
762 if (ao_usb_epr_ctr_tx(epr))
763 _ao_usb_set_stat_tx(AO_USB_INT_EPR, STM_USB_EPR_STAT_TX_NAK);
769 if (istr & (1 << STM_USB_ISTR_RESET)) {
771 ao_usb_ep0_receive |= AO_USB_EP0_GOT_RESET;
772 ao_usb_ep0_handle(ao_usb_ep0_receive);
777 /* Queue the current IN buffer for transmission */
779 _ao_usb_in_send(void)
781 _tx_dbg0("in_send start");
782 debug ("send %d\n", ao_usb_tx_count);
783 while (ao_usb_in_pending)
784 ao_sleep(&ao_usb_in_pending);
785 ao_usb_in_pending = 1;
786 if (ao_usb_tx_count != AO_USB_IN_SIZE)
787 ao_usb_in_flushed = 1;
788 ao_usb_copy_tx(ao_usb_tx_buffer, ao_usb_in_tx_buffer, ao_usb_tx_count);
789 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_in_tx_offset;
790 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = ao_usb_tx_count;
792 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
793 _tx_dbg0("in_send end");
796 /* Wait for a free IN buffer. Interrupts are blocked */
798 _ao_usb_in_wait(void)
801 /* Check if the current buffer is writable */
802 if (ao_usb_tx_count < AO_USB_IN_SIZE)
805 _tx_dbg0("in_wait top");
806 /* Wait for an IN buffer to be ready */
807 while (ao_usb_in_pending)
808 ao_sleep(&ao_usb_in_pending);
809 _tx_dbg0("in_wait bottom");
819 /* Anytime we've sent a character since
820 * the last time we flushed, we'll need
821 * to send a packet -- the only other time
822 * we would send a packet is when that
823 * packet was full, in which case we now
824 * want to send an empty packet
826 ao_arch_block_interrupts();
827 while (!ao_usb_in_flushed) {
828 _tx_dbg0("flush top");
830 _tx_dbg0("flush end");
832 ao_arch_release_interrupts();
836 ao_usb_putchar(char c)
841 ao_arch_block_interrupts();
844 ao_usb_in_flushed = 0;
845 ao_usb_tx_buffer[ao_usb_tx_count++] = (uint8_t) c;
847 /* Send the packet when full */
848 if (ao_usb_tx_count == AO_USB_IN_SIZE) {
849 _tx_dbg0("putchar full");
851 _tx_dbg0("putchar flushed");
853 ao_arch_release_interrupts();
857 _ao_usb_out_recv(void)
859 _rx_dbg0("out_recv top");
860 ao_usb_out_avail = 0;
862 ao_usb_rx_count = ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
864 _rx_dbg1("out_recv count", ao_usb_rx_count);
865 debug ("recv %d\n", ao_usb_rx_count);
866 debug_data("Fill OUT len %d:", ao_usb_rx_count);
867 ao_usb_copy_rx(ao_usb_rx_buffer, ao_usb_out_rx_buffer, ao_usb_rx_count);
872 _ao_usb_set_stat_rx(AO_USB_OUT_EPR, STM_USB_EPR_STAT_RX_VALID);
876 _ao_usb_pollchar(void)
881 return AO_READ_AGAIN;
884 if (ao_usb_rx_pos != ao_usb_rx_count)
887 _rx_dbg0("poll check");
888 /* Check to see if a packet has arrived */
889 if (!ao_usb_out_avail) {
890 _rx_dbg0("poll none");
891 return AO_READ_AGAIN;
896 /* Pull a character out of the fifo */
897 c = ao_usb_rx_buffer[ao_usb_rx_pos++];
906 ao_arch_block_interrupts();
907 while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN)
908 ao_sleep(AO_USB_OUT_SLEEP_ADDR);
909 ao_arch_release_interrupts();
921 buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
922 ao_usb_sram_addr += AO_USB_IN_SIZE;
927 ao_usb_free(uint16_t *addr)
929 uint16_t offset = ao_usb_packet_buffer_offset(addr);
930 if (offset < ao_usb_sram_addr)
931 ao_usb_sram_addr = offset;
935 ao_usb_write(uint16_t *buffer, uint16_t len)
937 ao_arch_block_interrupts();
939 /* Flush any pending regular */
943 while (ao_usb_in_pending)
944 ao_sleep(&ao_usb_in_pending);
945 ao_usb_in_pending = 1;
946 ao_usb_in_flushed = (len != AO_USB_IN_SIZE);
947 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_packet_buffer_offset(buffer);
948 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = len;
949 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
950 ao_arch_release_interrupts();
957 ao_arch_block_interrupts();
958 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
961 /* Disable USB pull-up */
962 stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
964 /* Switch off the device */
965 stm_usb.cntr = (1 << STM_USB_CNTR_PDWN) | (1 << STM_USB_CNTR_FRES);
967 /* Disable the interface */
968 stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_USBEN);
969 ao_arch_release_interrupts();
977 /* Select HSI48 as USB clock source */
978 stm_rcc.cfgr3 &= ~(1 << STM_RCC_CFGR3_USBSW);
980 /* Enable USB device */
981 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USBEN);
983 /* Clear reset condition */
984 stm_rcc.apb1rstr &= ~(1 << STM_RCC_APB1RSTR_USBRST);
986 /* Disable USB pull-up */
987 stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
989 /* Do not touch the GPIOA configuration; USB takes priority
990 * over GPIO on pins A11 and A12, but if you select alternate
991 * input 10 (the documented correct selection), then USB is
992 * pulled low and doesn't work at all
995 ao_arch_block_interrupts();
997 /* Route interrupts */
998 stm_nvic_set_enable(STM_ISR_USB_POS);
999 stm_nvic_set_priority(STM_ISR_USB_POS, 3);
1001 ao_usb_configuration = 0;
1003 /* Set up buffer descriptors */
1004 ao_usb_init_btable();
1006 /* Reset the USB controller */
1007 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1009 /* Clear the reset bit */
1012 /* Clear any spurious interrupts */
1017 debug ("ao_usb_enable\n");
1019 /* Enable interrupts */
1020 stm_usb.cntr = ((1 << STM_USB_CNTR_CTRM) |
1021 (0 << STM_USB_CNTR_PMAOVRM) |
1022 (0 << STM_USB_CNTR_ERRM) |
1023 (0 << STM_USB_CNTR_WKUPM) |
1024 (0 << STM_USB_CNTR_SUSPM) |
1025 (1 << STM_USB_CNTR_RESETM) |
1026 (0 << STM_USB_CNTR_SOFM) |
1027 (0 << STM_USB_CNTR_ESOFM) |
1028 (0 << STM_USB_CNTR_RESUME) |
1029 (0 << STM_USB_CNTR_FSUSP) |
1030 (0 << STM_USB_CNTR_LP_MODE) |
1031 (0 << STM_USB_CNTR_PDWN) |
1032 (0 << STM_USB_CNTR_FRES));
1034 ao_arch_release_interrupts();
1036 for (t = 0; t < 1000; t++)
1039 /* Enable USB pull-up */
1040 stm_usb.bcdr |= (1 << STM_USB_BCDR_DPPU);
1044 struct ao_task ao_usb_echo_task;
1052 c = ao_usb_getchar();
1063 printf ("control: %d out: %d in: %d int: %d reset: %d\n",
1064 control_count, out_count, in_count, int_count, reset_count);
1067 __code struct ao_cmds ao_usb_cmds[] = {
1068 { ao_usb_irq, "I\0Show USB interrupt counts" },
1076 /* Turn on syscfg */
1077 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
1079 /* Set PA11/PA12 remapping bit */
1080 stm_syscfg.cfgr1 |= (AO_PA11_PA12_RMP << STM_SYSCFG_CFGR1_PA11_PA12_RMP);
1084 debug ("ao_usb_init\n");
1085 ao_usb_ep0_state = AO_USB_EP0_IDLE;
1087 ao_add_task(&ao_usb_echo_task, ao_usb_echo, "usb echo");
1090 ao_cmd_register(&ao_usb_cmds[0]);
1094 ao_add_stdio(_ao_usb_pollchar, ao_usb_putchar, ao_usb_flush);
1099 #if TX_DBG || RX_DBG
1109 uint32_t in_pending;
1111 uint32_t in_flushed;
1121 #define NUM_USB_DBG 128
1123 static struct ao_usb_dbg dbg[128];
1126 static void _dbg(int line, char *msg, uint32_t value)
1129 dbg[dbg_i].line = line;
1130 dbg[dbg_i].msg = msg;
1131 dbg[dbg_i].value = value;
1132 asm("mrs %0,primask" : "=&r" (primask));
1133 dbg[dbg_i].primask = primask;
1135 dbg[dbg_i].in_count = in_count;
1136 dbg[dbg_i].in_epr = stm_usb.epr[AO_USB_IN_EPR];
1137 dbg[dbg_i].in_pending = ao_usb_in_pending;
1138 dbg[dbg_i].tx_count = ao_usb_tx_count;
1139 dbg[dbg_i].in_flushed = ao_usb_in_flushed;
1142 dbg[dbg_i].rx_count = ao_usb_rx_count;
1143 dbg[dbg_i].rx_pos = ao_usb_rx_pos;
1144 dbg[dbg_i].out_avail = ao_usb_out_avail;
1145 dbg[dbg_i].out_epr = stm_usb.epr[AO_USB_OUT_EPR];
1147 if (++dbg_i == NUM_USB_DBG)