2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 #include "ao_product.h"
26 #define USB_DEBUG_DATA 0
29 #ifndef AO_PA11_PA12_RMP
30 #error "must define AO_PA11_PA12_RMP"
33 #ifndef AO_POWER_MANAGEMENT
34 #define AO_POWER_MANAGEMENT 0
38 #define USE_USB_STDIO 1
42 #define AO_USB_OUT_SLEEP_ADDR (&ao_stdin_ready)
44 #define AO_USB_OUT_SLEEP_ADDR (&ao_usb_out_avail)
48 #define debug(format, args...) printf(format, ## args);
50 #define debug(format, args...)
54 #define debug_data(format, args...) printf(format, ## args);
56 #define debug_data(format, args...)
60 uint8_t dir_type_recip;
67 static uint8_t ao_usb_ep0_state;
69 /* Pending EP0 IN data */
70 static const uint8_t *ao_usb_ep0_in_data; /* Remaining data */
71 static uint8_t ao_usb_ep0_in_len; /* Remaining amount */
73 /* Temp buffer for smaller EP0 in data */
74 static uint8_t ao_usb_ep0_in_buf[2];
76 /* Pending EP0 OUT data */
77 static uint8_t *ao_usb_ep0_out_data;
78 static uint8_t ao_usb_ep0_out_len;
81 * Objects allocated in special USB memory
84 /* Buffer description tables */
85 static union stm_usb_bdt *ao_usb_bdt;
86 /* USB address of end of allocated storage */
88 static uint16_t ao_usb_sram_addr;
91 /* Pointer to ep0 tx/rx buffers in USB memory */
92 static uint16_t *ao_usb_ep0_tx_buffer;
93 static uint16_t *ao_usb_ep0_rx_buffer;
96 /* Pointer to interrupt buffer in USB memory */
97 static uint16_t ao_usb_int_tx_offset;
100 /* Pointer to bulk data tx/rx buffers in USB memory */
102 static uint16_t ao_usb_in_tx_offset;
103 static uint16_t *ao_usb_in_tx_buffer;
105 /* System ram shadow of USB buffer; writing individual bytes is
106 * too much of a pain (sigh) */
107 static uint8_t ao_usb_tx_buffer[AO_USB_IN_SIZE];
108 static uint8_t ao_usb_tx_count;
112 static uint16_t ao_usb_out_rx_offset;
113 static uint16_t *ao_usb_out_rx_buffer;
115 /* System ram shadow of USB buffer; writing individual bytes is
116 * too much of a pain (sigh) */
117 static uint8_t ao_usb_rx_buffer[AO_USB_OUT_SIZE];
118 static uint8_t ao_usb_rx_count, ao_usb_rx_pos;
122 static uint16_t ao_usb_in2_tx_offset;
123 static uint16_t *ao_usb_in2_tx_buffer;
125 /* System ram shadow of USB buffer; writing individual bytes is
126 * too much of a pain (sigh) */
127 static uint8_t ao_usb_tx2_buffer[AO_USB_IN_SIZE];
128 static uint8_t ao_usb_tx2_count;
132 * End point register indices
135 #define AO_USB_CONTROL_EPR 0
136 #define AO_USB_INT_EPR 1
137 #define AO_USB_OUT_EPR 2
138 #define AO_USB_IN_EPR 3
139 #define AO_USB_IN2_EPR 4
141 /* Marks when we don't need to send an IN packet.
142 * This happens only when the last IN packet is not full,
143 * otherwise the host will expect to keep seeing packets.
144 * Send a zero-length packet as required
146 static uint8_t ao_usb_in_flushed;
148 /* Marks when we have delivered an IN packet to the hardware
149 * and it has not been received yet. ao_sleep on this address
150 * to wait for it to be delivered.
152 static uint8_t ao_usb_in_pending;
155 /* Marks when we have delivered an IN packet to the hardware
156 * and it has not been received yet. ao_sleep on this address
157 * to wait for it to be delivered.
159 static uint8_t ao_usb_in2_pending;
160 static uint16_t in2_count;
161 static uint8_t ao_usb_in2_flushed;
164 /* Marks when an OUT packet has been received by the hardware
165 * but not pulled to the shadow buffer.
167 static uint8_t ao_usb_out_avail;
168 uint8_t ao_usb_running;
169 static uint8_t ao_usb_configuration;
171 #define AO_USB_EP0_GOT_SETUP 1
172 #define AO_USB_EP0_GOT_RX_DATA 2
173 #define AO_USB_EP0_GOT_TX_ACK 4
175 static uint8_t ao_usb_ep0_receive;
176 static uint8_t ao_usb_address;
177 static uint8_t ao_usb_address_pending;
179 static inline uint32_t set_toggle(uint32_t current_value,
181 uint32_t desired_value)
183 return (current_value ^ desired_value) & mask;
186 static inline uint16_t *ao_usb_packet_buffer_addr(uint16_t sram_addr)
188 return (uint16_t *) (void *) (stm_usb_sram + sram_addr);
191 static inline uint16_t ao_usb_packet_buffer_offset(uint16_t *addr)
193 return (uint16_t) ((uint8_t *) addr - stm_usb_sram);
196 static inline uint32_t ao_usb_epr_stat_rx(uint32_t epr) {
197 return (epr >> STM_USB_EPR_STAT_RX) & STM_USB_EPR_STAT_RX_MASK;
200 static inline uint32_t ao_usb_epr_stat_tx(uint32_t epr) {
201 return (epr >> STM_USB_EPR_STAT_TX) & STM_USB_EPR_STAT_TX_MASK;
204 static inline uint32_t ao_usb_epr_ctr_rx(uint32_t epr) {
205 return (epr >> STM_USB_EPR_CTR_RX) & 1;
208 static inline uint32_t ao_usb_epr_ctr_tx(uint32_t epr) {
209 return (epr >> STM_USB_EPR_CTR_TX) & 1;
212 static inline uint32_t ao_usb_epr_setup(uint32_t epr) {
213 return (epr >> STM_USB_EPR_SETUP) & 1;
216 static inline uint32_t ao_usb_epr_dtog_rx(uint32_t epr) {
217 return (epr >> STM_USB_EPR_DTOG_RX) & 1;
220 static inline uint32_t ao_usb_epr_dtog_tx(uint32_t epr) {
221 return (epr >> STM_USB_EPR_DTOG_TX) & 1;
225 * Set current device address and mark the
226 * interface as active
229 ao_usb_set_address(uint8_t address)
231 debug("ao_usb_set_address %02x\n", address);
232 stm_usb.daddr = (1 << STM_USB_DADDR_EF) | address;
233 ao_usb_address_pending = 0;
237 * Write these values to preserve register contents under HW changes
240 #define STM_USB_EPR_INVARIANT ((1 << STM_USB_EPR_CTR_RX) | \
241 (STM_USB_EPR_DTOG_RX_WRITE_INVARIANT << STM_USB_EPR_DTOG_RX) | \
242 (STM_USB_EPR_STAT_RX_WRITE_INVARIANT << STM_USB_EPR_STAT_RX) | \
243 (1 << STM_USB_EPR_CTR_TX) | \
244 (STM_USB_EPR_DTOG_TX_WRITE_INVARIANT << STM_USB_EPR_DTOG_TX) | \
245 (STM_USB_EPR_STAT_TX_WRITE_INVARIANT << STM_USB_EPR_STAT_TX))
247 #define STM_USB_EPR_INVARIANT_MASK ((1 << STM_USB_EPR_CTR_RX) | \
248 (STM_USB_EPR_DTOG_RX_MASK << STM_USB_EPR_DTOG_RX) | \
249 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) | \
250 (1 << STM_USB_EPR_CTR_TX) | \
251 (STM_USB_EPR_DTOG_TX_MASK << STM_USB_EPR_DTOG_TX) | \
252 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX))
255 * These bits are purely under sw control, so preserve them in the
256 * register by re-writing what was read
258 #define STM_USB_EPR_PRESERVE_MASK ((STM_USB_EPR_EP_TYPE_MASK << STM_USB_EPR_EP_TYPE) | \
259 (1 << STM_USB_EPR_EP_KIND) | \
260 (STM_USB_EPR_EA_MASK << STM_USB_EPR_EA))
266 #define _tx_dbg0(msg) _dbg(__LINE__,msg,0)
267 #define _tx_dbg1(msg,value) _dbg(__LINE__,msg,value)
269 #define _tx_dbg0(msg)
270 #define _tx_dbg1(msg,value)
274 #define _rx_dbg0(msg) _dbg(__LINE__,msg,0)
275 #define _rx_dbg1(msg,value) _dbg(__LINE__,msg,value)
277 #define _rx_dbg0(msg)
278 #define _rx_dbg1(msg,value)
282 static void _dbg(int line, char *msg, uint32_t value);
286 * Set the state of the specified endpoint register to a new
287 * value. This is tricky because the bits toggle where the new
288 * value is one, and we need to write invariant values in other
289 * spots of the register. This hardware is strange...
292 _ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
294 uint16_t epr_write, epr_old;
296 _tx_dbg1("set_stat_tx top", stat_tx);
297 epr_old = epr_write = stm_usb.epr[ep].r;
298 epr_write &= STM_USB_EPR_PRESERVE_MASK;
299 epr_write |= STM_USB_EPR_INVARIANT;
300 epr_write |= set_toggle(epr_old,
301 STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX,
302 stat_tx << STM_USB_EPR_STAT_TX);
303 stm_usb.epr[ep].r = epr_write;
304 _tx_dbg1("set_stat_tx bottom", epr_write);
308 ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
310 ao_arch_block_interrupts();
311 _ao_usb_set_stat_tx(ep, stat_tx);
312 ao_arch_release_interrupts();
316 _ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
317 uint16_t epr_write, epr_old;
319 epr_write = epr_old = stm_usb.epr[ep].r;
320 epr_write &= STM_USB_EPR_PRESERVE_MASK;
321 epr_write |= STM_USB_EPR_INVARIANT;
322 epr_write |= set_toggle(epr_old,
323 STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX,
324 stat_rx << STM_USB_EPR_STAT_RX);
325 stm_usb.epr[ep].r = epr_write;
329 ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
330 ao_arch_block_interrupts();
331 _ao_usb_set_stat_rx(ep, stat_rx);
332 ao_arch_release_interrupts();
336 * Set just endpoint 0, for use during startup
340 ao_usb_init_ep(uint8_t ep, uint32_t addr, uint32_t type, uint32_t stat_rx, uint32_t stat_tx)
344 ao_arch_block_interrupts();
345 epr = stm_usb.epr[ep].r;
346 epr = ((0 << STM_USB_EPR_CTR_RX) |
347 (epr & (1 << STM_USB_EPR_DTOG_RX)) |
349 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX),
350 (stat_rx << STM_USB_EPR_STAT_RX)) |
351 (type << STM_USB_EPR_EP_TYPE) |
352 (0 << STM_USB_EPR_EP_KIND) |
353 (0 << STM_USB_EPR_CTR_TX) |
354 (epr & (1 << STM_USB_EPR_DTOG_TX)) |
356 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX),
357 (stat_tx << STM_USB_EPR_STAT_TX)) |
358 (addr << STM_USB_EPR_EA));
359 stm_usb.epr[ep].r = epr;
360 ao_arch_release_interrupts();
361 debug ("writing epr[%d] 0x%04x wrote 0x%04x\n",
362 ep, epr, stm_usb.epr[ep].r);
366 ao_usb_alloc_buffers(void)
368 uint16_t sram_addr = 0;
370 ao_usb_bdt = (void *) stm_usb_sram;
371 sram_addr += 8 * STM_USB_BDT_SIZE;
373 ao_usb_ep0_tx_buffer = ao_usb_packet_buffer_addr(sram_addr);
374 sram_addr += AO_USB_CONTROL_SIZE;
376 ao_usb_ep0_rx_buffer = ao_usb_packet_buffer_addr(sram_addr);
377 sram_addr += AO_USB_CONTROL_SIZE;
381 ao_usb_int_tx_offset = sram_addr;
382 sram_addr += AO_USB_INT_SIZE;
386 ao_usb_out_rx_buffer = ao_usb_packet_buffer_addr(sram_addr);
387 ao_usb_out_rx_offset = sram_addr;
388 sram_addr += AO_USB_OUT_SIZE;
392 ao_usb_in_tx_buffer = ao_usb_packet_buffer_addr(sram_addr);
393 ao_usb_in_tx_offset = sram_addr;
394 sram_addr += AO_USB_IN_SIZE;
398 ao_usb_in2_tx_buffer = ao_usb_packet_buffer_addr(sram_addr);
399 ao_usb_in2_tx_offset = sram_addr;
400 sram_addr += AO_USB_IN_SIZE;
404 ao_usb_sram_addr = sram_addr;
409 ao_usb_init_btable(void)
411 /* Set up EP 0 - a Control end point with 32 bytes of in and out buffers */
413 ao_usb_bdt[0].single.addr_tx = ao_usb_packet_buffer_offset(ao_usb_ep0_tx_buffer);
414 ao_usb_bdt[0].single.count_tx = 0;
416 ao_usb_bdt[0].single.addr_rx = ao_usb_packet_buffer_offset(ao_usb_ep0_rx_buffer);
417 ao_usb_bdt[0].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
418 (((AO_USB_CONTROL_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
426 ao_usb_init_btable();
428 /* buffer table is at the start of USB memory */
431 ao_usb_init_ep(AO_USB_CONTROL_EPR, AO_USB_CONTROL_EP,
432 STM_USB_EPR_EP_TYPE_CONTROL,
433 STM_USB_EPR_STAT_RX_VALID,
434 STM_USB_EPR_STAT_TX_NAK);
436 /* Clear all of the other endpoints */
437 for (e = 1; e < 8; e++) {
439 STM_USB_EPR_EP_TYPE_CONTROL,
440 STM_USB_EPR_STAT_RX_DISABLED,
441 STM_USB_EPR_STAT_TX_DISABLED);
444 ao_usb_set_address(0);
448 /* Reset our internal state
451 ao_usb_ep0_state = AO_USB_EP0_IDLE;
453 ao_usb_ep0_in_data = NULL;
454 ao_usb_ep0_in_len = 0;
456 ao_usb_ep0_out_data = 0;
457 ao_usb_ep0_out_len = 0;
461 ao_usb_set_configuration(void)
463 debug ("ao_usb_set_configuration\n");
466 /* Set up the INT end point */
467 ao_usb_bdt[AO_USB_INT_EPR].single.addr_tx = ao_usb_int_tx_offset;
468 ao_usb_bdt[AO_USB_INT_EPR].single.count_tx = 0;
470 ao_usb_init_ep(AO_USB_INT_EPR,
472 STM_USB_EPR_EP_TYPE_INTERRUPT,
473 STM_USB_EPR_STAT_RX_DISABLED,
474 STM_USB_EPR_STAT_TX_NAK);
478 /* Set up the OUT end point */
479 ao_usb_bdt[AO_USB_OUT_EPR].single.addr_rx = ao_usb_out_rx_offset;
480 ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
481 (((AO_USB_OUT_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
483 ao_usb_init_ep(AO_USB_OUT_EPR,
485 STM_USB_EPR_EP_TYPE_BULK,
486 STM_USB_EPR_STAT_RX_VALID,
487 STM_USB_EPR_STAT_TX_DISABLED);
491 /* Set up the IN end point */
492 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_in_tx_offset;
493 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = 0;
495 ao_usb_init_ep(AO_USB_IN_EPR,
497 STM_USB_EPR_EP_TYPE_BULK,
498 STM_USB_EPR_STAT_RX_DISABLED,
499 STM_USB_EPR_STAT_TX_NAK);
503 /* Set up the IN2 end point */
504 ao_usb_bdt[AO_USB_IN2_EPR].single.addr_tx = ao_usb_in2_tx_offset;
505 ao_usb_bdt[AO_USB_IN2_EPR].single.count_tx = 0;
507 ao_usb_init_ep(AO_USB_IN2_EPR,
509 STM_USB_EPR_EP_TYPE_BULK,
510 STM_USB_EPR_STAT_RX_DISABLED,
511 STM_USB_EPR_STAT_TX_NAK);
514 ao_usb_in_flushed = 0;
515 ao_usb_in_pending = 0;
516 ao_wakeup(&ao_usb_in_pending);
518 ao_usb_in2_flushed = 0;
519 ao_usb_in2_pending = 0;
520 ao_wakeup(&ao_usb_in2_pending);
523 ao_usb_out_avail = 0;
524 ao_usb_configuration = 0;
526 ao_wakeup(AO_USB_OUT_SLEEP_ADDR);
530 ao_wakeup(&ao_usb_running);
535 static uint16_t control_count;
536 static uint16_t int_count;
537 static uint16_t in_count;
538 static uint16_t out_count;
539 static uint16_t reset_count;
542 /* The USB memory must be accessed in 16-bit units
546 ao_usb_copy_tx(const uint8_t *src, uint16_t *base, uint16_t bytes)
549 *base++ = src[0] | (src[1] << 8);
558 ao_usb_copy_rx(uint8_t *dst, uint16_t *base, uint16_t bytes)
561 uint16_t s = *base++;
571 /* Send an IN data packet */
573 ao_usb_ep0_flush(void)
577 /* Check to see if the endpoint is still busy */
578 if (ao_usb_epr_stat_tx(stm_usb.epr[0].r) == STM_USB_EPR_STAT_TX_VALID) {
579 debug("EP0 not accepting IN data\n");
583 this_len = ao_usb_ep0_in_len;
584 if (this_len > AO_USB_CONTROL_SIZE)
585 this_len = AO_USB_CONTROL_SIZE;
587 if (this_len < AO_USB_CONTROL_SIZE)
588 ao_usb_ep0_state = AO_USB_EP0_IDLE;
590 ao_usb_ep0_in_len -= this_len;
592 debug_data ("Flush EP0 len %d:", this_len);
593 ao_usb_copy_tx(ao_usb_ep0_in_data, ao_usb_ep0_tx_buffer, this_len);
595 ao_usb_ep0_in_data += this_len;
597 /* Mark the endpoint as TX valid to send the packet */
598 ao_usb_bdt[AO_USB_CONTROL_EPR].single.count_tx = this_len;
599 ao_usb_set_stat_tx(AO_USB_CONTROL_EPR, STM_USB_EPR_STAT_TX_VALID);
600 debug ("queue tx. epr 0 now %08x\n", stm_usb.epr[AO_USB_CONTROL_EPR]);
603 /* Read data from the ep0 OUT fifo */
605 ao_usb_ep0_fill(void)
607 uint16_t len = ao_usb_bdt[0].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
609 if (len > ao_usb_ep0_out_len)
610 len = ao_usb_ep0_out_len;
611 ao_usb_ep0_out_len -= len;
613 /* Pull all of the data out of the packet */
614 debug_data ("Fill EP0 len %d:", len);
615 ao_usb_copy_rx(ao_usb_ep0_out_data, ao_usb_ep0_rx_buffer, len);
617 ao_usb_ep0_out_data += len;
620 ao_usb_set_stat_rx(0, STM_USB_EPR_STAT_RX_VALID);
624 ao_usb_ep0_in_reset(void)
626 ao_usb_ep0_in_data = ao_usb_ep0_in_buf;
627 ao_usb_ep0_in_len = 0;
631 ao_usb_ep0_in_queue_byte(uint8_t a)
633 if (ao_usb_ep0_in_len < sizeof (ao_usb_ep0_in_buf))
634 ao_usb_ep0_in_buf[ao_usb_ep0_in_len++] = a;
638 ao_usb_ep0_in_set(const uint8_t *data, uint8_t len)
640 ao_usb_ep0_in_data = data;
641 ao_usb_ep0_in_len = len;
645 ao_usb_ep0_out_set(uint8_t *data, uint8_t len)
647 ao_usb_ep0_out_data = data;
648 ao_usb_ep0_out_len = len;
652 ao_usb_ep0_in_start(uint16_t max)
654 /* Don't send more than asked for */
655 if (ao_usb_ep0_in_len > max)
656 ao_usb_ep0_in_len = max;
660 struct ao_usb_line_coding ao_usb_line_coding = {115200, 0, 0, 8};
662 #if AO_USB_DEVICE_ID_SERIAL
663 static uint8_t ao_usb_serial[2 + 48];
665 /* Convert a 32-bit value to 8 hexidecimal UCS2 characters */
667 hex_to_ucs2(uint32_t in, uint8_t *out)
671 for (i = 28; i >= 0; i -= 4) {
672 uint8_t bits = (in >> i) & 0xf;
673 *out++ = ((bits < 10) ? '0' : ('a' - 10)) + bits;
678 /* Encode the device ID (96 bits) in hexidecimal to use as a device
682 ao_usb_serial_init(void)
684 ao_usb_serial[0] = 50; /* length */
685 ao_usb_serial[1] = AO_USB_DESC_STRING;
686 hex_to_ucs2(stm_device_id.u_id0, ao_usb_serial + 2 + 0);
687 hex_to_ucs2(stm_device_id.u_id1, ao_usb_serial + 2 + 16);
688 hex_to_ucs2(stm_device_id.u_id2, ao_usb_serial + 2 + 32);
692 /* Walk through the list of descriptors and find a match
695 ao_usb_get_descriptor(uint16_t value, uint16_t length)
697 const uint8_t *descriptor;
698 uint8_t type = value >> 8;
699 uint8_t index = value;
701 descriptor = ao_usb_descriptors;
702 while (descriptor[0] != 0) {
703 if (descriptor[1] == type && index-- == 0) {
705 if (type == AO_USB_DESC_CONFIGURATION)
709 #if AO_USB_DEVICE_ID_SERIAL
710 /* Slightly hacky - the serial number is string 3 */
711 if (type == AO_USB_DESC_STRING && (value & 0xff) == 3) {
712 descriptor = ao_usb_serial;
713 len = sizeof (ao_usb_serial);
718 ao_usb_ep0_in_set(descriptor, len);
721 descriptor += descriptor[0];
726 ao_usb_ep0_setup(void)
728 /* Pull the setup packet out of the fifo */
729 ao_usb_ep0_out_set((uint8_t *) &ao_usb_setup, 8);
731 if (ao_usb_ep0_out_len != 0) {
732 debug ("invalid setup packet length\n");
736 if ((ao_usb_setup.dir_type_recip & AO_USB_DIR_IN) || ao_usb_setup.length == 0)
737 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
739 ao_usb_ep0_state = AO_USB_EP0_DATA_OUT;
741 ao_usb_ep0_in_reset();
743 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_TYPE_MASK) {
744 case AO_USB_TYPE_STANDARD:
745 debug ("Standard setup packet\n");
746 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_RECIP_MASK) {
747 case AO_USB_RECIP_DEVICE:
748 debug ("Device setup packet\n");
749 switch(ao_usb_setup.request) {
750 case AO_USB_REQ_GET_STATUS:
751 debug ("get status\n");
752 ao_usb_ep0_in_queue_byte(0);
753 ao_usb_ep0_in_queue_byte(0);
755 case AO_USB_REQ_SET_ADDRESS:
756 debug ("set address %d\n", ao_usb_setup.value);
757 ao_usb_address = ao_usb_setup.value;
758 ao_usb_address_pending = 1;
760 case AO_USB_REQ_GET_DESCRIPTOR:
761 debug ("get descriptor %d\n", ao_usb_setup.value);
762 ao_usb_get_descriptor(ao_usb_setup.value, ao_usb_setup.length);
764 case AO_USB_REQ_GET_CONFIGURATION:
765 debug ("get configuration %d\n", ao_usb_configuration);
766 ao_usb_ep0_in_queue_byte(ao_usb_configuration);
768 case AO_USB_REQ_SET_CONFIGURATION:
769 ao_usb_configuration = ao_usb_setup.value;
770 debug ("set configuration %d\n", ao_usb_configuration);
771 ao_usb_set_configuration();
775 case AO_USB_RECIP_INTERFACE:
776 debug ("Interface setup packet\n");
777 switch(ao_usb_setup.request) {
778 case AO_USB_REQ_GET_STATUS:
779 ao_usb_ep0_in_queue_byte(0);
780 ao_usb_ep0_in_queue_byte(0);
782 case AO_USB_REQ_GET_INTERFACE:
783 ao_usb_ep0_in_queue_byte(0);
785 case AO_USB_REQ_SET_INTERFACE:
789 case AO_USB_RECIP_ENDPOINT:
790 debug ("Endpoint setup packet\n");
791 switch(ao_usb_setup.request) {
792 case AO_USB_REQ_GET_STATUS:
793 ao_usb_ep0_in_queue_byte(0);
794 ao_usb_ep0_in_queue_byte(0);
800 case AO_USB_TYPE_CLASS:
801 debug ("Class setup packet\n");
802 switch (ao_usb_setup.request) {
803 case AO_USB_SET_LINE_CODING:
804 debug ("set line coding\n");
805 ao_usb_ep0_out_set((uint8_t *) &ao_usb_line_coding, 7);
807 case AO_USB_GET_LINE_CODING:
808 debug ("get line coding\n");
809 ao_usb_ep0_in_set((const uint8_t *) &ao_usb_line_coding, 7);
811 case AO_USB_SET_CONTROL_LINE_STATE:
817 /* If we're not waiting to receive data from the host,
818 * queue an IN response
820 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
821 ao_usb_ep0_in_start(ao_usb_setup.length);
825 ao_usb_ep0_handle(uint8_t receive)
827 ao_usb_ep0_receive = 0;
828 if (receive & AO_USB_EP0_GOT_SETUP) {
832 if (receive & AO_USB_EP0_GOT_RX_DATA) {
833 debug ("\tgot rx data\n");
834 if (ao_usb_ep0_state == AO_USB_EP0_DATA_OUT) {
836 if (ao_usb_ep0_out_len == 0) {
837 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
838 ao_usb_ep0_in_start(0);
842 if (receive & AO_USB_EP0_GOT_TX_ACK) {
843 debug ("\tgot tx ack\n");
845 #if HAS_FLIGHT && AO_USB_FORCE_IDLE
846 ao_flight_force_idle = 1;
848 /* Wait until the IN packet is received from addr 0
849 * before assigning our local address
851 if (ao_usb_address_pending)
852 ao_usb_set_address(ao_usb_address);
853 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
858 #if AO_POWER_MANAGEMENT
862 stm_usb.cntr |= (1 << STM_USB_CNTR_FSUSP);
864 stm_usb.cntr |= (1 << STM_USB_CNTR_LP_MODE);
872 stm_usb.cntr &= ~(1 << STM_USB_CNTR_FSUSP);
880 uint32_t istr = stm_usb.istr;
882 stm_usb.istr = ~istr;
883 if (istr & (1 << STM_USB_ISTR_CTR)) {
884 uint8_t ep = istr & STM_USB_ISTR_EP_ID_MASK;
885 uint16_t epr, epr_write;
887 /* Preserve the SW write bits, don't mess with most HW writable bits,
888 * clear the CTR_RX and CTR_TX bits
890 epr = stm_usb.epr[ep].r;
892 epr_write &= STM_USB_EPR_PRESERVE_MASK;
893 epr_write |= STM_USB_EPR_INVARIANT;
894 epr_write &= ~(1 << STM_USB_EPR_CTR_RX);
895 epr_write &= ~(1 << STM_USB_EPR_CTR_TX);
896 stm_usb.epr[ep].r = epr_write;
903 if (ao_usb_epr_ctr_rx(epr)) {
904 if (ao_usb_epr_setup(epr))
905 ao_usb_ep0_receive |= AO_USB_EP0_GOT_SETUP;
907 ao_usb_ep0_receive |= AO_USB_EP0_GOT_RX_DATA;
909 if (ao_usb_epr_ctr_tx(epr))
910 ao_usb_ep0_receive |= AO_USB_EP0_GOT_TX_ACK;
911 ao_usb_ep0_handle(ao_usb_ep0_receive);
917 if (ao_usb_epr_ctr_rx(epr)) {
918 _rx_dbg1("RX ISR", epr);
919 ao_usb_out_avail = 1;
920 _rx_dbg0("out avail set");
921 ao_wakeup(AO_USB_OUT_SLEEP_ADDR);
922 _rx_dbg0("stdin awoken");
929 _tx_dbg1("TX ISR", epr);
930 if (ao_usb_epr_ctr_tx(epr)) {
931 ao_usb_in_pending = 0;
932 ao_wakeup(&ao_usb_in_pending);
938 _tx_dbg1("TX2 ISR", epr);
939 if (ao_usb_epr_ctr_tx(epr)) {
940 ao_usb_in2_pending = 0;
941 ao_wakeup(&ao_usb_in2_pending);
949 if (ao_usb_epr_ctr_tx(epr))
950 _ao_usb_set_stat_tx(AO_USB_INT_EPR, STM_USB_EPR_STAT_TX_NAK);
956 if (istr & (1 << STM_USB_ISTR_RESET)) {
963 #if AO_POWER_MANAGEMENT
964 if (istr & (1 << STM_USB_ISTR_SUSP)) {
965 debug ("\tsuspend\n");
968 if (istr & (1 << STM_USB_ISTR_WKUP)) {
969 debug ("\twakeup\n");
976 /* Queue the current IN buffer for transmission */
978 _ao_usb_in_send(void)
980 _tx_dbg0("in_send start");
981 debug ("send %d\n", ao_usb_tx_count);
982 while (ao_usb_in_pending)
983 ao_sleep(&ao_usb_in_pending);
984 ao_usb_in_pending = 1;
985 if (ao_usb_tx_count != AO_USB_IN_SIZE)
986 ao_usb_in_flushed = 1;
987 ao_usb_copy_tx(ao_usb_tx_buffer, ao_usb_in_tx_buffer, ao_usb_tx_count);
988 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_in_tx_offset;
989 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = ao_usb_tx_count;
991 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
992 _tx_dbg0("in_send end");
995 /* Wait for a free IN buffer. Interrupts are blocked */
997 _ao_usb_in_wait(void)
1000 /* Check if the current buffer is writable */
1001 if (ao_usb_tx_count < AO_USB_IN_SIZE)
1004 _tx_dbg0("in_wait top");
1005 /* Wait for an IN buffer to be ready */
1006 while (ao_usb_in_pending)
1007 ao_sleep(&ao_usb_in_pending);
1008 _tx_dbg0("in_wait bottom");
1015 if (!ao_usb_running)
1018 /* Anytime we've sent a character since
1019 * the last time we flushed, we'll need
1020 * to send a packet -- the only other time
1021 * we would send a packet is when that
1022 * packet was full, in which case we now
1023 * want to send an empty packet
1025 ao_arch_block_interrupts();
1026 while (!ao_usb_in_flushed) {
1027 _tx_dbg0("flush top");
1029 _tx_dbg0("flush end");
1031 ao_arch_release_interrupts();
1035 ao_usb_putchar(char c)
1037 if (!ao_usb_running)
1040 ao_arch_block_interrupts();
1043 ao_usb_in_flushed = 0;
1044 ao_usb_tx_buffer[ao_usb_tx_count++] = (uint8_t) c;
1046 /* Send the packet when full */
1047 if (ao_usb_tx_count == AO_USB_IN_SIZE) {
1048 _tx_dbg0("putchar full");
1050 _tx_dbg0("putchar flushed");
1052 ao_arch_release_interrupts();
1057 /* Queue the current IN buffer for transmission */
1059 _ao_usb_in2_send(void)
1061 _tx_dbg0("in2_send start");
1062 debug ("send2 %d\n", ao_usb_tx_count);
1063 while (ao_usb_in2_pending)
1064 ao_sleep(&ao_usb_in2_pending);
1065 ao_usb_in2_pending = 1;
1066 if (ao_usb_tx2_count != AO_USB_IN_SIZE)
1067 ao_usb_in2_flushed = 1;
1068 ao_usb_copy_tx(ao_usb_tx2_buffer, ao_usb_in2_tx_buffer, ao_usb_tx2_count);
1069 ao_usb_bdt[AO_USB_IN2_EPR].single.addr_tx = ao_usb_in_tx_offset;
1070 ao_usb_bdt[AO_USB_IN2_EPR].single.count_tx = ao_usb_tx_count;
1071 ao_usb_tx2_count = 0;
1072 _ao_usb_set_stat_tx(AO_USB_IN2_EPR, STM_USB_EPR_STAT_TX_VALID);
1073 _tx_dbg0("in2_send end");
1076 /* Wait for a free IN buffer. Interrupts are blocked */
1078 _ao_usb_in2_wait(void)
1081 /* Check if the current buffer is writable */
1082 if (ao_usb_tx2_count < AO_USB_IN_SIZE)
1085 _tx_dbg0("in2_wait top");
1086 /* Wait for an IN buffer to be ready */
1087 while (ao_usb_in2_pending)
1088 ao_sleep(&ao_usb_in2_pending);
1089 _tx_dbg0("in_wait bottom");
1096 if (!ao_usb_running)
1099 /* Anytime we've sent a character since
1100 * the last time we flushed, we'll need
1101 * to send a packet -- the only other time
1102 * we would send a packet is when that
1103 * packet was full, in which case we now
1104 * want to send an empty packet
1106 ao_arch_block_interrupts();
1107 while (!ao_usb_in2_flushed) {
1108 _tx_dbg0("flush2 top");
1110 _tx_dbg0("flush2 end");
1112 ao_arch_release_interrupts();
1116 ao_usb_putchar2(char c)
1118 if (!ao_usb_running)
1121 ao_arch_block_interrupts();
1124 ao_usb_in2_flushed = 0;
1125 ao_usb_tx2_buffer[ao_usb_tx2_count++] = (uint8_t) c;
1127 /* Send the packet when full */
1128 if (ao_usb_tx2_count == AO_USB_IN_SIZE) {
1129 _tx_dbg0("putchar2 full");
1131 _tx_dbg0("putchar2 flushed");
1133 ao_arch_release_interrupts();
1139 _ao_usb_out_recv(void)
1141 _rx_dbg0("out_recv top");
1142 ao_usb_out_avail = 0;
1144 ao_usb_rx_count = ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
1146 _rx_dbg1("out_recv count", ao_usb_rx_count);
1147 debug ("recv %d\n", ao_usb_rx_count);
1148 debug_data("Fill OUT len %d:", ao_usb_rx_count);
1149 ao_usb_copy_rx(ao_usb_rx_buffer, ao_usb_out_rx_buffer, ao_usb_rx_count);
1153 /* ACK the packet */
1154 _ao_usb_set_stat_rx(AO_USB_OUT_EPR, STM_USB_EPR_STAT_RX_VALID);
1158 _ao_usb_pollchar(void)
1162 if (!ao_usb_running)
1163 return AO_READ_AGAIN;
1166 if (ao_usb_rx_pos != ao_usb_rx_count)
1169 _rx_dbg0("poll check");
1170 /* Check to see if a packet has arrived */
1171 if (!ao_usb_out_avail) {
1172 _rx_dbg0("poll none");
1173 return AO_READ_AGAIN;
1178 /* Pull a character out of the fifo */
1179 c = ao_usb_rx_buffer[ao_usb_rx_pos++];
1184 ao_usb_getchar(void)
1188 ao_arch_block_interrupts();
1189 while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN)
1190 ao_sleep(AO_USB_OUT_SLEEP_ADDR);
1191 ao_arch_release_interrupts();
1202 buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
1203 ao_usb_sram_addr += AO_USB_IN_SIZE;
1208 ao_usb_write(uint16_t *buffer, uint16_t len)
1210 ao_arch_block_interrupts();
1212 /* Wait for everything to be ready at the same time */
1214 /* Make sure USB is connected */
1215 if (!ao_usb_running) {
1216 ao_sleep(&ao_usb_running);
1220 /* Flush any pending regular I/O */
1221 if (ao_usb_tx_count) {
1226 /* Wait for an idle IN buffer */
1227 if (ao_usb_in_pending) {
1228 ao_sleep(&ao_usb_in_pending);
1234 ao_usb_in_pending = 1;
1235 ao_usb_in_flushed = (len != AO_USB_IN_SIZE);
1236 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_packet_buffer_offset(buffer);
1237 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = len;
1238 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
1239 ao_arch_release_interrupts();
1244 ao_usb_write2(uint16_t *buffer, uint16_t len)
1246 ao_arch_block_interrupts();
1248 /* Wait for everything to be ready at the same time */
1250 /* Make sure USB is connected */
1251 if (!ao_usb_running) {
1252 ao_sleep(&ao_usb_running);
1256 /* Flush any pending regular I/O */
1257 if (ao_usb_tx2_count) {
1262 /* Wait for an idle IN buffer */
1263 if (ao_usb_in2_pending) {
1264 ao_sleep(&ao_usb_in2_pending);
1270 ao_usb_in2_pending = 1;
1271 ao_usb_in2_flushed = (len != AO_USB_IN_SIZE);
1272 ao_usb_bdt[AO_USB_IN2_EPR].single.addr_tx = ao_usb_packet_buffer_offset(buffer);
1273 ao_usb_bdt[AO_USB_IN2_EPR].single.count_tx = len;
1274 _ao_usb_set_stat_tx(AO_USB_IN2_EPR, STM_USB_EPR_STAT_TX_VALID);
1275 ao_arch_release_interrupts();
1281 ao_usb_disable(void)
1283 ao_arch_block_interrupts();
1284 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1287 /* Disable USB pull-up */
1288 stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
1290 /* Switch off the device */
1291 stm_usb.cntr = (1 << STM_USB_CNTR_PDWN) | (1 << STM_USB_CNTR_FRES);
1293 /* Disable the interface */
1294 stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_USBEN);
1295 ao_arch_release_interrupts();
1303 /* Select HSI48 as USB clock source */
1304 stm_rcc.cfgr3 &= ~(1 << STM_RCC_CFGR3_USBSW);
1306 /* Enable USB device */
1307 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USBEN);
1309 /* Clear reset condition */
1310 stm_rcc.apb1rstr &= ~(1 << STM_RCC_APB1RSTR_USBRST);
1312 /* Disable USB pull-up */
1313 stm_usb.bcdr &= ~(1 << STM_USB_BCDR_DPPU);
1315 /* Do not touch the GPIOA configuration; USB takes priority
1316 * over GPIO on pins A11 and A12, but if you select alternate
1317 * input 10 (the documented correct selection), then USB is
1318 * pulled low and doesn't work at all
1321 ao_arch_block_interrupts();
1323 /* Route interrupts */
1324 stm_nvic_set_enable(STM_ISR_USB_POS);
1325 stm_nvic_set_priority(STM_ISR_USB_POS, 3);
1327 ao_usb_configuration = 0;
1329 /* Set up buffer descriptors */
1330 ao_usb_init_btable();
1332 /* Reset the USB controller */
1333 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1335 /* Clear the reset bit */
1338 /* Clear any spurious interrupts */
1343 debug ("ao_usb_enable\n");
1345 /* Enable interrupts */
1346 stm_usb.cntr = ((1 << STM_USB_CNTR_CTRM) |
1347 (0 << STM_USB_CNTR_PMAOVRM) |
1348 (0 << STM_USB_CNTR_ERRM) |
1349 (AO_POWER_MANAGEMENT << STM_USB_CNTR_WKUPM) |
1350 (AO_POWER_MANAGEMENT << STM_USB_CNTR_SUSPM) |
1351 (1 << STM_USB_CNTR_RESETM) |
1352 (0 << STM_USB_CNTR_SOFM) |
1353 (0 << STM_USB_CNTR_ESOFM) |
1354 (0 << STM_USB_CNTR_RESUME) |
1355 (0 << STM_USB_CNTR_FSUSP) |
1356 (0 << STM_USB_CNTR_LP_MODE) |
1357 (0 << STM_USB_CNTR_PDWN) |
1358 (0 << STM_USB_CNTR_FRES));
1360 ao_arch_release_interrupts();
1362 for (t = 0; t < 1000; t++)
1365 /* Enable USB pull-up */
1366 stm_usb.bcdr |= (1 << STM_USB_BCDR_DPPU);
1370 struct ao_task ao_usb_echo_task;
1378 c = ao_usb_getchar();
1389 printf ("control: %d out: %d in: %d int: %d reset: %d\n",
1390 control_count, out_count, in_count, int_count, reset_count);
1393 __code struct ao_cmds ao_usb_cmds[] = {
1394 { ao_usb_irq, "I\0Show USB interrupt counts" },
1402 /* Turn on syscfg */
1403 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
1405 /* Set PA11/PA12 remapping bit */
1406 stm_syscfg.cfgr1 |= (AO_PA11_PA12_RMP << STM_SYSCFG_CFGR1_PA11_PA12_RMP);
1408 #ifndef AO_USB_START_DISABLED
1412 #if AO_USB_DEVICE_ID_SERIAL
1413 ao_usb_serial_init();
1416 debug ("ao_usb_init\n");
1417 ao_usb_ep0_state = AO_USB_EP0_IDLE;
1419 ao_usb_alloc_buffers();
1422 ao_add_task(&ao_usb_echo_task, ao_usb_echo, "usb echo");
1425 ao_cmd_register(&ao_usb_cmds[0]);
1429 ao_add_stdio(_ao_usb_pollchar, ao_usb_putchar, ao_usb_flush);
1434 #if TX_DBG || RX_DBG
1444 uint32_t in_pending;
1446 uint32_t in_flushed;
1456 #define NUM_USB_DBG 128
1458 static struct ao_usb_dbg dbg[128];
1461 static void _dbg(int line, char *msg, uint32_t value)
1464 dbg[dbg_i].line = line;
1465 dbg[dbg_i].msg = msg;
1466 dbg[dbg_i].value = value;
1467 asm("mrs %0,primask" : "=&r" (primask));
1468 dbg[dbg_i].primask = primask;
1470 dbg[dbg_i].in_count = in_count;
1471 dbg[dbg_i].in_epr = stm_usb.epr[AO_USB_IN_EPR];
1472 dbg[dbg_i].in_pending = ao_usb_in_pending;
1473 dbg[dbg_i].tx_count = ao_usb_tx_count;
1474 dbg[dbg_i].in_flushed = ao_usb_in_flushed;
1477 dbg[dbg_i].rx_count = ao_usb_rx_count;
1478 dbg[dbg_i].rx_pos = ao_usb_rx_pos;
1479 dbg[dbg_i].out_avail = ao_usb_out_avail;
1480 dbg[dbg_i].out_epr = stm_usb.epr[AO_USB_OUT_EPR];
1482 if (++dbg_i == NUM_USB_DBG)