2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 #include <ao_fake_flight.h>
29 volatile AO_TICK_TYPE ao_tick_count;
38 volatile __data uint8_t ao_data_interval = 1;
39 volatile __data uint8_t ao_data_count;
42 void stm_systick_isr(void)
44 if (stm_systick.csr & (1 << STM_SYSTICK_CSR_COUNTFLAG)) {
47 if (ao_task_alarm_tick && (int16_t) (ao_tick_count - ao_task_alarm_tick) >= 0)
48 ao_task_check_alarm((uint16_t) ao_tick_count);
51 if (++ao_data_count == ao_data_interval) {
55 if (ao_fake_flight_active)
56 ao_fake_flight_poll();
61 #if (AO_DATA_ALL & ~(AO_DATA_ADC))
62 ao_wakeup((void *) &ao_data_count);
74 ao_timer_set_adc_interval(uint8_t interval)
77 ao_data_interval = interval;
83 #define SYSTICK_RELOAD (AO_SYSTICK / 100 - 1)
88 stm_systick.rvr = SYSTICK_RELOAD;
90 stm_systick.csr = ((1 << STM_SYSTICK_CSR_ENABLE) |
91 (1 << STM_SYSTICK_CSR_TICKINT) |
92 (STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 << STM_SYSTICK_CSR_CLKSOURCE));
99 ao_clock_enable_crs(void)
101 /* Enable crs interface clock */
102 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_CRSEN);
104 /* Disable error counter */
105 stm_crs.cr = ((stm_crs.cr & (1 << 4)) |
106 (32 << STM_CRS_CR_TRIM) |
107 (0 << STM_CRS_CR_SWSYNC) |
108 (0 << STM_CRS_CR_AUTOTRIMEN) |
109 (0 << STM_CRS_CR_CEN) |
110 (0 << STM_CRS_CR_ESYNCIE) |
111 (0 << STM_CRS_CR_ERRIE) |
112 (0 << STM_CRS_CR_SYNCWARNIE) |
113 (0 << STM_CRS_CR_SYNCOKIE));
115 /* Configure for USB source */
116 stm_crs.cfgr = ((stm_crs.cfgr & ((1 << 30) | (1 << 27))) |
117 (0 << STM_CRS_CFGR_SYNCPOL) |
118 (STM_CRS_CFGR_SYNCSRC_USB << STM_CRS_CFGR_SYNCSRC) |
119 (STM_CRS_CFGR_SYNCDIV_1 << STM_CRS_CFGR_SYNCDIV) |
120 (0x22 << STM_CRS_CFGR_FELIM) |
121 (((48000000 / 1000) - 1) << STM_CRS_CFGR_RELOAD));
123 /* Enable error counter, set auto trim */
124 stm_crs.cr = ((stm_crs.cr & (1 << 4)) |
125 (32 << STM_CRS_CR_TRIM) |
126 (0 << STM_CRS_CR_SWSYNC) |
127 (1 << STM_CRS_CR_AUTOTRIMEN) |
128 (1 << STM_CRS_CR_CEN) |
129 (0 << STM_CRS_CR_ESYNCIE) |
130 (0 << STM_CRS_CR_ERRIE) |
131 (0 << STM_CRS_CR_SYNCWARNIE) |
132 (0 << STM_CRS_CR_SYNCOKIE));
139 stm_rcc.cr |= (1 << STM_RCC_CR_HSION);
140 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSIRDY)))
143 stm_rcc.cfgr = (stm_rcc.cfgr & ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW)) |
144 (STM_RCC_CFGR_SW_HSI << STM_RCC_CFGR_SW);
146 /* wait for system to switch to HSI */
147 while ((stm_rcc.cfgr & (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS)) !=
148 (STM_RCC_CFGR_SWS_HSI << STM_RCC_CFGR_SWS))
151 /* reset the clock config, leaving us running on the HSI */
152 stm_rcc.cfgr &= (uint32_t)0x0000000f;
154 /* reset PLLON, CSSON, HSEBYP, HSEON */
155 stm_rcc.cr &= 0x0000ffff;
159 ao_clock_normal_start(void)
163 #define STM_RCC_CFGR_SWS_TARGET_CLOCK STM_RCC_CFGR_SWS_PLL
164 #define STM_RCC_CFGR_SW_TARGET_CLOCK STM_RCC_CFGR_SW_PLL
165 #define STM_PLLSRC AO_HSE
166 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK STM_RCC_CFGR_PLLSRC_HSE
169 stm_rcc.cr |= (1 << STM_RCC_CR_HSEBYP);
171 stm_rcc.cr &= ~(1 << STM_RCC_CR_HSEBYP);
173 /* Enable HSE clock */
174 stm_rcc.cr |= (1 << STM_RCC_CR_HSEON);
175 while (!(stm_rcc.cr & (1 << STM_RCC_CR_HSERDY)))
179 /* Disable the PLL */
180 stm_rcc.cr &= ~(1 << STM_RCC_CR_PLLON);
181 while (stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY))
184 /* PLLVCO to 48MHz (for USB) -> PLLMUL = 3 */
186 cfgr &= ~(STM_RCC_CFGR_PLLMUL_MASK << STM_RCC_CFGR_PLLMUL);
187 cfgr |= (AO_RCC_CFGR_PLLMUL << STM_RCC_CFGR_PLLMUL);
190 cfgr &= ~(1 << STM_RCC_CFGR_PLLSRC);
191 cfgr |= (STM_RCC_CFGR_PLLSRC_TARGET_CLOCK << STM_RCC_CFGR_PLLSRC);
194 /* Disable pre divider */
195 stm_rcc.cfgr2 = (STM_RCC_CFGR2_PREDIV_1 << STM_RCC_CFGR2_PREDIV);
197 /* Enable the PLL and wait for it */
198 stm_rcc.cr |= (1 << STM_RCC_CR_PLLON);
199 while (!(stm_rcc.cr & (1 << STM_RCC_CR_PLLRDY)))
208 #define STM_RCC_CFGR_SWS_TARGET_CLOCK STM_RCC_CFGR_SWS_HSI48
209 #define STM_RCC_CFGR_SW_TARGET_CLOCK STM_RCC_CFGR_SW_HSI48
211 /* Turn HSI48 clock on */
212 stm_rcc.cr2 |= (1 << STM_RCC_CR2_HSI48ON);
214 /* Wait for clock to stabilize */
215 while ((stm_rcc.cr2 & (1 << STM_RCC_CR2_HSI48RDY)) == 0)
218 ao_clock_enable_crs();
221 #ifndef STM_RCC_CFGR_SWS_TARGET_CLOCK
222 #define STM_HSI 16000000
223 #define STM_RCC_CFGR_SWS_TARGET_CLOCK STM_RCC_CFGR_SWS_HSI
224 #define STM_RCC_CFGR_SW_TARGET_CLOCK STM_RCC_CFGR_SW_HSI
225 #define STM_PLLSRC STM_HSI
226 #define STM_RCC_CFGR_PLLSRC_TARGET_CLOCK 0
231 ao_clock_normal_switch(void)
236 cfgr &= ~(STM_RCC_CFGR_SW_MASK << STM_RCC_CFGR_SW);
237 cfgr |= (STM_RCC_CFGR_SW_TARGET_CLOCK << STM_RCC_CFGR_SW);
240 uint32_t c, part, mask, val;
243 mask = (STM_RCC_CFGR_SWS_MASK << STM_RCC_CFGR_SWS);
244 val = (STM_RCC_CFGR_SWS_TARGET_CLOCK << STM_RCC_CFGR_SWS);
249 #if !AO_HSI && !AO_NEED_HSI
250 /* Turn off the HSI clock */
251 stm_rcc.cr &= ~(1 << STM_RCC_CR_HSION);
255 stm_rcc.cfgr3 |= (1 << STM_RCC_CFGR3_USBSW);
264 /* Switch to HSI while messing about */
267 /* Disable all interrupts */
270 /* Start high speed clock */
271 ao_clock_normal_start();
273 /* Set flash latency to tolerate 48MHz SYSCLK -> 1 wait state */
275 /* Enable prefetch */
276 stm_flash.acr |= (1 << STM_FLASH_ACR_PRFTBE);
278 /* Enable 1 wait state so the CPU can run at 48MHz */
279 stm_flash.acr |= (STM_FLASH_ACR_LATENCY_1 << STM_FLASH_ACR_LATENCY);
281 /* Enable power interface clock */
282 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
284 /* HCLK to 48MHz -> AHB prescaler = /1 */
286 cfgr &= ~(STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE);
287 cfgr |= (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE);
289 while ((stm_rcc.cfgr & (STM_RCC_CFGR_HPRE_MASK << STM_RCC_CFGR_HPRE)) !=
290 (AO_RCC_CFGR_HPRE_DIV << STM_RCC_CFGR_HPRE))
293 /* APB Prescaler = AO_APB_PRESCALER */
295 cfgr &= ~(STM_RCC_CFGR_PPRE_MASK << STM_RCC_CFGR_PPRE);
296 cfgr |= (AO_RCC_CFGR_PPRE_DIV << STM_RCC_CFGR_PPRE);
299 /* Switch to the desired system clock */
300 ao_clock_normal_switch();
302 /* Clear reset flags */
303 stm_rcc.csr |= (1 << STM_RCC_CSR_RMVF);
306 /* Output SYSCLK on PA8 for measurments */
308 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN);
310 stm_afr_set(&stm_gpioa, 8, STM_AFR_AF0);
311 stm_moder_set(&stm_gpioa, 8, STM_MODER_ALTERNATE);
312 stm_ospeedr_set(&stm_gpioa, 8, STM_OSPEEDR_40MHz);
314 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOPRE_DIV_1 << STM_RCC_CFGR_MCOPRE);
315 stm_rcc.cfgr |= (STM_RCC_CFGR_MCOSEL_HSE << STM_RCC_CFGR_MCOSEL);
319 #if AO_POWER_MANAGEMENT
321 ao_clock_suspend(void)
327 ao_clock_resume(void)
329 ao_clock_normal_start();
330 ao_clock_normal_switch();