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   1 /*
   2  * Copyright © 2016 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #include "ao.h"
  20 #include "ao_pwm.h"
  21
  22 static uint8_t  pwm_running;
  23
  24 static uint16_t pwm_value[NUM_PWM];
  25
  26 static void
  27 ao_pwm_up(void)
  28 {
  29         if (pwm_running++ == 0) {
  30                 struct stm_tim23        *tim = AO_PWM_TIMER;
  31
  32                 tim->ccr1 = 0;
  33                 tim->ccr2 = 0;
  34                 tim->ccr3 = 0;
  35                 tim->ccr4 = 0;
  36                 tim->arr = PWM_MAX - 1; /* turn on the timer */
  37                 tim->cr1 = ((STM_TIM23_CR1_CKD_1 << STM_TIM23_CR1_CKD) |
  38                             (0 << STM_TIM23_CR1_ARPE) |
  39                             (STM_TIM23_CR1_CMS_EDGE << STM_TIM23_CR1_CMS) |
  40                             (STM_TIM23_CR1_DIR_UP << STM_TIM23_CR1_DIR) |
  41                             (0 << STM_TIM23_CR1_OPM) |
  42                             (0 << STM_TIM23_CR1_URS) |
  43                             (0 << STM_TIM23_CR1_UDIS) |
  44                             (1 << STM_TIM23_CR1_CEN));
  45
  46                 /* Set the timer running */
  47                 tim->egr = (1 << STM_TIM23_EGR_UG);
  48         }
  49 }
  50
  51 static void
  52 ao_pwm_down(void)
  53 {
  54         if (--pwm_running == 0) {
  55                 struct stm_tim23        *tim = AO_PWM_TIMER;
  56
  57                 tim->arr = 0;
  58                 tim->cr1 = ((STM_TIM23_CR1_CKD_1 << STM_TIM23_CR1_CKD) |
  59                             (0 << STM_TIM23_CR1_ARPE) |
  60                             (STM_TIM23_CR1_CMS_EDGE << STM_TIM23_CR1_CMS) |
  61                             (STM_TIM23_CR1_DIR_UP << STM_TIM23_CR1_DIR) |
  62                             (0 << STM_TIM23_CR1_OPM) |
  63                             (0 << STM_TIM23_CR1_URS) |
  64                             (0 << STM_TIM23_CR1_UDIS) |
  65                             (0 << STM_TIM23_CR1_CEN));
  66
  67                 /* Stop the timer */
  68                 tim->egr = (1 << STM_TIM23_EGR_UG);
  69         }
  70 }
  71
  72 void
  73 ao_pwm_set(uint8_t pwm, uint16_t value)
  74 {
  75         struct stm_tim23        *tim = AO_PWM_TIMER;
  76         uint8_t                 ch = AO_PWM_0_CH;
  77
  78         if (value > PWM_MAX)
  79                 value = PWM_MAX;
  80         if (value != 0) {
  81                 if (pwm_value[pwm] == 0)
  82                         ao_pwm_up();
  83         }
  84 #if NUM_PWM > 1
  85         switch (pwm) {
  86         case 0:
  87                 ch = AO_PWM_0_CH;
  88                 break;
  89         case 1:
  90                 ch = AO_PWM_0_CH;
  91                 break;
  92 #if NUM_PWM > 2
  93         case 2:
  94                 ch = AO_PWM_0_CH;
  95                 break;
  96 #endif
  97 #if NUM_PWM > 3
  98         case 3:
  99                 ch = AO_PWM_0_CH;
 100                 break;
 101 #endif
 102         }
 103 #endif
 104
 105         switch (ch) {
 106         case 1:
 107                 tim->ccr1 = value;
 108                 break;
 109         case 2:
 110                 tim->ccr2 = value;
 111                 break;
 112         case 3:
 113                 tim->ccr3 = value;
 114                 break;
 115         case 4:
 116                 tim->ccr4 = value;
 117                 break;
 118         }
 119         if (value == 0) {
 120                 if (pwm_value[pwm] != 0)
 121                         ao_pwm_down();
 122         }
 123         pwm_value[pwm] = value;
 124 }
 125
 126 static void
 127 ao_pwm_cmd(void)
 128 {
 129         uint8_t ch;
 130         uint16_t val;
 131
 132         ao_cmd_decimal();
 133         ch = ao_cmd_lex_u32;
 134         ao_cmd_decimal();
 135         val = ao_cmd_lex_u32;
 136         if (ao_cmd_status != ao_cmd_success)
 137                 return;
 138
 139         printf("Set channel %d to %d\n", ch, val);
 140         ao_pwm_set(ch, val);
 141 }
 142
 143 static const struct ao_cmds ao_pwm_cmds[] = {
 144         { ao_pwm_cmd,   "P <ch> <val>\0Set PWM ch to val" },
 145         { 0, NULL },
 146 };
 147
 148 void
 149 ao_pwm_init(void)
 150 {
 151         struct stm_tim23        *tim = AO_PWM_TIMER;
 152
 153         stm_rcc.apb1enr |= (1 << AO_PWM_TIMER_ENABLE);
 154
 155         tim->cr1 = 0;
 156         tim->psc = AO_PWM_TIMER_SCALE - 1;
 157         tim->cnt = 0;
 158         tim->ccer = ((1 << STM_TIM23_CCER_CC1E) |
 159                      (0 << STM_TIM23_CCER_CC1P) |
 160                      (1 << STM_TIM23_CCER_CC2E) |
 161                      (0 << STM_TIM23_CCER_CC2P) |
 162                      (1 << STM_TIM23_CCER_CC3E) |
 163                      (0 << STM_TIM23_CCER_CC3P) |
 164                      (1 << STM_TIM23_CCER_CC4E) |
 165                      (0 << STM_TIM23_CCER_CC4P));
 166
 167         tim->ccmr1 = ((0 << STM_TIM23_CCMR1_OC2CE) |
 168                       (STM_TIM23_CCMR1_OC2M_PWM_MODE_1 << STM_TIM23_CCMR1_OC2M) |
 169                       (0 << STM_TIM23_CCMR1_OC2PE) |
 170                       (0 << STM_TIM23_CCMR1_OC2FE) |
 171                       (STM_TIM23_CCMR1_CC2S_OUTPUT << STM_TIM23_CCMR1_CC2S) |
 172
 173                       (0 << STM_TIM23_CCMR1_OC1CE) |
 174                       (STM_TIM23_CCMR1_OC1M_PWM_MODE_1 << STM_TIM23_CCMR1_OC1M) |
 175                       (0 << STM_TIM23_CCMR1_OC1PE) |
 176                       (0 << STM_TIM23_CCMR1_OC1FE) |
 177                       (STM_TIM23_CCMR1_CC1S_OUTPUT << STM_TIM23_CCMR1_CC1S));
 178
 179
 180         tim->ccmr2 = ((0 << STM_TIM23_CCMR2_OC4CE) |
 181                       (STM_TIM23_CCMR2_OC4M_PWM_MODE_1 << STM_TIM23_CCMR2_OC4M) |
 182                       (0 << STM_TIM23_CCMR2_OC4PE) |
 183                       (0 << STM_TIM23_CCMR2_OC4FE) |
 184                       (STM_TIM23_CCMR2_CC4S_OUTPUT << STM_TIM23_CCMR2_CC4S) |
 185
 186                       (0 << STM_TIM23_CCMR2_OC3CE) |
 187                       (STM_TIM23_CCMR2_OC3M_PWM_MODE_1 << STM_TIM23_CCMR2_OC3M) |
 188                       (0 << STM_TIM23_CCMR2_OC3PE) |
 189                       (0 << STM_TIM23_CCMR2_OC3FE) |
 190                       (STM_TIM23_CCMR2_CC3S_OUTPUT << STM_TIM23_CCMR2_CC3S));
 191         tim->egr = 0;
 192
 193         tim->sr = 0;
 194         tim->dier = 0;
 195         tim->smcr = 0;
 196         tim->cr2 = ((0 << STM_TIM23_CR2_TI1S) |
 197                     (STM_TIM23_CR2_MMS_RESET<< STM_TIM23_CR2_MMS) |
 198                     (0 << STM_TIM23_CR2_CCDS));
 199
 200         stm_afr_set(AO_PWM_0_GPIO, AO_PWM_0_PIN, STM_AFR_AF1);
 201         stm_ospeedr_set(AO_PWM_0_GPIO, AO_PWM_0_PIN, STM_OSPEEDR_MEDIUM);
 202 #if NUM_PWM > 1
 203         stm_afr_set(AO_PWM_1_GPIO, AO_PWM_1_PIN, STM_AFR_AF1);
 204         stm_ospeedr_set(AO_PWM_1_GPIO, AO_PWM_1_PIN, STM_OSPEEDR_MEDIUM);
 205 #endif
 206 #if NUM_PWM > 2
 207         stm_afr_set(AO_PWM_2_GPIO, AO_PWM_2_PIN, STM_AFR_AF1);
 208         stm_ospeedr_set(AO_PWM_2_GPIO, AO_PWM_2_PIN, STM_OSPEEDR_MEDIUM);
 209 #endif
 210 #if NUM_PWM > 3
 211         stm_afr_set(AO_PWM_3_GPIO, AO_PWM_3_PIN, STM_AFR_AF1);
 212         stm_ospeedr_set(AO_PWM_3_GPIO, AO_PWM_3_PIN, STM_OSPEEDR_MEDIUM);
 213 #endif
 214         ao_cmd_register(&ao_pwm_cmds[0]);
 215 }