2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 struct ao_dma_config {
21 void (*isr)(int index);
24 uint8_t ao_dma_done[STM_NUM_DMA];
26 static struct ao_dma_config ao_dma_config[STM_NUM_DMA];
27 static uint8_t ao_dma_allocated[STM_NUM_DMA];
28 static uint8_t ao_dma_mutex[STM_NUM_DMA];
29 static uint8_t ao_dma_active;
31 #define id(ch) STM_DMA_INDEX(ch)
32 #define id_mask(id) (STM_DMA_ISR_MASK << (id))
33 #define ch_mask(ch) id_mask(id(ch))
36 ao_dma_isr(uint8_t low_index, uint8_t high_index, uint32_t mask) {
37 /* Get channel interrupt bits */
38 uint32_t isr = stm_dma.isr & mask;
43 for (index = low_index; index <= high_index; index++) {
44 if (isr & id_mask(index)) {
45 if (ao_dma_config[index].isr)
46 (*ao_dma_config[index].isr)(index);
48 ao_dma_done[index] = 1;
49 ao_wakeup(&ao_dma_done[index]);
55 void stm_dma_ch1_isr(void) { ao_dma_isr(id(1), id(1), ch_mask(1)); }
56 void stm_dma_ch2_3_isr(void) { ao_dma_isr(id(2), id(3), ch_mask(2) | ch_mask(3)); }
57 void stm_dma1_ch4_5_6_isr(void) { ao_dma_isr(id(4), id(6), ch_mask(4) | ch_mask(5) | ch_mask(6)); }
60 ao_dma_set_transfer(uint8_t index,
61 volatile void *peripheral,
66 if (ao_dma_allocated[index]) {
67 if (ao_dma_mutex[index])
68 ao_panic(AO_PANIC_DMA);
69 ao_dma_mutex[index] = 1;
71 ao_mutex_get(&ao_dma_mutex[index]);
73 if (ao_dma_active++ == 0)
74 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_DMAEN);
76 stm_dma.channel[index].ccr = ccr | (1 << STM_DMA_CCR_TCIE);
77 stm_dma.channel[index].cndtr = count;
78 stm_dma.channel[index].cpar = peripheral;
79 stm_dma.channel[index].cmar = memory;
80 ao_dma_config[index].isr = NULL;
84 ao_dma_set_isr(uint8_t index, void (*isr)(int))
86 ao_dma_config[index].isr = isr;
90 ao_dma_start(uint8_t index)
92 ao_dma_done[index] = 0;
93 stm_dma.channel[index].ccr |= (1 << STM_DMA_CCR_EN);
97 ao_dma_done_transfer(uint8_t index)
99 stm_dma.channel[index].ccr &= ~(1 << STM_DMA_CCR_EN);
101 if (--ao_dma_active == 0)
102 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_DMAEN);
104 if (ao_dma_allocated[index])
105 ao_dma_mutex[index] = 0;
107 ao_mutex_put(&ao_dma_mutex[index]);
111 ao_dma_abort(uint8_t index)
113 stm_dma.channel[index].ccr &= ~(1 << STM_DMA_CCR_EN);
114 ao_wakeup(&ao_dma_done[index]);
118 ao_dma_alloc(uint8_t index)
120 if (ao_dma_allocated[index])
121 ao_panic(AO_PANIC_DMA);
122 ao_dma_allocated[index] = 1;
125 #define STM_NUM_DMA_ISR 3
133 for (isr_id = 0; isr_id < STM_NUM_DMA_ISR; isr_id++) {
134 stm_nvic_set_enable(STM_ISR_DMA_CH1_POS + isr_id);
135 stm_nvic_set_priority(STM_ISR_DMA_CH1_POS + isr_id, 4);
137 for (index = 0; index < STM_NUM_DMA; index++) {
138 ao_dma_allocated[index] = 0;
139 ao_dma_mutex[index] = 0;