2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 #ifndef BEEPER_CHANNEL
21 #error BEEPER_CHANNEL undefined
25 #define BEEPER_TIMER 1
29 #define timer stm_tim1
30 #define STM_RCC_TIMER STM_RCC_APB2ENR_TIM1EN
31 #define stm_rcc_enr stm_rcc.apb2enr
35 #define timer stm_tim2
36 #define STM_RCC_TIMER STM_RCC_APB1ENR_TIM2EN
37 #define stm_rcc_enr stm_rcc.apb1enr
41 #define timer stm_tim3
42 #define STM_RCC_TIMER STM_RCC_APB1ENR_TIM3EN
43 #define stm_rcc_enr stm_rcc.apb1enr
47 #error BEEPER_TIMER invalid
57 stm_rcc_enr &= ~(1 << STM_RCC_TIMER);
66 stm_rcc_enr |= (1 << STM_RCC_TIMER);
69 /* Master output enable */
70 stm_tim1.bdtr = (1 << STM_TIM1_BDTR_MOE);
72 stm_tim1.cr2 = ((0 << STM_TIM1_CR2_TI1S) |
73 (STM_TIM1_CR2_MMS_RESET << STM_TIM1_CR2_MMS) |
74 (0 << STM_TIM1_CR2_CCDS));
76 /* Set prescaler to match cc1111 clocks
78 stm_tim1.psc = AO_TIM_CLK / 750000;
80 /* 1. Select the counter clock (internal, external, prescaler).
82 * Setting SMCR to zero means use the internal clock
87 /* 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. */
91 /* 3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a
92 * DMA request is to be generated.
96 /* 4. Select the output mode. For example, you must write
97 * OCxM=011, OCxPE=0, CCxP=0 and CCxE=1 to toggle OCx output
98 * pin when CNT matches CCRx, CCRx preload is not used, OCx
99 * is enabled and active high.
102 #if BEEPER_CHANNEL == 1
103 stm_tim1.ccmr1 = ((0 << STM_TIM1_CCMR1_OC2CE) |
104 (STM_TIM1_CCMR_OCM_FROZEN << STM_TIM1_CCMR1_OC2M) |
105 (0 << STM_TIM1_CCMR1_OC2PE) |
106 (0 << STM_TIM1_CCMR1_OC2FE) |
107 (STM_TIM1_CCMR_CCS_OUTPUT << STM_TIM1_CCMR1_CC2S) |
109 (0 << STM_TIM1_CCMR1_OC1CE) |
110 (STM_TIM1_CCMR_OCM_TOGGLE << STM_TIM1_CCMR1_OC1M) |
111 (0 << STM_TIM1_CCMR1_OC1PE) |
112 (0 << STM_TIM1_CCMR1_OC1FE) |
113 (STM_TIM1_CCMR_CCS_OUTPUT << STM_TIM1_CCMR1_CC1S));
115 stm_tim1.ccer = ((0 << STM_TIM1_CCER_CC4P) |
116 (0 << STM_TIM1_CCER_CC4E) |
117 (0 << STM_TIM1_CCER_CC3NP) |
118 (0 << STM_TIM1_CCER_CC3NE) |
119 (0 << STM_TIM1_CCER_CC3P) |
120 (0 << STM_TIM1_CCER_CC3E) |
121 (0 << STM_TIM1_CCER_CC2NP) |
122 (0 << STM_TIM1_CCER_CC2NE) |
123 (0 << STM_TIM1_CCER_CC2P) |
124 (0 << STM_TIM1_CCER_CC2E) |
125 (0 << STM_TIM1_CCER_CC1NE) |
126 (0 << STM_TIM1_CCER_CC1P) |
127 (1 << STM_TIM1_CCER_CC1E));
129 #if BEEPER_CHANNEL == 2
130 stm_tim1.ccmr1 = ((0 << STM_TIM1_CCMR1_OC2CE) |
131 (STM_TIM1_CCMR_OCM_TOGGLE << STM_TIM1_CCMR1_OC2M) |
132 (0 << STM_TIM1_CCMR1_OC2PE) |
133 (0 << STM_TIM1_CCMR1_OC2FE) |
134 (STM_TIM1_CCMR_CCS_OUTPUT << STM_TIM1_CCMR1_CC2S) |
136 (0 << STM_TIM1_CCMR1_OC1CE) |
137 (STM_TIM1_CCMR_OCM_FROZEN << STM_TIM1_CCMR1_OC1M) |
138 (0 << STM_TIM1_CCMR1_OC1PE) |
139 (0 << STM_TIM1_CCMR1_OC1FE) |
140 (STM_TIM1_CCMR_CCS_OUTPUT << STM_TIM1_CCMR1_CC1S));
142 stm_tim1.ccer = ((0 << STM_TIM1_CCER_CC4P) |
143 (0 << STM_TIM1_CCER_CC4E) |
144 (0 << STM_TIM1_CCER_CC3NP) |
145 (0 << STM_TIM1_CCER_CC3NE) |
146 (0 << STM_TIM1_CCER_CC3P) |
147 (0 << STM_TIM1_CCER_CC3E) |
148 (0 << STM_TIM1_CCER_CC2NP) |
149 (0 << STM_TIM1_CCER_CC2NE) |
150 (0 << STM_TIM1_CCER_CC2P) |
151 (1 << STM_TIM1_CCER_CC2E) |
152 (0 << STM_TIM1_CCER_CC1NE) |
153 (0 << STM_TIM1_CCER_CC1P) |
154 (0 << STM_TIM1_CCER_CC1E));
156 #if BEEPER_CHANNEL == 3
157 stm_tim1.ccmr2 = ((0 << STM_TIM1_CCMR2_OC4CE) |
158 (STM_TIM1_CCMR_OCM_FROZEN << STM_TIM1_CCMR2_OC4M) |
159 (0 << STM_TIM1_CCMR2_OC4PE) |
160 (0 << STM_TIM1_CCMR2_OC4FE) |
161 (STM_TIM1_CCMR_CCS_OUTPUT << STM_TIM1_CCMR2_CC4S) |
163 (0 << STM_TIM1_CCMR2_OC3CE) |
164 (STM_TIM1_CCMR_OCM_TOGGLE << STM_TIM1_CCMR2_OC3M) |
165 (0 << STM_TIM1_CCMR2_OC3PE) |
166 (0 << STM_TIM1_CCMR2_OC3FE) |
167 (STM_TIM1_CCMR_CCS_OUTPUT << STM_TIM1_CCMR2_CC3S));
169 stm_tim1.ccer = ((0 << STM_TIM1_CCER_CC4P) |
170 (0 << STM_TIM1_CCER_CC4E) |
171 (0 << STM_TIM1_CCER_CC3NP) |
172 (0 << STM_TIM1_CCER_CC3NE) |
173 (0 << STM_TIM1_CCER_CC3P) |
174 (1 << STM_TIM1_CCER_CC3E) |
175 (0 << STM_TIM1_CCER_CC2NP) |
176 (0 << STM_TIM1_CCER_CC2NE) |
177 (0 << STM_TIM1_CCER_CC2P) |
178 (0 << STM_TIM1_CCER_CC2E) |
179 (0 << STM_TIM1_CCER_CC1NE) |
180 (0 << STM_TIM1_CCER_CC1P) |
181 (0 << STM_TIM1_CCER_CC1E));
183 #if BEEPER_CHANNEL == 4
184 stm_tim1.ccmr2 = ((0 << STM_TIM1_CCMR2_OC4CE) |
185 (STM_TIM1_CCMR2_OC4M_TOGGLE << STM_TIM1_CCMR2_OC4M) |
186 (0 << STM_TIM1_CCMR2_OC4PE) |
187 (0 << STM_TIM1_CCMR2_OC4FE) |
188 (STM_TIM1_CCMR2_CC4S_OUTPUT << STM_TIM1_CCMR2_CC4S) |
190 (0 << STM_TIM1_CCMR2_OC3CE) |
191 (STM_TIM1_CCMR2_OC3M_FROZEN << STM_TIM1_CCMR2_OC3M) |
192 (0 << STM_TIM1_CCMR2_OC3PE) |
193 (0 << STM_TIM1_CCMR2_OC3FE) |
194 (STM_TIM1_CCMR2_CC3S_OUTPUT << STM_TIM1_CCMR2_CC3S));
196 stm_tim1.ccer = ((0 << STM_TIM1_CCER_CC4NP) |
197 (0 << STM_TIM1_CCER_CC4P) |
198 (1 << STM_TIM1_CCER_CC4E) |
199 (0 << STM_TIM1_CCER_CC3NP) |
200 (0 << STM_TIM1_CCER_CC3P) |
201 (0 << STM_TIM1_CCER_CC3E) |
202 (0 << STM_TIM1_CCER_CC2NP) |
203 (0 << STM_TIM1_CCER_CC2P) |
204 (0 << STM_TIM1_CCER_CC2E) |
205 (0 << STM_TIM1_CCER_CC1NP) |
206 (0 << STM_TIM1_CCER_CC1P) |
207 (0 << STM_TIM1_CCER_CC1E));
209 /* 5. Enable the counter by setting the CEN bit in the TIMx_CR1 register. */
211 stm_tim1.cr1 = ((STM_TIM1_CR1_CKD_1 << STM_TIM1_CR1_CKD) |
212 (0 << STM_TIM1_CR1_ARPE) |
213 (STM_TIM1_CR1_CMS_EDGE << STM_TIM1_CR1_CMS) |
214 (0 << STM_TIM1_CR1_DIR) |
215 (0 << STM_TIM1_CR1_OPM) |
216 (0 << STM_TIM1_CR1_URS) |
217 (0 << STM_TIM1_CR1_UDIS) |
218 (1 << STM_TIM1_CR1_CEN));
220 /* Update the values */
221 stm_tim1.egr = (1 << STM_TIM1_EGR_UG);
223 #if BEEPER_TIMER == 2 || BEEPER_TIMER == 3
225 timer.cr2 = ((0 << STM_TIM23_CR2_TI1S) |
226 (STM_TIM23_CR2_MMS_RESET << STM_TIM23_CR2_MMS) |
227 (0 << STM_TIM23_CR2_CCDS));
229 /* Set prescaler to match cc1111 clocks
231 timer.psc = AO_TIM_CLK / 750000;
233 /* 1. Select the counter clock (internal, external, prescaler).
235 * Setting SMCR to zero means use the internal clock
240 /* 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. */
244 /* 3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a
245 * DMA request is to be generated.
247 /* don't want this */
249 /* 4. Select the output mode. For example, you must write
250 * OCxM=011, OCxPE=0, CCxP=0 and CCxE=1 to toggle OCx output
251 * pin when CNT matches CCRx, CCRx preload is not used, OCx
252 * is enabled and active high.
255 #if BEEPER_CHANNEL == 1
256 timer.ccmr1 = ((0 << STM_TIM23_CCMR1_OC2CE) |
257 (STM_TIM23_CCMR1_OC2M_FROZEN << STM_TIM23_CCMR1_OC2M) |
258 (0 << STM_TIM23_CCMR1_OC2PE) |
259 (0 << STM_TIM23_CCMR1_OC2FE) |
260 (STM_TIM23_CCMR1_CC2S_OUTPUT << STM_TIM23_CCMR1_CC2S) |
262 (0 << STM_TIM23_CCMR1_OC1CE) |
263 (STM_TIM23_CCMR1_OC1M_TOGGLE << STM_TIM23_CCMR1_OC1M) |
264 (0 << STM_TIM23_CCMR1_OC1PE) |
265 (0 << STM_TIM23_CCMR1_OC1FE) |
266 (STM_TIM23_CCMR1_CC1S_OUTPUT << STM_TIM23_CCMR1_CC1S));
268 timer.ccer = ((0 << STM_TIM23_CCER_CC4P) |
269 (0 << STM_TIM23_CCER_CC4E) |
270 (0 << STM_TIM23_CCER_CC3NP) |
271 (0 << STM_TIM23_CCER_CC3P) |
272 (0 << STM_TIM23_CCER_CC3E) |
273 (0 << STM_TIM23_CCER_CC2NP) |
274 (0 << STM_TIM23_CCER_CC2P) |
275 (0 << STM_TIM23_CCER_CC2E) |
276 (0 << STM_TIM23_CCER_CC1P) |
277 (1 << STM_TIM23_CCER_CC1E));
279 #if BEEPER_CHANNEL == 2
280 timer.ccmr1 = ((0 << STM_TIM23_CCMR1_OC2CE) |
281 (STM_TIM23_CCMR1_OC2M_TOGGLE << STM_TIM23_CCMR1_OC2M) |
282 (0 << STM_TIM23_CCMR1_OC2PE) |
283 (0 << STM_TIM23_CCMR1_OC2FE) |
284 (STM_TIM23_CCMR1_CC2S_OUTPUT << STM_TIM23_CCMR1_CC2S) |
286 (0 << STM_TIM23_CCMR1_OC1CE) |
287 (STM_TIM23_CCMR1_OC1M_FROZEN << STM_TIM23_CCMR1_OC1M) |
288 (0 << STM_TIM23_CCMR1_OC1PE) |
289 (0 << STM_TIM23_CCMR1_OC1FE) |
290 (STM_TIM23_CCMR1_CC1S_OUTPUT << STM_TIM23_CCMR1_CC1S));
292 timer.ccer = ((0 << STM_TIM23_CCER_CC4P) |
293 (0 << STM_TIM23_CCER_CC4E) |
294 (0 << STM_TIM23_CCER_CC3NP) |
295 (0 << STM_TIM23_CCER_CC3P) |
296 (0 << STM_TIM23_CCER_CC3E) |
297 (0 << STM_TIM23_CCER_CC2NP) |
298 (0 << STM_TIM23_CCER_CC2P) |
299 (1 << STM_TIM23_CCER_CC2E) |
300 (0 << STM_TIM23_CCER_CC1P) |
301 (0 << STM_TIM23_CCER_CC1E));
303 #if BEEPER_CHANNEL == 3
304 timer.ccmr2 = ((0 << STM_TIM23_CCMR2_OC4CE) |
305 (STM_TIM23_CCMR2_OC4M_FROZEN << STM_TIM23_CCMR2_OC4M) |
306 (0 << STM_TIM23_CCMR2_OC4PE) |
307 (0 << STM_TIM23_CCMR2_OC4FE) |
308 (STM_TIM23_CCMR2_CC4S_OUTPUT << STM_TIM23_CCMR2_CC4S) |
310 (0 << STM_TIM23_CCMR2_OC3CE) |
311 (STM_TIM23_CCMR2_OC3M_TOGGLE << STM_TIM23_CCMR2_OC3M) |
312 (0 << STM_TIM23_CCMR2_OC3PE) |
313 (0 << STM_TIM23_CCMR2_OC3FE) |
314 (STM_TIM23_CCMR2_CC3S_OUTPUT << STM_TIM23_CCMR2_CC3S));
316 timer.ccer = ((0 << STM_TIM23_CCER_CC4P) |
317 (0 << STM_TIM23_CCER_CC4E) |
318 (0 << STM_TIM23_CCER_CC3NP) |
319 (0 << STM_TIM23_CCER_CC3P) |
320 (1 << STM_TIM23_CCER_CC3E) |
321 (0 << STM_TIM23_CCER_CC2NP) |
322 (0 << STM_TIM23_CCER_CC2P) |
323 (0 << STM_TIM23_CCER_CC2E) |
324 (0 << STM_TIM23_CCER_CC1P) |
325 (0 << STM_TIM23_CCER_CC1E));
327 #if BEEPER_CHANNEL == 4
328 timer.ccmr2 = ((0 << STM_TIM23_CCMR2_OC4CE) |
329 (STM_TIM23_CCMR2_OC4M_TOGGLE << STM_TIM23_CCMR2_OC4M) |
330 (0 << STM_TIM23_CCMR2_OC4PE) |
331 (0 << STM_TIM23_CCMR2_OC4FE) |
332 (STM_TIM23_CCMR2_CC4S_OUTPUT << STM_TIM23_CCMR2_CC4S) |
334 (0 << STM_TIM23_CCMR2_OC3CE) |
335 (STM_TIM23_CCMR2_OC3M_FROZEN << STM_TIM23_CCMR2_OC3M) |
336 (0 << STM_TIM23_CCMR2_OC3PE) |
337 (0 << STM_TIM23_CCMR2_OC3FE) |
338 (STM_TIM23_CCMR2_CC3S_OUTPUT << STM_TIM23_CCMR2_CC3S));
340 timer.ccer = ((0 << STM_TIM23_CCER_CC4P) |
341 (1 << STM_TIM23_CCER_CC4E) |
342 (0 << STM_TIM23_CCER_CC3NP) |
343 (0 << STM_TIM23_CCER_CC3P) |
344 (0 << STM_TIM23_CCER_CC3E) |
345 (0 << STM_TIM23_CCER_CC2NP) |
346 (0 << STM_TIM23_CCER_CC2P) |
347 (0 << STM_TIM23_CCER_CC2E) |
348 (0 << STM_TIM23_CCER_CC1P) |
349 (0 << STM_TIM23_CCER_CC1E));
351 /* 5. Enable the counter by setting the CEN bit in the TIMx_CR1 register. */
353 timer.cr1 = ((STM_TIM23_CR1_CKD_1 << STM_TIM23_CR1_CKD) |
354 (0 << STM_TIM23_CR1_ARPE) |
355 (STM_TIM23_CR1_CMS_EDGE << STM_TIM23_CR1_CMS) |
356 (0 << STM_TIM23_CR1_DIR) |
357 (0 << STM_TIM23_CR1_OPM) |
358 (0 << STM_TIM23_CR1_URS) |
359 (0 << STM_TIM23_CR1_UDIS) |
360 (1 << STM_TIM23_CR1_CEN));
362 /* Update the values */
363 timer.egr = (1 << STM_TIM23_EGR_UG);
369 ao_beep_for(uint8_t beep, uint16_t ticks) __reentrant
379 ao_enable_port(BEEPER_PORT);
380 stm_afr_set(BEEPER_PORT, BEEPER_PIN, STM_AFR_AF2);
382 /* Leave the timer off until requested */
383 stm_rcc_enr &= ~(1 << STM_RCC_TIMER);