2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #ifndef _AO_ARCH_FUNCS_H_
20 #define _AO_ARCH_FUNCS_H_
27 /* PCLK is set to 48MHz (HCLK 48MHz, HPRE 1, PPRE 1) */
29 #define _AO_SPI_SPEED_24MHz STM_SPI_CR1_BR_PCLK_2
30 #define _AO_SPI_SPEED_12MHz STM_SPI_CR1_BR_PCLK_4
31 #define _AO_SPI_SPEED_6MHz STM_SPI_CR1_BR_PCLK_8
32 #define _AO_SPI_SPEED_3MHz STM_SPI_CR1_BR_PCLK_16
33 #define _AO_SPI_SPEED_1500kHz STM_SPI_CR1_BR_PCLK_32
34 #define _AO_SPI_SPEED_750kHz STM_SPI_CR1_BR_PCLK_64
35 #define _AO_SPI_SPEED_375kHz STM_SPI_CR1_BR_PCLK_128
36 #define _AO_SPI_SPEED_187500Hz STM_SPI_CR1_BR_PCLK_256
38 static inline uint32_t
39 ao_spi_speed(uint32_t hz)
41 if (hz >=24000000) return _AO_SPI_SPEED_24MHz;
42 if (hz >=12000000) return _AO_SPI_SPEED_12MHz;
43 if (hz >= 6000000) return _AO_SPI_SPEED_6MHz;
44 if (hz >= 3000000) return _AO_SPI_SPEED_3MHz;
45 if (hz >= 1500000) return _AO_SPI_SPEED_1500kHz;
46 if (hz >= 750000) return _AO_SPI_SPEED_750kHz;
47 if (hz >= 375000) return _AO_SPI_SPEED_375kHz;
48 return _AO_SPI_SPEED_187500Hz;
51 #define AO_SPI_CONFIG_1 0x00
52 #define AO_SPI_1_CONFIG_PA5_PA6_PA7 AO_SPI_CONFIG_1
53 #define AO_SPI_2_CONFIG_PB13_PB14_PB15 AO_SPI_CONFIG_1
55 #define AO_SPI_CONFIG_2 0x04
56 #define AO_SPI_1_CONFIG_PB3_PB4_PB5 AO_SPI_CONFIG_2
57 #define AO_SPI_2_CONFIG_PD1_PD3_PD4 AO_SPI_CONFIG_2
59 #define AO_SPI_CONFIG_3 0x08
60 #define AO_SPI_1_CONFIG_PE13_PE14_PE15 AO_SPI_CONFIG_3
62 #define AO_SPI_CONFIG_NONE 0x0c
64 #define AO_SPI_INDEX_MASK 0x01
65 #define AO_SPI_CONFIG_MASK 0x0c
67 #define AO_SPI_1_PA5_PA6_PA7 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA5_PA6_PA7)
68 #define AO_SPI_1_PB3_PB4_PB5 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PB3_PB4_PB5)
69 #define AO_SPI_1_PE13_PE14_PE15 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PE13_PE14_PE15)
71 #define AO_SPI_2_PB13_PB14_PB15 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PB13_PB14_PB15)
72 #define AO_SPI_2_PD1_PD3_PD4 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PD1_PD3_PD4)
74 #define AO_SPI_INDEX(id) ((id) & AO_SPI_INDEX_MASK)
75 #define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
77 #define AO_SPI_CPOL_BIT 4
78 #define AO_SPI_CPHA_BIT 5
79 #define AO_SPI_CPOL(id) ((uint32_t) (((id) >> AO_SPI_CPOL_BIT) & 1))
80 #define AO_SPI_CPHA(id) ((uint32_t) (((id) >> AO_SPI_CPHA_BIT) & 1))
82 #define AO_SPI_MAKE_MODE(pol,pha) (((pol) << AO_SPI_CPOL_BIT) | ((pha) << AO_SPI_CPHA_BIT))
83 #define AO_SPI_MODE_0 AO_SPI_MAKE_MODE(0,0)
84 #define AO_SPI_MODE_1 AO_SPI_MAKE_MODE(0,1)
85 #define AO_SPI_MODE_2 AO_SPI_MAKE_MODE(1,0)
86 #define AO_SPI_MODE_3 AO_SPI_MAKE_MODE(1,1)
89 ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id);
92 ao_spi_get(uint8_t spi_index, uint32_t speed);
95 ao_spi_put(uint8_t spi_index);
98 ao_spi_send(const void *block, uint16_t len, uint8_t spi_index);
101 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
104 ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index);
107 ao_spi_start_bytes(uint8_t spi_index);
110 ao_spi_stop_bytes(uint8_t spi_index);
113 ao_spi_send_byte(uint8_t byte, uint8_t spi_index)
115 struct stm_spi *stm_spi;
117 switch (AO_SPI_INDEX(spi_index)) {
126 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
129 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
134 static inline uint8_t
135 ao_spi_recv_byte(uint8_t spi_index)
137 struct stm_spi *stm_spi;
139 switch (AO_SPI_INDEX(spi_index)) {
148 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
151 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
157 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
160 ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index);
165 #define ao_spi_set_cs(reg,mask) ((reg)->bsrr = ((uint32_t) (mask)) << 16)
166 #define ao_spi_clr_cs(reg,mask) ((reg)->bsrr = (mask))
168 #define ao_spi_get_mask(reg,mask,bus, speed) do { \
169 ao_spi_get(bus, speed); \
170 ao_spi_set_cs(reg,mask); \
173 static inline uint8_t
174 ao_spi_try_get_mask(struct stm_gpio *reg, uint16_t mask, uint8_t bus, uint32_t speed, uint8_t task_id)
176 if (!ao_spi_try_get(bus, speed, task_id))
178 ao_spi_set_cs(reg, mask);
182 #define ao_spi_put_mask(reg,mask,bus) do { \
183 ao_spi_clr_cs(reg,mask); \
187 #define ao_spi_get_bit(reg,bit,bus,speed) ao_spi_get_mask(reg,(1<<bit),bus,speed)
188 #define ao_spi_put_bit(reg,bit,bus) ao_spi_put_mask(reg,(1<<bit),bus)
190 #if AO_POWER_MANAGEMENT
191 extern struct ao_power ao_power_gpioa;
192 extern struct ao_power ao_power_gpiob;
193 extern struct ao_power ao_power_gpioc;
194 extern struct ao_power ao_power_gpiof;
197 static inline void ao_enable_port(struct stm_gpio *port)
199 if ((port) == &stm_gpioa) {
200 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPAEN);
201 ao_power_register(&ao_power_gpioa);
202 } else if ((port) == &stm_gpiob) {
203 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPBEN);
204 ao_power_register(&ao_power_gpiob);
205 } else if ((port) == &stm_gpioc) {
206 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPCEN);
207 ao_power_register(&ao_power_gpioc);
208 } else if ((port) == &stm_gpiof) {
209 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_IOPFEN);
210 ao_power_register(&ao_power_gpiof);
214 static inline void ao_disable_port(struct stm_gpio *port)
216 if ((port) == &stm_gpioa) {
217 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPAEN);
218 ao_power_unregister(&ao_power_gpioa);
219 } else if ((port) == &stm_gpiob) {
220 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPBEN);
221 ao_power_unregister(&ao_power_gpiob);
222 } else if ((port) == &stm_gpioc) {
223 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPCEN);
224 ao_power_unregister(&ao_power_gpioc);
225 } else if ((port) == &stm_gpiof) {
226 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_IOPFEN);
227 ao_power_unregister(&ao_power_gpiof);
231 #define ao_gpio_set(port, bit, v) stm_gpio_set(port, bit, v)
233 #define ao_gpio_get(port, bit) stm_gpio_get(port, bit)
235 #define ao_enable_output(port,bit,v) do { \
236 ao_enable_port(port); \
237 ao_gpio_set(port, bit, v); \
238 stm_moder_set(port, bit, STM_MODER_OUTPUT);\
241 #define ao_gpio_set_mode(port,bit,mode) do { \
242 if (mode == AO_EXTI_MODE_PULL_UP) \
243 stm_pupdr_set(port, bit, STM_PUPDR_PULL_UP); \
244 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
245 stm_pupdr_set(port, bit, STM_PUPDR_PULL_DOWN); \
247 stm_pupdr_set(port, bit, STM_PUPDR_NONE); \
250 #define ao_enable_input(port,bit,mode) do { \
251 ao_enable_port(port); \
252 stm_moder_set(port, bit, STM_MODER_INPUT); \
253 ao_gpio_set_mode(port, bit, mode); \
256 #define ao_enable_cs(port,bit) do { \
257 ao_enable_output(port, bit, 1); \
260 #define ao_spi_init_cs(port, mask) do { \
261 ao_enable_port(port); \
262 if ((mask) & 0x0001) ao_enable_cs(port, 0); \
263 if ((mask) & 0x0002) ao_enable_cs(port, 1); \
264 if ((mask) & 0x0004) ao_enable_cs(port, 2); \
265 if ((mask) & 0x0008) ao_enable_cs(port, 3); \
266 if ((mask) & 0x0010) ao_enable_cs(port, 4); \
267 if ((mask) & 0x0020) ao_enable_cs(port, 5); \
268 if ((mask) & 0x0040) ao_enable_cs(port, 6); \
269 if ((mask) & 0x0080) ao_enable_cs(port, 7); \
270 if ((mask) & 0x0100) ao_enable_cs(port, 8); \
271 if ((mask) & 0x0200) ao_enable_cs(port, 9); \
272 if ((mask) & 0x0400) ao_enable_cs(port, 10);\
273 if ((mask) & 0x0800) ao_enable_cs(port, 11);\
274 if ((mask) & 0x1000) ao_enable_cs(port, 12);\
275 if ((mask) & 0x2000) ao_enable_cs(port, 13);\
276 if ((mask) & 0x4000) ao_enable_cs(port, 14);\
277 if ((mask) & 0x8000) ao_enable_cs(port, 15);\
283 extern uint8_t ao_dma_done[STM_NUM_DMA];
286 ao_dma_set_transfer(uint8_t index,
287 volatile void *peripheral,
293 ao_dma_set_isr(uint8_t index, void (*isr)(int index));
296 ao_dma_start(uint8_t index);
299 ao_dma_done_transfer(uint8_t index);
302 ao_dma_abort(uint8_t index);
305 ao_dma_alloc(uint8_t index);
313 ao_i2c_get(uint8_t i2c_index);
316 ao_i2c_start(uint8_t i2c_index, uint16_t address);
319 ao_i2c_put(uint8_t i2c_index);
322 ao_i2c_send(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
325 ao_i2c_recv(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
330 /* ao_serial_stm.c */
332 #if USE_SERIAL_1_FLOW && USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_FLOW && USE_SERIAL_2_SW_FLOW
333 #define HAS_SERIAL_SW_FLOW 1
335 #define HAS_SERIAL_SW_FLOW 0
338 #if USE_SERIAL_2_FLOW && !USE_SERIAL_2_SW_FLOW
339 #define USE_SERIAL_2_HW_FLOW 1
342 #if USE_SERIAL_1_FLOW && !USE_SERIAL_1_SW_FLOW
343 #define USE_SERIAL_1_HW_FLOW 1
346 #if USE_SERIAL_1_HW_FLOW || USE_SERIAL_2_HW_FLOW
347 #define HAS_SERIAL_HW_FLOW 1
349 #define HAS_SERIAL_HW_FLOW 0
352 struct ao_stm_usart {
353 struct ao_fifo rx_fifo;
354 struct ao_fifo tx_fifo;
355 struct stm_usart *reg;
358 #if HAS_SERIAL_SW_FLOW
359 /* RTS - 0 if we have FIFO space, 1 if not
360 * CTS - 0 if we can send, 0 if not
362 struct stm_gpio *gpio_rts;
363 struct stm_gpio *gpio_cts;
371 extern struct ao_stm_usart ao_stm_usart1;
375 extern struct ao_stm_usart ao_stm_usart2;
379 extern struct ao_stm_usart ao_stm_usart3;
382 #define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
384 typedef uint32_t ao_arch_irq_t;
386 static inline uint32_t
387 ao_arch_irqsave(void) {
389 asm("mrs %0,primask" : "=&r" (primask));
390 ao_arch_block_interrupts();
395 ao_arch_irqrestore(uint32_t primask) {
396 asm("msr primask,%0" : : "r" (primask));
400 ao_arch_memory_barrier(void) {
401 asm volatile("" ::: "memory");
406 ao_arch_init_stack(struct ao_task *task, uint32_t *sp, void *start)
408 uint32_t a = (uint32_t) start;
411 /* Return address (goes into LR) */
414 /* Clear register values r0-r7 */
422 /* PRIMASK with interrupts enabled */
428 static inline void ao_arch_save_regs(void) {
429 /* Save general registers */
430 asm("push {r0-r7,lr}\n");
437 asm("mrs r0,primask");
441 static inline void ao_arch_save_stack(void) {
443 asm("mov %0,sp" : "=&r" (sp) );
444 ao_cur_task->sp32 = (sp);
445 if (sp < &ao_cur_task->stack32[0])
446 ao_panic (AO_PANIC_STACK);
449 static inline void ao_arch_restore_stack(void) {
451 asm("mov sp, %0" : : "r" (ao_cur_task->sp32) );
453 /* Restore PRIMASK */
455 asm("msr primask,r0");
459 asm("msr apsr_nczvq,r0");
461 /* Restore general registers */
462 asm("pop {r0-r7,pc}\n");
465 static inline void ao_sleep_mode(void) {
468 WFI (Wait for Interrupt) or WFE (Wait for Event) while:
469 – Set SLEEPDEEP in Cortex ® -M0 System Control register
470 – Set PDDS bit in Power Control register (PWR_CR)
471 – Clear WUF bit in Power Control/Status register (PWR_CSR)
474 ao_arch_block_interrupts();
476 /* Enable power interface clock */
477 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_PWREN);
479 stm_scb.scr |= (1 << STM_SCB_SCR_SLEEPDEEP);
481 stm_pwr.cr |= (1 << STM_PWR_CR_PDDS) | (1 << STM_PWR_CR_LPDS);
483 stm_pwr.cr |= (1 << STM_PWR_CR_CWUF);
493 #ifndef HAS_SAMPLE_PROFILE
494 #define HAS_SAMPLE_PROFILE 0
497 #if !HAS_SAMPLE_PROFILE
498 #define HAS_ARCH_START_SCHEDULER 1
500 static inline void ao_arch_start_scheduler(void) {
504 asm("mrs %0,msp" : "=&r" (sp));
505 asm("msr psp,%0" : : "r" (sp));
506 asm("mrs %0,control" : "=&r" (control));
508 asm("msr control,%0" : : "r" (control));
513 #define ao_arch_isr_stack()
517 #define ao_arch_wait_interrupt() do { \
519 ao_arch_release_interrupts(); \
520 asm(".global ao_idle_loc\nao_idle_loc:"); \
521 ao_arch_block_interrupts(); \
524 #define ao_arch_critical(b) do { \
525 uint32_t __mask = ao_arch_irqsave(); \
526 do { b } while (0); \
527 ao_arch_irqrestore(__mask); \
534 ao_usb_alloc(uint16_t *buffers[2]);
537 ao_usb_alloc2(uint16_t *buffers[2]);
540 ao_usb_write(uint16_t len);
543 ao_usb_write2(uint16_t len);
544 #endif /* AO_USB_DIRECTIO */
549 ao_debug_out(char c);
551 #endif /* _AO_ARCH_FUNCS_H_ */