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   1 /*
   2  * Copyright © 2015 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; version 2 of the License.
   7  *
   8  * This program is distributed in the hope that it will be useful, but
   9  * WITHOUT ANY WARRANTY; without even the implied warranty of
  10  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  11  * General Public License for more details.
  12  *
  13  * You should have received a copy of the GNU General Public License along
  14  * with this program; if not, write to the Free Software Foundation, Inc.,
  15  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  16  */
  17
  18 #include <ao.h>
  19 #include <ao_data.h>
  20
  21 #define AO_ADC_DEBUG    0
  22
  23 static uint8_t  ao_adc_ready;
  24
  25 /*
  26  * Callback from DMA ISR
  27  *
  28  * Mark time in ring, shut down DMA engine
  29  */
  30 static void ao_adc_done(int index)
  31 {
  32         (void) index;
  33         /* Clear ISR bits */
  34         stm_adc.isr = ((1 << STM_ADC_ISR_AWD) |
  35                        (1 << STM_ADC_ISR_OVR) |
  36                        (1 << STM_ADC_ISR_EOSEQ) |
  37                        (1 << STM_ADC_ISR_EOC));
  38
  39         AO_DATA_PRESENT(AO_DATA_ADC);
  40         ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
  41         if (ao_data_present == AO_DATA_ALL) {
  42 #if HAS_MS5607
  43                 ao_data_ring[ao_data_head].ms5607_raw = ao_ms5607_current;
  44 #endif
  45 #if HAS_MMA655X
  46                 ao_data_ring[ao_data_head].mma655x = ao_mma655x_current;
  47 #endif
  48 #if HAS_HMC5883
  49                 ao_data_ring[ao_data_head].hmc5883 = ao_hmc5883_current;
  50 #endif
  51 #if HAS_MPU6000
  52                 ao_data_ring[ao_data_head].mpu6000 = ao_mpu6000_current;
  53 #endif
  54                 ao_data_ring[ao_data_head].tick = ao_tick_count;
  55                 ao_data_head = ao_data_ring_next(ao_data_head);
  56                 ao_wakeup((void *) &ao_data_head);
  57         }
  58         ao_adc_ready = 1;
  59 }
  60
  61 /*
  62  * Start the ADC sequence using the DMA engine
  63  */
  64 void
  65 ao_adc_poll(void)
  66 {
  67         if (!ao_adc_ready)
  68                 return;
  69         ao_adc_ready = 0;
  70         stm_adc.isr = 0;
  71         ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1),
  72                             &stm_adc.dr,
  73                             (void *) (&ao_data_ring[ao_data_head].adc),
  74                             AO_NUM_ADC,
  75                             (0 << STM_DMA_CCR_MEM2MEM) |
  76                             (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
  77                             (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
  78                             (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
  79                             (1 << STM_DMA_CCR_MINC) |
  80                             (0 << STM_DMA_CCR_PINC) |
  81                             (0 << STM_DMA_CCR_CIRC) |
  82                             (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR) |
  83                             (1 << STM_DMA_CCR_TCIE));
  84         ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1), ao_adc_done);
  85         ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
  86
  87         stm_adc.cr |= (1 << STM_ADC_CR_ADSTART);
  88 }
  89
  90 static void
  91 ao_adc_dump(void)
  92 {
  93         struct ao_data  packet;
  94
  95         ao_data_get(&packet);
  96         AO_ADC_DUMP(&packet);
  97 }
  98
  99 #if AO_ADC_DEBUG
 100 static void
 101 ao_adc_one(void)
 102 {
 103         int             ch;
 104         uint16_t        value;
 105
 106         ch = ao_cmd_decimal();
 107         if (ao_cmd_status != ao_cmd_success)
 108                 return;
 109         if (ch < 0 || AO_NUM_ADC <= ch) {
 110                 ao_cmd_status = ao_cmd_syntax_error;
 111                 return;
 112         }
 113
 114         ao_timer_set_adc_interval(0);
 115         ao_delay(1);
 116
 117         printf("At top, data %u isr %04x cr %04x\n", stm_adc.dr, stm_adc.isr, stm_adc.cr);
 118
 119         if (stm_adc.cr & (1 << STM_ADC_CR_ADEN)) {
 120                 printf("Disabling\n"); flush();
 121                 stm_adc.cr |= (1 << STM_ADC_CR_ADDIS);
 122                 while (stm_adc.cr & (1 << STM_ADC_CR_ADDIS))
 123                         ;
 124                 printf("Disabled\n"); flush();
 125         }
 126
 127         /* Turn off everything */
 128         stm_adc.cr &= ~((1 << STM_ADC_CR_ADCAL) |
 129                         (1 << STM_ADC_CR_ADSTP) |
 130                         (1 << STM_ADC_CR_ADSTART) |
 131                         (1 << STM_ADC_CR_ADEN));
 132
 133         printf("After disable, ADC status %04x\n", stm_adc.cr);
 134
 135         /* Configure */
 136         stm_adc.cfgr1 = ((0 << STM_ADC_CFGR1_AWDCH) |                             /* analog watchdog channel 0 */
 137                          (0 << STM_ADC_CFGR1_AWDEN) |                             /* Disable analog watchdog */
 138                          (0 << STM_ADC_CFGR1_AWDSGL) |                            /* analog watchdog on all channels */
 139                          (0 << STM_ADC_CFGR1_DISCEN) |                            /* Not discontinuous mode. All channels converted with one trigger */
 140                          (0 << STM_ADC_CFGR1_AUTOOFF) |                           /* Leave ADC running */
 141                          (1 << STM_ADC_CFGR1_WAIT) |                              /* Wait for data to be read before next conversion */
 142                          (0 << STM_ADC_CFGR1_CONT) |                              /* only one set of conversions per trigger */
 143                          (1 << STM_ADC_CFGR1_OVRMOD) |                            /* overwrite on overrun */
 144                          (STM_ADC_CFGR1_EXTEN_DISABLE << STM_ADC_CFGR1_EXTEN) |   /* SW trigger */
 145                          (0 << STM_ADC_CFGR1_ALIGN) |                             /* Align to LSB */
 146                          (STM_ADC_CFGR1_RES_12 << STM_ADC_CFGR1_RES) |            /* 12 bit resolution */
 147                          (STM_ADC_CFGR1_SCANDIR_UP << STM_ADC_CFGR1_SCANDIR) |    /* scan 0 .. n */
 148                          (STM_ADC_CFGR1_DMACFG_ONESHOT << STM_ADC_CFGR1_DMACFG) | /* one set of conversions then stop */
 149                          (0 << STM_ADC_CFGR1_DMAEN));                             /* disable DMA */
 150
 151         stm_adc.chselr = (1 << ch);
 152
 153         /* Longest sample time */
 154         stm_adc.smpr = STM_ADC_SMPR_SMP_41_5 << STM_ADC_SMPR_SMP;
 155
 156         printf("Before enable, ADC status %04x\n", stm_adc.cr); flush();
 157         /* Enable */
 158         stm_adc.cr |= (1 << STM_ADC_CR_ADEN);
 159         while ((stm_adc.isr & (1 << STM_ADC_ISR_ADRDY)) == 0)
 160                 ;
 161
 162         /* Start */
 163         stm_adc.cr |= (1 << STM_ADC_CR_ADSTART);
 164
 165         /* Wait for conversion complete */
 166         while (!(stm_adc.isr & (1 << STM_ADC_ISR_EOC)))
 167                 ;
 168
 169         value = stm_adc.dr;
 170         printf ("value %u, cr is %04x isr is %04x\n",
 171                 value, stm_adc.cr, stm_adc.isr);
 172
 173
 174         /* Clear ISR bits */
 175         stm_adc.isr = ((1 << STM_ADC_ISR_AWD) |
 176                        (1 << STM_ADC_ISR_OVR) |
 177                        (1 << STM_ADC_ISR_EOSEQ) |
 178                        (1 << STM_ADC_ISR_EOC));
 179 }
 180 #endif
 181
 182 const struct ao_cmds ao_adc_cmds[] = {
 183         { ao_adc_dump,  "a\0Display current ADC values" },
 184 #if AO_ADC_DEBUG
 185         { ao_adc_one,   "A ch\0Display one ADC channel" },
 186 #endif
 187         { 0, NULL },
 188 };
 189
 190 void
 191 ao_adc_init(void)
 192 {
 193         uint32_t        chselr;
 194
 195         /* Reset ADC */
 196         stm_rcc.apb2rstr |= (1 << STM_RCC_APB2RSTR_ADCRST);
 197         stm_rcc.apb2rstr &= ~(1 << STM_RCC_APB2RSTR_ADCRST);
 198
 199         /* Turn on ADC pins */
 200         stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
 201
 202 #ifdef AO_ADC_PIN0_PORT
 203         stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
 204         stm_pupdr_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_PUPDR_NONE);
 205 #endif
 206 #ifdef AO_ADC_PIN1_PORT
 207         stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
 208         stm_pupdr_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_PUPDR_NONE);
 209 #endif
 210 #ifdef AO_ADC_PIN2_PORT
 211         stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
 212         stm_pupdr_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_PUPDR_NONE);
 213 #endif
 214 #ifdef AO_ADC_PIN3_PORT
 215         stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
 216         stm_pupdr_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_PUPDR_NONE);
 217 #endif
 218 #ifdef AO_ADC_PIN4_PORT
 219         stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
 220         stm_pupdr_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_PUPDR_NONE);
 221 #endif
 222 #ifdef AO_ADC_PIN5_PORT
 223         stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
 224         stm_pupdr_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_PUPDR_NONE);
 225 #endif
 226 #ifdef AO_ADC_PIN6_PORT
 227         stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
 228         stm_pupdr_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_PUPDR_NONE);
 229 #endif
 230 #ifdef AO_ADC_PIN7_PORT
 231         stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
 232         stm_pupdr_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_PUPDR_NONE);
 233 #endif
 234 #ifdef AO_ADC_PIN24_PORT
 235         #error "Too many ADC ports"
 236 #endif
 237
 238         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADCEN);
 239
 240         chselr = 0;
 241 #if AO_NUM_ADC > 0
 242         chselr |= (1 << AO_ADC_PIN0_CH);
 243 #endif
 244 #if AO_NUM_ADC > 1
 245         chselr |= (1 << AO_ADC_PIN1_CH);
 246 #endif
 247 #if AO_NUM_ADC > 2
 248         chselr |= (1 << AO_ADC_PIN2_CH);
 249 #endif
 250 #if AO_NUM_ADC > 3
 251         chselr |= (1 << AO_ADC_PIN3_CH);
 252 #endif
 253 #if AO_NUM_ADC > 4
 254         chselr |= (1 << AO_ADC_PIN4_CH);
 255 #endif
 256 #if AO_NUM_ADC > 5
 257         chselr |= (1 << AO_ADC_PIN5_CH);
 258 #endif
 259 #if AO_NUM_ADC > 6
 260         chselr |= (1 << AO_ADC_PIN6_CH);
 261 #endif
 262 #if AO_NUM_ADC > 7
 263         chselr |= (1 << AO_ADC_PIN7_CH);
 264 #endif
 265 #if AO_NUM_ADC > 8
 266 #error Need more ADC defines
 267 #endif
 268
 269         /* Wait for ADC to be idle */
 270         while (stm_adc.cr & ((1 << STM_ADC_CR_ADCAL) |
 271                              (1 << STM_ADC_CR_ADDIS)))
 272                 ;
 273
 274         /* Disable */
 275         if (stm_adc.cr & (1 << STM_ADC_CR_ADEN)) {
 276                 stm_adc.cr |= (1 << STM_ADC_CR_ADDIS);
 277                 while (stm_adc.cr & (1 << STM_ADC_CR_ADDIS))
 278                         ;
 279         }
 280
 281         /* Turn off everything */
 282         stm_adc.cr &= ~((1 << STM_ADC_CR_ADCAL) |
 283                         (1 << STM_ADC_CR_ADSTP) |
 284                         (1 << STM_ADC_CR_ADSTART) |
 285                         (1 << STM_ADC_CR_ADEN));
 286
 287         /* Configure */
 288         stm_adc.cfgr1 = ((0 << STM_ADC_CFGR1_AWDCH) |                             /* analog watchdog channel 0 */
 289                          (0 << STM_ADC_CFGR1_AWDEN) |                             /* Disable analog watchdog */
 290                          (0 << STM_ADC_CFGR1_AWDSGL) |                            /* analog watchdog on all channels */
 291                          (0 << STM_ADC_CFGR1_DISCEN) |                            /* Not discontinuous mode. All channels converted with one trigger */
 292                          (0 << STM_ADC_CFGR1_AUTOOFF) |                           /* Leave ADC running */
 293                          (1 << STM_ADC_CFGR1_WAIT) |                              /* Wait for data to be read before next conversion */
 294                          (0 << STM_ADC_CFGR1_CONT) |                              /* only one set of conversions per trigger */
 295                          (1 << STM_ADC_CFGR1_OVRMOD) |                            /* overwrite on overrun */
 296                          (STM_ADC_CFGR1_EXTEN_DISABLE << STM_ADC_CFGR1_EXTEN) |   /* SW trigger */
 297                          (0 << STM_ADC_CFGR1_ALIGN) |                             /* Align to LSB */
 298                          (STM_ADC_CFGR1_RES_12 << STM_ADC_CFGR1_RES) |            /* 12 bit resolution */
 299                          (STM_ADC_CFGR1_SCANDIR_UP << STM_ADC_CFGR1_SCANDIR) |    /* scan 0 .. n */
 300                          (STM_ADC_CFGR1_DMACFG_ONESHOT << STM_ADC_CFGR1_DMACFG) | /* one set of conversions then stop */
 301                          (1 << STM_ADC_CFGR1_DMAEN));                             /* enable DMA */
 302
 303         /* Set the clock */
 304         stm_adc.cfgr2 = STM_ADC_CFGR2_CKMODE_PCLK_2 << STM_ADC_CFGR2_CKMODE;
 305
 306         /* Shortest sample time */
 307         stm_adc.smpr = STM_ADC_SMPR_SMP_71_5 << STM_ADC_SMPR_SMP;
 308
 309         stm_adc.chselr = chselr;
 310
 311         stm_adc.ccr = ((0 << STM_ADC_CCR_VBATEN) |
 312                        (0 << STM_ADC_CCR_TSEN) |
 313                        (0 << STM_ADC_CCR_VREFEN));
 314
 315         /* Calibrate */
 316         stm_adc.cr |= (1 << STM_ADC_CR_ADCAL);
 317         while ((stm_adc.cr & (1 << STM_ADC_CR_ADCAL)) != 0)
 318                 ;
 319
 320         /* Enable */
 321         stm_adc.cr |= (1 << STM_ADC_CR_ADEN);
 322         while ((stm_adc.isr & (1 << STM_ADC_ISR_ADRDY)) == 0)
 323                 ;
 324
 325         /* Clear any stale status bits */
 326         stm_adc.isr = 0;
 327
 328         /* Turn on syscfg */
 329         stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
 330
 331         /* Set ADC to use DMA channel 1 (option 1) */
 332         stm_syscfg.cfgr1 &= ~(1 << STM_SYSCFG_CFGR1_ADC_DMA_RMP);
 333
 334         ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
 335
 336         ao_cmd_register(&ao_adc_cmds[0]);
 337
 338         ao_adc_ready = 1;
 339 }