2 * Copyright © 2015 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 #define AO_ADC_DEBUG 0
23 static uint8_t ao_adc_ready;
26 * Callback from DMA ISR
28 * Mark time in ring, shut down DMA engine
30 static void ao_adc_done(int index)
34 stm_adc.isr = ((1 << STM_ADC_ISR_AWD) |
35 (1 << STM_ADC_ISR_OVR) |
36 (1 << STM_ADC_ISR_EOSEQ) |
37 (1 << STM_ADC_ISR_EOC));
39 AO_DATA_PRESENT(AO_DATA_ADC);
40 ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
41 ao_data_fill(ao_data_head);
46 * Start the ADC sequence using the DMA engine
55 ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1),
57 (void *) (&ao_data_ring[ao_data_head].adc),
59 (0 << STM_DMA_CCR_MEM2MEM) |
60 (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
61 (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
62 (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
63 (1 << STM_DMA_CCR_MINC) |
64 (0 << STM_DMA_CCR_PINC) |
65 (0 << STM_DMA_CCR_CIRC) |
66 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR) |
67 (1 << STM_DMA_CCR_TCIE));
68 ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1), ao_adc_done);
69 ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
71 stm_adc.cr |= (1 << STM_ADC_CR_ADSTART);
77 struct ao_data packet;
90 ch = ao_cmd_decimal();
91 if (ao_cmd_status != ao_cmd_success)
93 if (ch < 0 || AO_NUM_ADC <= ch) {
94 ao_cmd_status = ao_cmd_syntax_error;
98 ao_timer_set_adc_interval(0);
101 printf("At top, data %u isr %04x cr %04x\n", stm_adc.dr, stm_adc.isr, stm_adc.cr);
103 if (stm_adc.cr & (1 << STM_ADC_CR_ADEN)) {
104 printf("Disabling\n"); flush();
105 stm_adc.cr |= (1 << STM_ADC_CR_ADDIS);
106 while (stm_adc.cr & (1 << STM_ADC_CR_ADDIS))
108 printf("Disabled\n"); flush();
111 /* Turn off everything */
112 stm_adc.cr &= ~((1 << STM_ADC_CR_ADCAL) |
113 (1 << STM_ADC_CR_ADSTP) |
114 (1 << STM_ADC_CR_ADSTART) |
115 (1 << STM_ADC_CR_ADEN));
117 printf("After disable, ADC status %04x\n", stm_adc.cr);
120 stm_adc.cfgr1 = ((0 << STM_ADC_CFGR1_AWDCH) | /* analog watchdog channel 0 */
121 (0 << STM_ADC_CFGR1_AWDEN) | /* Disable analog watchdog */
122 (0 << STM_ADC_CFGR1_AWDSGL) | /* analog watchdog on all channels */
123 (0 << STM_ADC_CFGR1_DISCEN) | /* Not discontinuous mode. All channels converted with one trigger */
124 (0 << STM_ADC_CFGR1_AUTOOFF) | /* Leave ADC running */
125 (1 << STM_ADC_CFGR1_WAIT) | /* Wait for data to be read before next conversion */
126 (0 << STM_ADC_CFGR1_CONT) | /* only one set of conversions per trigger */
127 (1 << STM_ADC_CFGR1_OVRMOD) | /* overwrite on overrun */
128 (STM_ADC_CFGR1_EXTEN_DISABLE << STM_ADC_CFGR1_EXTEN) | /* SW trigger */
129 (0 << STM_ADC_CFGR1_ALIGN) | /* Align to LSB */
130 (STM_ADC_CFGR1_RES_12 << STM_ADC_CFGR1_RES) | /* 12 bit resolution */
131 (STM_ADC_CFGR1_SCANDIR_UP << STM_ADC_CFGR1_SCANDIR) | /* scan 0 .. n */
132 (STM_ADC_CFGR1_DMACFG_ONESHOT << STM_ADC_CFGR1_DMACFG) | /* one set of conversions then stop */
133 (0 << STM_ADC_CFGR1_DMAEN)); /* disable DMA */
135 stm_adc.chselr = (1 << ch);
137 /* Longest sample time */
138 stm_adc.smpr = STM_ADC_SMPR_SMP_41_5 << STM_ADC_SMPR_SMP;
140 printf("Before enable, ADC status %04x\n", stm_adc.cr); flush();
142 stm_adc.cr |= (1 << STM_ADC_CR_ADEN);
143 while ((stm_adc.isr & (1 << STM_ADC_ISR_ADRDY)) == 0)
147 stm_adc.cr |= (1 << STM_ADC_CR_ADSTART);
149 /* Wait for conversion complete */
150 while (!(stm_adc.isr & (1 << STM_ADC_ISR_EOC)))
154 printf ("value %u, cr is %04x isr is %04x\n",
155 value, stm_adc.cr, stm_adc.isr);
159 stm_adc.isr = ((1 << STM_ADC_ISR_AWD) |
160 (1 << STM_ADC_ISR_OVR) |
161 (1 << STM_ADC_ISR_EOSEQ) |
162 (1 << STM_ADC_ISR_EOC));
166 const struct ao_cmds ao_adc_cmds[] = {
167 { ao_adc_dump, "a\0Display current ADC values" },
169 { ao_adc_one, "A ch\0Display one ADC channel" },
180 stm_rcc.apb2rstr |= (1 << STM_RCC_APB2RSTR_ADCRST);
181 stm_rcc.apb2rstr &= ~(1UL << STM_RCC_APB2RSTR_ADCRST);
183 /* Turn on ADC pins */
184 stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
186 #ifdef AO_ADC_PIN0_PORT
187 stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
188 stm_pupdr_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_PUPDR_NONE);
190 #ifdef AO_ADC_PIN1_PORT
191 stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
192 stm_pupdr_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_PUPDR_NONE);
194 #ifdef AO_ADC_PIN2_PORT
195 stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
196 stm_pupdr_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_PUPDR_NONE);
198 #ifdef AO_ADC_PIN3_PORT
199 stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
200 stm_pupdr_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_PUPDR_NONE);
202 #ifdef AO_ADC_PIN4_PORT
203 stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
204 stm_pupdr_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_PUPDR_NONE);
206 #ifdef AO_ADC_PIN5_PORT
207 stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
208 stm_pupdr_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_PUPDR_NONE);
210 #ifdef AO_ADC_PIN6_PORT
211 stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
212 stm_pupdr_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_PUPDR_NONE);
214 #ifdef AO_ADC_PIN7_PORT
215 stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
216 stm_pupdr_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_PUPDR_NONE);
218 #ifdef AO_ADC_PIN24_PORT
219 #error "Too many ADC ports"
222 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADCEN);
226 chselr |= (1 << AO_ADC_PIN0_CH);
229 chselr |= (1 << AO_ADC_PIN1_CH);
232 chselr |= (1 << AO_ADC_PIN2_CH);
235 chselr |= (1 << AO_ADC_PIN3_CH);
238 chselr |= (1 << AO_ADC_PIN4_CH);
241 chselr |= (1 << AO_ADC_PIN5_CH);
244 chselr |= (1 << AO_ADC_PIN6_CH);
247 chselr |= (1 << AO_ADC_PIN7_CH);
250 #error Need more ADC defines
253 /* Wait for ADC to be idle */
254 while (stm_adc.cr & ((1UL << STM_ADC_CR_ADCAL) |
255 (1UL << STM_ADC_CR_ADDIS)))
259 if (stm_adc.cr & (1 << STM_ADC_CR_ADEN)) {
260 stm_adc.cr |= (1 << STM_ADC_CR_ADDIS);
261 while (stm_adc.cr & (1 << STM_ADC_CR_ADDIS))
265 /* Turn off everything */
266 stm_adc.cr &= ~((1UL << STM_ADC_CR_ADCAL) |
267 (1UL << STM_ADC_CR_ADSTP) |
268 (1UL << STM_ADC_CR_ADSTART) |
269 (1UL << STM_ADC_CR_ADEN));
272 stm_adc.cfgr1 = ((0 << STM_ADC_CFGR1_AWDCH) | /* analog watchdog channel 0 */
273 (0 << STM_ADC_CFGR1_AWDEN) | /* Disable analog watchdog */
274 (0 << STM_ADC_CFGR1_AWDSGL) | /* analog watchdog on all channels */
275 (0 << STM_ADC_CFGR1_DISCEN) | /* Not discontinuous mode. All channels converted with one trigger */
276 (0 << STM_ADC_CFGR1_AUTOOFF) | /* Leave ADC running */
277 (1 << STM_ADC_CFGR1_WAIT) | /* Wait for data to be read before next conversion */
278 (0 << STM_ADC_CFGR1_CONT) | /* only one set of conversions per trigger */
279 (1 << STM_ADC_CFGR1_OVRMOD) | /* overwrite on overrun */
280 (STM_ADC_CFGR1_EXTEN_DISABLE << STM_ADC_CFGR1_EXTEN) | /* SW trigger */
281 (0 << STM_ADC_CFGR1_ALIGN) | /* Align to LSB */
282 (STM_ADC_CFGR1_RES_12 << STM_ADC_CFGR1_RES) | /* 12 bit resolution */
283 (STM_ADC_CFGR1_SCANDIR_UP << STM_ADC_CFGR1_SCANDIR) | /* scan 0 .. n */
284 (STM_ADC_CFGR1_DMACFG_ONESHOT << STM_ADC_CFGR1_DMACFG) | /* one set of conversions then stop */
285 (1 << STM_ADC_CFGR1_DMAEN)); /* enable DMA */
288 stm_adc.cfgr2 = STM_ADC_CFGR2_CKMODE_PCLK_2 << STM_ADC_CFGR2_CKMODE;
290 /* Shortest sample time */
291 stm_adc.smpr = STM_ADC_SMPR_SMP_71_5 << STM_ADC_SMPR_SMP;
293 stm_adc.chselr = chselr;
295 stm_adc.ccr = ((0 << STM_ADC_CCR_VBATEN) |
296 (0 << STM_ADC_CCR_TSEN) |
297 (0 << STM_ADC_CCR_VREFEN));
300 stm_adc.cr |= (1UL << STM_ADC_CR_ADCAL);
301 while ((stm_adc.cr & (1UL << STM_ADC_CR_ADCAL)) != 0)
305 stm_adc.cr |= (1 << STM_ADC_CR_ADEN);
306 while ((stm_adc.isr & (1 << STM_ADC_ISR_ADRDY)) == 0)
309 /* Clear any stale status bits */
313 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
315 /* Set ADC to use DMA channel 1 (option 1) */
316 stm_syscfg.cfgr1 &= ~(1UL << STM_SYSCFG_CFGR1_ADC_DMA_RMP);
318 ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
320 ao_cmd_register(&ao_adc_cmds[0]);