2 * Copyright © 2015 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #include <ao_adc_fast.h>
21 uint16_t ao_adc_ring[AO_ADC_RING_SIZE] __attribute__((aligned(4)));
23 /* Maximum number of samples fetched per _ao_adc_start call */
24 #define AO_ADC_RING_CHUNK (AO_ADC_RING_SIZE >> 1)
26 uint16_t ao_adc_ring_head, ao_adc_ring_remain;
27 uint16_t ao_adc_running;
30 * Callback from DMA ISR
32 * Wakeup any waiting processes, mark the DMA as done, start the ADC
33 * if there's still lots of space in the ring
35 static void ao_adc_dma_done(int index)
38 ao_adc_ring_head += ao_adc_running;
39 ao_adc_ring_remain += ao_adc_running;
40 if (ao_adc_ring_head == AO_ADC_RING_SIZE)
43 ao_wakeup(&ao_adc_ring_head);
44 ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
56 count = _ao_adc_space();
59 if (count > AO_ADC_RING_CHUNK)
60 count = AO_ADC_RING_CHUNK;
61 ao_adc_running = count;
62 buf = ao_adc_ring + ao_adc_ring_head;
64 ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1),
68 (0 << STM_DMA_CCR_MEM2MEM) |
69 (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
70 (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
71 (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
72 (1 << STM_DMA_CCR_MINC) |
73 (0 << STM_DMA_CCR_PINC) |
74 (0 << STM_DMA_CCR_CIRC) |
75 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
76 ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1), ao_adc_dma_done);
77 ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));
79 stm_adc.cr |= (1 << STM_ADC_CR_ADSTART);
89 stm_rcc.apb2rstr |= (1 << STM_RCC_APB2RSTR_ADCRST);
90 stm_rcc.apb2rstr &= ~(1 << STM_RCC_APB2RSTR_ADCRST);
92 /* Turn on ADC pins */
93 stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
95 #ifdef AO_ADC_PIN0_PORT
96 stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
98 #ifdef AO_ADC_PIN1_PORT
99 stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
101 #ifdef AO_ADC_PIN2_PORT
102 stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
104 #ifdef AO_ADC_PIN3_PORT
105 stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
107 #ifdef AO_ADC_PIN4_PORT
108 stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
110 #ifdef AO_ADC_PIN5_PORT
111 stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
113 #ifdef AO_ADC_PIN6_PORT
114 stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
116 #ifdef AO_ADC_PIN7_PORT
117 stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
119 #ifdef AO_ADC_PIN24_PORT
120 #error "Too many ADC ports"
123 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADCEN);
127 chselr |= (1 << AO_ADC_PIN0_CH);
130 chselr |= (1 << AO_ADC_PIN1_CH);
133 chselr |= (1 << AO_ADC_PIN2_CH);
136 chselr |= (1 << AO_ADC_PIN3_CH);
139 chselr |= (1 << AO_ADC_PIN4_CH);
142 chselr |= (1 << AO_ADC_PIN5_CH);
145 chselr |= (1 << AO_ADC_PIN6_CH);
148 chselr |= (1 << AO_ADC_PIN7_CH);
151 #error Need more ADC defines
155 stm_adc.cfgr2 = STM_ADC_CFGR2_CKMODE_PCLK_2 << STM_ADC_CFGR2_CKMODE;
157 /* Shortest sample time */
158 stm_adc.smpr = STM_ADC_SMPR_SMP_1_5 << STM_ADC_SMPR_SMP;
161 stm_adc.cr |= (1 << STM_ADC_CR_ADCAL);
162 for (i = 0; i < 0xf000; i++) {
163 if ((stm_adc.cr & (1 << STM_ADC_CR_ADCAL)) == 0)
168 stm_adc.cr |= (1 << STM_ADC_CR_ADEN);
169 while ((stm_adc.isr & (1 << STM_ADC_ISR_ADRDY)) == 0)
172 stm_adc.chselr = chselr;
174 stm_adc.cfgr1 = ((0 << STM_ADC_CFGR1_AWDCH) |
175 (0 << STM_ADC_CFGR1_AWDEN) |
176 (0 << STM_ADC_CFGR1_AWDSGL) |
177 (0 << STM_ADC_CFGR1_DISCEN) |
178 (0 << STM_ADC_CFGR1_AUTOOFF) |
179 (0 << STM_ADC_CFGR1_WAIT) |
180 (1 << STM_ADC_CFGR1_CONT) |
181 (1 << STM_ADC_CFGR1_OVRMOD) |
182 (STM_ADC_CFGR1_EXTEN_DISABLE << STM_ADC_CFGR1_EXTEN) |
183 (0 << STM_ADC_CFGR1_ALIGN) |
184 (STM_ADC_CFGR1_RES_12 << STM_ADC_CFGR1_RES) |
185 (STM_ADC_CFGR1_SCANDIR_UP << STM_ADC_CFGR1_SCANDIR) |
186 (STM_ADC_CFGR1_DMACFG_ONESHOT << STM_ADC_CFGR1_DMACFG) |
187 (1 << STM_ADC_CFGR1_DMAEN));
190 /* Clear any stale status bits */
194 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGCOMPEN);
196 /* Set ADC to use DMA channel 1 (option 1) */
197 stm_syscfg.cfgr1 &= ~(1 << STM_SYSCFG_CFGR1_ADC_DMA_RMP);
199 ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC_1));