2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #ifndef _AO_ARCH_FUNCS_H_
20 #define _AO_ARCH_FUNCS_H_
25 /* PCLK is set to 16MHz (HCLK 32MHz, APB prescaler 2) */
27 #define _AO_SPI_SPEED_8MHz STM_SPI_CR1_BR_PCLK_2
28 #define _AO_SPI_SPEED_4MHz STM_SPI_CR1_BR_PCLK_4
29 #define _AO_SPI_SPEED_2MHz STM_SPI_CR1_BR_PCLK_8
30 #define _AO_SPI_SPEED_1MHz STM_SPI_CR1_BR_PCLK_16
31 #define _AO_SPI_SPEED_500kHz STM_SPI_CR1_BR_PCLK_32
32 #define _AO_SPI_SPEED_250kHz STM_SPI_CR1_BR_PCLK_64
33 #define _AO_SPI_SPEED_125kHz STM_SPI_CR1_BR_PCLK_128
34 #define _AO_SPI_SPEED_62500Hz STM_SPI_CR1_BR_PCLK_256
36 /* Companion bus wants something no faster than 200kHz */
38 static inline uint32_t
39 ao_spi_speed(uint32_t hz)
41 if (hz >= 4000000) return _AO_SPI_SPEED_4MHz;
42 if (hz >= 2000000) return _AO_SPI_SPEED_2MHz;
43 if (hz >= 1000000) return _AO_SPI_SPEED_1MHz;
44 if (hz >= 500000) return _AO_SPI_SPEED_500kHz;
45 if (hz >= 250000) return _AO_SPI_SPEED_250kHz;
46 if (hz >= 125000) return _AO_SPI_SPEED_125kHz;
47 return _AO_SPI_SPEED_62500Hz;
50 #define AO_SPI_CPOL_BIT 4
51 #define AO_SPI_CPHA_BIT 5
53 #define AO_SPI_CONFIG_1 0x00
54 #define AO_SPI_1_CONFIG_PA5_PA6_PA7 AO_SPI_CONFIG_1
56 #define AO_SPI_CONFIG_2 0x04
57 #define AO_SPI_1_CONFIG_PA12_PA13_PA14 AO_SPI_CONFIG_2
58 #define AO_SPI_2_CONFIG_PD1_PD3_PD4 AO_SPI_CONFIG_2
60 #define AO_SPI_CONFIG_3 0x08
61 #define AO_SPI_1_CONFIG_PB3_PB4_PB5 AO_SPI_CONFIG_3
63 #define AO_SPI_CONFIG_NONE 0x0c
65 #define AO_SPI_INDEX_MASK 0x01
66 #define AO_SPI_CONFIG_MASK 0x0c
68 #define AO_SPI_1_PA5_PA6_PA7 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA5_PA6_PA7)
69 #define AO_SPI_1_PA12_PA13_PA14 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA12_PA13_PA14)
70 #define AO_SPI_1_PB3_PB4_PB5 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PB3_PB4_PB5)
72 #define AO_SPI_2_PB13_PB14_PB15 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PB13_PB14_PB15)
73 #define AO_SPI_2_PD1_PD3_PD4 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PD1_PD3_PD4)
75 #define AO_SPI_INDEX(id) ((id) & AO_SPI_INDEX_MASK)
76 #define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
77 #define AO_SPI_PIN_CONFIG(id) ((id) & (AO_SPI_INDEX_MASK | AO_SPI_CONFIG_MASK))
78 #define AO_SPI_CPOL(id) ((uint32_t) (((id) >> AO_SPI_CPOL_BIT) & 1))
79 #define AO_SPI_CPHA(id) ((uint32_t) (((id) >> AO_SPI_CPHA_BIT) & 1))
81 #define AO_SPI_MAKE_MODE(pol,pha) (((pol) << AO_SPI_CPOL_BIT) | ((pha) << AO_SPI_CPHA_BIT))
82 #define AO_SPI_MODE_0 AO_SPI_MAKE_MODE(0,0)
83 #define AO_SPI_MODE_1 AO_SPI_MAKE_MODE(0,1)
84 #define AO_SPI_MODE_2 AO_SPI_MAKE_MODE(1,0)
85 #define AO_SPI_MODE_3 AO_SPI_MAKE_MODE(1,1)
88 ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id);
91 ao_spi_get(uint8_t spi_index, uint32_t speed);
94 ao_spi_put(uint8_t spi_index);
97 ao_spi_send(const void *block, uint16_t len, uint8_t spi_index);
100 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
103 ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index);
106 ao_spi_start_bytes(uint8_t spi_index);
109 ao_spi_stop_bytes(uint8_t spi_index);
112 ao_spi_send_byte(uint8_t byte, uint8_t spi_index)
114 struct stm_spi *stm_spi = &stm_spi1;
117 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
120 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
125 static inline uint8_t
126 ao_spi_recv_byte(uint8_t spi_index)
128 struct stm_spi *stm_spi = &stm_spi1;
131 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
134 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
136 return (uint8_t) stm_spi->dr;
140 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
143 ao_spi_duplex(const void *out, void *in, uint16_t len, uint8_t spi_index);
148 #define ao_spi_set_cs(reg,mask) ((reg)->bsrr = ((uint32_t) (mask)) << 16)
149 #define ao_spi_clr_cs(reg,mask) ((reg)->bsrr = (mask))
151 #define ao_spi_get_mask(reg,mask,bus, speed) do { \
152 ao_spi_get(bus, speed); \
153 ao_spi_set_cs(reg,mask); \
156 static inline uint8_t
157 ao_spi_try_get_mask(struct stm_gpio *reg, uint16_t mask, uint8_t bus, uint32_t speed, uint8_t task_id)
159 if (!ao_spi_try_get(bus, speed, task_id))
161 ao_spi_set_cs(reg, mask);
165 #define ao_spi_put_mask(reg,mask,bus) do { \
166 ao_spi_clr_cs(reg,mask); \
170 #define ao_spi_get_bit(reg,bit,bus,speed) ao_spi_get_mask(reg,(1<<bit),bus,speed)
171 #define ao_spi_put_bit(reg,bit,bus) ao_spi_put_mask(reg,(1<<bit),bus)
173 #define ao_enable_port(port) do { \
174 if ((port) == &stm_gpioa) \
175 stm_rcc.iopenr |= (1 << STM_RCC_IOPENR_IOPAEN); \
176 else if ((port) == &stm_gpiob) \
177 stm_rcc.iopenr |= (1 << STM_RCC_IOPENR_IOPBEN); \
178 else if ((port) == &stm_gpioc) \
179 stm_rcc.iopenr |= (1 << STM_RCC_IOPENR_IOPCEN); \
180 else if ((port) == &stm_gpiod) \
181 stm_rcc.iopenr |= (1 << STM_RCC_IOPENR_IOPDEN); \
182 else if ((port) == &stm_gpioe) \
183 stm_rcc.iopenr |= (1 << STM_RCC_IOPENR_IOPEEN); \
184 else if ((port) == &stm_gpioh) \
185 stm_rcc.iopenr |= (1 << STM_RCC_IOPENR_IOPHEN); \
188 #define ao_disable_port(port) do { \
189 if ((port) == &stm_gpioa) \
190 stm_rcc.iopenr &= ~(1 << STM_RCC_IOPENR_IOPAEN); \
191 else if ((port) == &stm_gpiob) \
192 stm_rcc.iopenr &= ~(1 << STM_RCC_IOPENR_IOPBEN); \
193 else if ((port) == &stm_gpioc) \
194 stm_rcc.iopenr &= ~(1 << STM_RCC_IOPENR_IOPCEN); \
195 else if ((port) == &stm_gpiod) \
196 stm_rcc.iopenr &= ~(1 << STM_RCC_IOPENR_IOPDEN); \
197 else if ((port) == &stm_gpioe) \
198 stm_rcc.iopenr &= ~(1 << STM_RCC_IOPENR_IOPEEN); \
199 else if ((port) == &stm_gpioh) \
200 stm_rcc.iopenr &= ~(1 << STM_RCC_IOPENR_IOPHEN); \
204 #define ao_gpio_set(port, bit, v) stm_gpio_set(port, bit, v)
206 #define ao_gpio_get(port, bit) stm_gpio_get(port, bit)
208 #define ao_gpio_set_bits(port, bits) stm_gpio_set_bits(port, bits)
210 #define ao_gpio_set_mask(port, bits, mask) stm_gpio_set_mask(port, bits, mask)
212 #define ao_gpio_clr_bits(port, bits) stm_gpio_clr_bits(port, bits);
214 #define ao_gpio_get_all(port) stm_gpio_get_all(port)
216 #define ao_enable_output(port,bit,v) do { \
217 ao_enable_port(port); \
218 ao_gpio_set(port, bit, v); \
219 stm_moder_set(port, bit, STM_MODER_OUTPUT);\
222 #define ao_enable_output_mask(port,bits,mask) do { \
223 ao_enable_port(port); \
224 ao_gpio_set_mask(port, bits, mask); \
225 ao_set_output_mask(port, mask); \
228 #define AO_OUTPUT_PUSH_PULL STM_OTYPER_PUSH_PULL
229 #define AO_OUTPUT_OPEN_DRAIN STM_OTYPER_OPEN_DRAIN
231 #define ao_gpio_set_output_mode(port,bit,mode) \
232 stm_otyper_set(port, pin, mode)
234 #define ao_gpio_set_mode(port,bit,mode) do { \
235 if (mode == AO_EXTI_MODE_PULL_UP) \
236 stm_pupdr_set(port, bit, STM_PUPDR_PULL_UP); \
237 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
238 stm_pupdr_set(port, bit, STM_PUPDR_PULL_DOWN); \
240 stm_pupdr_set(port, bit, STM_PUPDR_NONE); \
243 #define ao_gpio_set_mode_mask(port,mask,mode) do { \
244 if (mode == AO_EXTI_MODE_PULL_UP) \
245 stm_pupdr_set_mask(port, mask, STM_PUPDR_PULL_UP); \
246 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
247 stm_pupdr_set_mask(port, mask, STM_PUPDR_PULL_DOWN); \
249 stm_pupdr_set_mask(port, mask, STM_PUPDR_NONE); \
252 #define ao_set_input(port, bit) do { \
253 stm_moder_set(port, bit, STM_MODER_INPUT); \
256 #define ao_set_output(port, bit, v) do { \
257 ao_gpio_set(port, bit, v); \
258 stm_moder_set(port, bit, STM_MODER_OUTPUT); \
261 #define ao_set_output_mask(port, mask) do { \
262 stm_moder_set_mask(port, mask, STM_MODER_OUTPUT); \
265 #define ao_set_input_mask(port, mask) do { \
266 stm_moder_set_mask(port, mask, STM_MODER_INPUT); \
269 #define ao_enable_input(port,bit,mode) do { \
270 ao_enable_port(port); \
271 ao_set_input(port, bit); \
272 ao_gpio_set_mode(port, bit, mode); \
275 #define ao_enable_input_mask(port,mask,mode) do { \
276 ao_enable_port(port); \
277 ao_gpio_set_mode_mask(port, mask, mode); \
278 ao_set_input_mask(port, mask); \
281 #define _ao_enable_cs(port, bit) do { \
282 stm_gpio_set((port), bit, 1); \
283 stm_moder_set((port), bit, STM_MODER_OUTPUT); \
286 #define ao_enable_cs(port,bit) do { \
287 ao_enable_port(port); \
288 _ao_enable_cs(port, bit); \
291 #define ao_spi_init_cs(port, mask) do { \
292 ao_enable_port(port); \
293 if ((mask) & 0x0001) _ao_enable_cs(port, 0); \
294 if ((mask) & 0x0002) _ao_enable_cs(port, 1); \
295 if ((mask) & 0x0004) _ao_enable_cs(port, 2); \
296 if ((mask) & 0x0008) _ao_enable_cs(port, 3); \
297 if ((mask) & 0x0010) _ao_enable_cs(port, 4); \
298 if ((mask) & 0x0020) _ao_enable_cs(port, 5); \
299 if ((mask) & 0x0040) _ao_enable_cs(port, 6); \
300 if ((mask) & 0x0080) _ao_enable_cs(port, 7); \
301 if ((mask) & 0x0100) _ao_enable_cs(port, 8); \
302 if ((mask) & 0x0200) _ao_enable_cs(port, 9); \
303 if ((mask) & 0x0400) _ao_enable_cs(port, 10);\
304 if ((mask) & 0x0800) _ao_enable_cs(port, 11);\
305 if ((mask) & 0x1000) _ao_enable_cs(port, 12);\
306 if ((mask) & 0x2000) _ao_enable_cs(port, 13);\
307 if ((mask) & 0x4000) _ao_enable_cs(port, 14);\
308 if ((mask) & 0x8000) _ao_enable_cs(port, 15);\
314 extern uint8_t ao_dma_done[STM_NUM_DMA];
317 ao_dma_set_transfer(uint8_t index,
318 volatile void *peripheral,
324 ao_dma_set_isr(uint8_t index, void (*isr)(int index));
327 ao_dma_start(uint8_t index);
330 ao_dma_done_transfer(uint8_t index);
333 ao_dma_alloc(uint8_t index, uint8_t cselr);
341 ao_i2c_get(uint8_t i2c_index);
344 ao_i2c_start(uint8_t i2c_index, uint16_t address);
347 ao_i2c_put(uint8_t i2c_index);
350 ao_i2c_send(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
353 ao_i2c_recv(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
358 #if USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_SW_FLOW || USE_SERIAL_3_SW_FLOW
359 #define HAS_SERIAL_SW_FLOW 1
361 #define HAS_SERIAL_SW_FLOW 0
364 #if USE_SERIAL_1_FLOW && !USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_FLOW && !USE_SERIAL_2_SW_FLOW || USE_SERIAL_3_FLOW && !USE_SERIAL_3_SW_FLOW
365 #define HAS_SERIAL_HW_FLOW 1
367 #define HAS_SERIAL_HW_FLOW 0
370 /* ao_serial_stm.c */
371 struct ao_stm_usart {
372 struct ao_fifo rx_fifo;
373 struct ao_fifo tx_fifo;
374 struct stm_usart *reg;
377 #if HAS_SERIAL_SW_FLOW
378 /* RTS - 0 if we have FIFO space, 1 if not
379 * CTS - 0 if we can send, 0 if not
381 struct stm_gpio *gpio_rts;
382 struct stm_gpio *gpio_cts;
389 #include <ao_lpuart.h>
392 ao_debug_out(char c);
395 extern struct ao_stm_usart ao_stm_usart1;
399 extern struct ao_stm_usart ao_stm_usart2;
403 extern struct ao_stm_usart ao_stm_usart3;
406 #define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
408 typedef uint32_t ao_arch_irq_t;
411 ao_arch_block_interrupts(void) {
412 #ifdef AO_NONMASK_INTERRUPTS
413 asm("msr basepri,%0" : : "r" (AO_STM_NVIC_BASEPRI_MASK));
420 ao_arch_release_interrupts(void) {
421 #ifdef AO_NONMASK_INTERRUPTS
422 asm("msr basepri,%0" : : "r" (0x0));
428 static inline uint32_t
429 ao_arch_irqsave(void) {
431 #ifdef AO_NONMASK_INTERRUPTS
432 asm("mrs %0,basepri" : "=r" (val));
434 asm("mrs %0,primask" : "=r" (val));
436 ao_arch_block_interrupts();
441 ao_arch_irqrestore(uint32_t basepri) {
442 #ifdef AO_NONMASK_INTERRUPTS
443 asm("msr basepri,%0" : : "r" (basepri));
445 asm("msr primask,%0" : : "r" (basepri));
450 ao_arch_memory_barrier(void) {
451 asm volatile("" ::: "memory");
455 ao_arch_irq_check(void) {
456 #ifdef AO_NONMASK_INTERRUPTS
458 asm("mrs %0,basepri" : "=r" (basepri));
460 ao_panic(AO_PANIC_IRQ);
463 asm("mrs %0,primask" : "=r" (primask));
464 if ((primask & 1) == 0)
465 ao_panic(AO_PANIC_IRQ);
471 ao_arch_init_stack(struct ao_task *task, void *start)
473 uint32_t *sp = &task->stack32[AO_STACK_SIZE >> 2];
474 uint32_t a = (uint32_t) start;
477 /* Return address (goes into LR) */
480 /* Clear register values r0-r7 */
488 /* PRIMASK with interrupts enabled */
494 static inline void ao_arch_save_regs(void) {
495 /* Save general registers */
496 asm("push {r0-r7,lr}\n");
503 asm("mrs r0,primask");
507 static inline void ao_arch_save_stack(void) {
509 asm("mov %0,sp" : "=&r" (sp) );
510 ao_cur_task->sp32 = (sp);
513 static inline void ao_arch_restore_stack(void) {
515 asm("mov sp, %0" : : "r" (ao_cur_task->sp32) );
517 /* Restore PRIMASK */
519 asm("msr primask,r0");
523 asm("msr apsr_nczvq,r0");
525 /* Restore general registers */
526 asm("pop {r0-r7,pc}\n");
529 #ifndef HAS_SAMPLE_PROFILE
530 #define HAS_SAMPLE_PROFILE 0
534 #define HAS_ARCH_VALIDATE_CUR_STACK 1
537 ao_validate_cur_stack(void)
541 asm("mrs %0,psp" : "=&r" (psp));
543 psp <= ao_cur_task->stack &&
544 psp >= ao_cur_task->stack - 256)
545 ao_panic(AO_PANIC_STACK);
549 #if !HAS_SAMPLE_PROFILE
550 #define HAS_ARCH_START_SCHEDULER 1
552 static inline void ao_arch_start_scheduler(void) {
556 asm("mrs %0,msp" : "=&r" (sp));
557 asm("msr psp,%0" : : "r" (sp));
558 asm("mrs %0,control" : "=r" (control));
560 asm("msr control,%0" : : "r" (control));
565 #define ao_arch_isr_stack()
570 ao_arch_wait_interrupt(void) {
571 #ifdef AO_NONMASK_INTERRUPTS
573 "dsb\n" /* Serialize data */
574 "isb\n" /* Serialize instructions */
575 "cpsid i\n" /* Block all interrupts */
576 "msr basepri,%0\n" /* Allow all interrupts through basepri */
577 "wfi\n" /* Wait for an interrupt */
578 "cpsie i\n" /* Allow all interrupts */
579 "msr basepri,%1\n" /* Block interrupts through basepri */
580 : : "r" (0), "r" (AO_STM_NVIC_BASEPRI_MASK));
583 ao_arch_release_interrupts();
584 ao_arch_block_interrupts();
588 #define ao_arch_critical(b) do { \
589 uint32_t __mask = ao_arch_irqsave(); \
590 do { b } while (0); \
591 ao_arch_irqrestore(__mask); \
597 ao_storage_device_is_erased(uint32_t pos);
599 #endif /* _AO_ARCH_FUNCS_H_ */