2 * Copyright © 2018 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
20 typedef volatile uint32_t vuint32_t;
21 typedef volatile void * vvoid_t;
22 typedef volatile uint16_t vuint16_t;
23 typedef volatile uint8_t vuint8_t;
30 extern struct stm_pwr stm_pwr;
32 #define stm_pwr (*((struct stm_pwr *) 0x40007000))
34 #define STM_PWR_CR_FISSR 21
35 #define STM_PWR_CR_FMSSR 20
36 #define STM_PWR_CR_VOS 14
37 #define STM_PWR_CR_VOS_SCALE_MODE_3 1
38 #define STM_PWR_CR_VOS_SCALE_MODE_2 2
39 #define STM_PWR_CR_VOS_SCALE_MODE_1 3
40 #define STM_PWR_CR_VOS_SCALE_MODE_MASK 3
41 #define STM_PWR_CR_ADCDC1 13
42 #define STM_PWR_CR_MRLVDS 11
43 #define STM_PWR_CR_LPLVDS 10
44 #define STM_PWR_CR_FPDS 9
45 #define STM_PWR_CR_DBP 8
46 #define STM_PWR_CR_PLS 5
47 #define STM_PWR_CR_PVDE 4
48 #define STM_PWR_CR_CSBF 3
49 #define STM_PWR_CR_CWUF 2
50 #define STM_PWR_CR_PDDS 1
51 #define STM_PWR_CR_LPDS 0
103 extern struct stm_rcc stm_rcc;
105 #define stm_rcc (*((struct stm_rcc *) 0x40023800))
107 /* Internal HSI is 16MHz */
108 #define STM_HSI_FREQ 16000000
110 #define STM_RCC_CR_PLLI2SRDY (27)
111 #define STM_RCC_CR_PLLI2SON (26)
112 #define STM_RCC_CR_PLLRDY (25)
113 #define STM_RCC_CR_PLLON (24)
114 #define STM_RCC_CR_CSSON (19)
115 #define STM_RCC_CR_HSEBYP (18)
116 #define STM_RCC_CR_HSERDY (17)
117 #define STM_RCC_CR_HSEON (16)
118 #define STM_RCC_CR_HSICAL (8)
119 #define STM_RCC_CR_HSITRIM (3)
120 #define STM_RCC_CR_HSIRDY (1)
121 #define STM_RCC_CR_HSION (0)
123 #define STM_RCC_PLLCFGR_PLLM 0
124 #define STM_RCC_PLLCFGR_PLLM_MASK 0x3f
125 #define STM_RCC_PLLCFGR_PLLN 6
126 #define STM_RCC_PLLCFGR_PLLN_MASK 0x1ff
127 #define STM_RCC_PLLCFGR_PLLP 16
128 #define STM_RCC_PLLCFGR_PLLP_DIV_2 0
129 #define STM_RCC_PLLCFGR_PLLP_DIV_4 1
130 #define STM_RCC_PLLCFGR_PLLP_DIV_6 2
131 #define STM_RCC_PLLCFGR_PLLP_DIV_8 3
132 #define STM_RCC_PLLCFGR_PLLP_MASK 0x3
133 #define STM_RCC_PLLCFGR_PLLSRC 22
134 #define STM_RCC_PLLCFGR_PLLSRC_HSI 0
135 #define STM_RCC_PLLCFGR_PLLSRC_HSE 1
136 #define STM_RCC_PLLCFGR_PLLQ 24
137 #define STM_RCC_PLLCFGR_PLLQ_MASK 0xf
138 #define STM_RCC_PLLCFGR_PLLR 28
139 #define STM_RCC_PLLCFGR_PLLR_MASK 0x7
141 #define STM_RCC_CFGR_MCO2 (30)
142 #define STM_RCC_CFGR_MCO2PRE (27)
143 #define STM_RCC_CFGR_MCO1PRE (24)
144 #define STM_RCC_CFGR_MCO1 (21)
145 #define STM_RCC_CFGR_RTCPRE (16)
147 #define STM_RCC_CFGR_PPRE2 (13)
148 #define STM_RCC_CFGR_PPRE2_DIV_1 0
149 #define STM_RCC_CFGR_PPRE2_DIV_2 4
150 #define STM_RCC_CFGR_PPRE2_DIV_4 5
151 #define STM_RCC_CFGR_PPRE2_DIV_8 6
152 #define STM_RCC_CFGR_PPRE2_DIV_16 7
153 #define STM_RCC_CFGR_PPRE2_MASK 7
155 #define STM_RCC_CFGR_PPRE1 (10)
156 #define STM_RCC_CFGR_PPRE1_DIV_1 0
157 #define STM_RCC_CFGR_PPRE1_DIV_2 4
158 #define STM_RCC_CFGR_PPRE1_DIV_4 5
159 #define STM_RCC_CFGR_PPRE1_DIV_8 6
160 #define STM_RCC_CFGR_PPRE1_DIV_16 7
161 #define STM_RCC_CFGR_PPRE1_MASK 7
163 #define STM_RCC_CFGR_HPRE (4)
164 #define STM_RCC_CFGR_HPRE_DIV_1 0x0
165 #define STM_RCC_CFGR_HPRE_DIV_2 0x8
166 #define STM_RCC_CFGR_HPRE_DIV_4 0x9
167 #define STM_RCC_CFGR_HPRE_DIV_8 0xa
168 #define STM_RCC_CFGR_HPRE_DIV_16 0xb
169 #define STM_RCC_CFGR_HPRE_DIV_64 0xc
170 #define STM_RCC_CFGR_HPRE_DIV_128 0xd
171 #define STM_RCC_CFGR_HPRE_DIV_256 0xe
172 #define STM_RCC_CFGR_HPRE_DIV_512 0xf
173 #define STM_RCC_CFGR_HPRE_MASK 0xf
175 #define STM_RCC_CFGR_SWS (2)
176 #define STM_RCC_CFGR_SWS_HSI 0
177 #define STM_RCC_CFGR_SWS_HSE 1
178 #define STM_RCC_CFGR_SWS_PLL 2
179 #define STM_RCC_CFGR_SWS_MASK 3
181 #define STM_RCC_CFGR_SW (0)
182 #define STM_RCC_CFGR_SW_HSI 0
183 #define STM_RCC_CFGR_SW_HSE 1
184 #define STM_RCC_CFGR_SW_PLL 2
185 #define STM_RCC_CFGR_SW_MASK 3
187 #define STM_RCC_AHB1ENR_IOPAEN 0
188 #define STM_RCC_AHB1ENR_IOPBEN 1
189 #define STM_RCC_AHB1ENR_IOPCEN 2
190 #define STM_RCC_AHB1ENR_IOPDEN 3
191 #define STM_RCC_AHB1ENR_IOPEEN 4
192 #define STM_RCC_AHB1ENR_IOPFEN 5
193 #define STM_RCC_AHB1ENR_IOPGEN 6
194 #define STM_RCC_AHB1ENR_IOPHEN 7
196 #define STM_RCC_AHB2ENR_OTGFSEN 7
197 #define STM_RCC_AHB2ENR_RNGEN 6
198 #define STM_RCC_AHB2ENR_CRYPEN 4
200 #define STM_RCC_APB1ENR_UART8EN 31
201 #define STM_RCC_APB1ENR_UART7EN 30
202 #define STM_RCC_APB1ENR_DACEN 29
203 #define STM_RCC_APB1ENR_PWREN 28
204 #define STM_RCC_APB1ENR_CAN3EN 27
205 #define STM_RCC_APB1ENR_CAN2EN 26
206 #define STM_RCC_APB1ENR_CAN1EN 25
207 #define STM_RCC_APB1ENR_I2CFMP1EN 24
208 #define STM_RCC_APB1ENR_I2C3EN 23
209 #define STM_RCC_APB1ENR_I2C2EN 22
210 #define STM_RCC_APB1ENR_I2C1EN 21
211 #define STM_RCC_APB1ENR_UART5EN 20
212 #define STM_RCC_APB1ENR_UART4EN 19
213 #define STM_RCC_APB1ENR_USART3EN 18
214 #define STM_RCC_APB1ENR_USART2EN 17
215 #define STM_RCC_APB1ENR_SPI3EN 15
216 #define STM_RCC_APB1ENR_SPI2EN 14
217 #define STM_RCC_APB1ENR_WWDGEN 11
218 #define STM_RCC_APB1ENR_RTCAPBEN 10
219 #define STM_RCC_APB1ENR_LPTIMER1EN 9
220 #define STM_RCC_APB1ENR_TIM14EN 8
221 #define STM_RCC_APB1ENR_TIM13EN 7
222 #define STM_RCC_APB1ENR_TIM12EN 6
223 #define STM_RCC_APB1ENR_TIM7EN 5
224 #define STM_RCC_APB1ENR_TIM6EN 4
225 #define STM_RCC_APB1ENR_TIM5EN 3
226 #define STM_RCC_APB1ENR_TIM4EN 2
227 #define STM_RCC_APB1ENR_TIM3EN 1
228 #define STM_RCC_APB1ENR_TIM2EN 0
230 #define STM_RCC_APB2ENR_DFSDM2EN 25
231 #define STM_RCC_APB2ENR_DFSDM1EN 24
232 #define STM_RCC_APB2ENR_SAI1EN 22
233 #define STM_RCC_APB2ENR_SPI5EN 20
234 #define STM_RCC_APB2ENR_TIM11EN 18
235 #define STM_RCC_APB2ENR_TIM10EN 17
236 #define STM_RCC_APB2ENR_TIM9EN 16
237 #define STM_RCC_APB2ENR_EXITEN 15
238 #define STM_RCC_APB2ENR_SYSCFGEN 14
239 #define STM_RCC_APB2ENR_SPI4EN 13
240 #define STM_RCC_APB2ENR_SPI1EN 12
241 #define STM_RCC_APB2ENR_SDIOEN 11
242 #define STM_RCC_APB2ENR_ADC1EN 8
243 #define STM_RCC_APB2ENR_UART10EN 7
244 #define STM_RCC_APB2ENR_UART9EN 5
245 #define STM_RCC_APB2ENR_USART6EN 5
246 #define STM_RCC_APB2ENR_USART1EN 4
247 #define STM_RCC_APB2ENR_TIM8EN 1
248 #define STM_RCC_APB2ENR_TIM1EN 0
250 #define STM_RCC_CSR_RMVF 24
252 #define STM_RCC_DCKCFGR_CKDFSDMSEL 31
253 #define STM_RCC_DCKCFGR_I2S2SRC 27
254 #define STM_RCC_DCKCFGR_I2S1SRC 25
255 #define STM_RCC_DCKCFGR_TIMPRE 24
256 #define STM_RCC_DCKCFGR_SAII1BSRC 22
257 #define STM_RCC_DCKCFGR_SAII1ASRC 20
258 #define STM_RCC_DCKCFGR_CKDFSDM1ASEL 15
259 #define STM_RCC_DCKCFGR_CKDFSDM2ASEL 14
260 #define STM_RCC_DCKCFGR_PLLDIVR 8
261 #define STM_RCC_DCKCFGR_PLLI2SDIVR 0
263 #define STM_RCC_DCKCFGR2_LPTIMER1SEL 30
264 #define STM_RCC_DCKCFGR2_LPTIMER1SEL_APB 0
265 #define STM_RCC_DCKCFGR2_LPTIMER1SEL_HSI 1
266 #define STM_RCC_DCKCFGR2_LPTIMER1SEL_LSI 2
267 #define STM_RCC_DCKCFGR2_LPTIMER1SEL_LSE 3
268 #define STM_RCC_DCKCFGR2_SDIOSEL 28
269 #define STM_RCC_DCKCFGR2_SDIOSEL_CK_48MHZ 0
270 #define STM_RCC_DCKCFGR2_SDIOSEL_SYSTEM_CLOCK 1
271 #define STM_RCC_DCKCFGR2_CK48MSEL 27
272 #define STM_RCC_DCKCFGR2_CK48MSEL_PLL_Q 1
273 #define STM_RCC_DCKCFGR2_CK48MSEL_PLLI2S_Q 1
274 #define STM_RCC_DCKCFGR2_I2CFMP1SEL 22
275 #define STM_RCC_DCKCFGR2_I2CFMP1SEL_APB 0
276 #define STM_RCC_DCKCFGR2_I2CFMP1SEL_SYSTEM_CLOCK 1
277 #define STM_RCC_DCKCFGR2_I2CFMP1SEL_HSI 2
278 #define STM_RCC_DCKCFGR2_I2CFMP1SEL_APB_ALSO 3
284 extern struct stm_ictr stm_ictr;
286 #define stm_ictr (*((struct stm_ictr *) 0xe000e004))
288 #define STM_ICTR_ICTR_INTLINESNUM 0
289 #define STM_ICTR_ICTR_INTLINESNUM_MASK 0xf
292 vuint32_t iser[8]; /* 0x000 0xe000e100 Set Enable Register */
294 uint8_t _unused020[0x080 - 0x020];
296 vuint32_t icer[8]; /* 0x080 0xe000e180 Clear Enable Register */
298 uint8_t _unused0a0[0x100 - 0x0a0];
300 vuint32_t ispr[8]; /* 0x100 0xe000e200 Set Pending Register */
302 uint8_t _unused120[0x180 - 0x120];
304 vuint32_t icpr[8]; /* 0x180 0xe000e280 Clear Pending Register */
306 uint8_t _unused1a0[0x200 - 0x1a0];
308 vuint32_t iabr[8]; /* 0x200 0xe000e300 Active Bit Register */
310 uint8_t _unused220[0x300 - 0x220];
312 vuint32_t ipr[60]; /* 0x300 0xe000e400 Priority Register */
315 extern struct stm_nvic stm_nvic;
317 #define stm_nvic (*((struct stm_nvic *) 0xe000e100))
319 #define IRQ_REG(irq) ((irq) >> 5)
320 #define IRQ_BIT(irq) ((irq) & 0x1f)
321 #define IRQ_MASK(irq) (1 << IRQ_BIT(irq))
322 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
325 stm_nvic_set_enable(int irq) {
326 stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
330 stm_nvic_clear_enable(int irq) {
331 stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
335 stm_nvic_enabled(int irq) {
336 return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
340 stm_nvic_set_pending(int irq) {
341 stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
345 stm_nvic_clear_pending(int irq) {
346 stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
350 stm_nvic_pending(int irq) {
351 return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
355 stm_nvic_active(int irq) {
356 return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
359 #define IRQ_PRIO_REG(irq) ((irq) >> 2)
360 #define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3)
361 #define IRQ_PRIO_MASK(irq) (0xff << IRQ_PRIO_BIT(irq))
364 stm_nvic_set_priority(int irq, uint8_t prio) {
365 int n = IRQ_PRIO_REG(irq);
369 v &= ~IRQ_PRIO_MASK(irq);
370 v |= (prio) << IRQ_PRIO_BIT(irq);
374 static inline uint8_t
375 stm_nvic_get_priority(int irq) {
376 return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
379 #define isr(name) void stm_ ## name ## _isr(void)
416 isr(tim_trg_com_tim11);
435 isr(tim8_trg_com_tim14);
489 #define STM_ISR_WWDG_POS 0
490 #define STM_ISR_PVD_POS 1
491 #define STM_ISR_TAMPER_STAMP_POS 2
492 #define STM_ISR_RTC_WKUP_POS 3
493 #define STM_ISR_FLASH_POS 4
494 #define STM_ISR_RCC_POS 5
495 #define STM_ISR_EXTI0_POS 6
496 #define STM_ISR_EXTI1_POS 7
497 #define STM_ISR_EXTI2_POS 8
498 #define STM_ISR_EXTI3_POS 9
499 #define STM_ISR_EXTI4_POS 10
500 #define STM_ISR_DMA1_STREAM0_POS 11
501 #define STM_ISR_DMA1_STREAM1_POS 12
502 #define STM_ISR_DMA1_STREAM2_POS 13
503 #define STM_ISR_DMA1_STREAM3_POS 14
504 #define STM_ISR_DMA1_STREAM4_POS 15
505 #define STM_ISR_DMA1_STREAM5_POS 16
506 #define STM_ISR_DMA1_STREAM6_POS 17
507 #define STM_ISR_ADC_POS 18
508 #define STM_ISR_CAN1_TX_POS 19
509 #define STM_ISR_CAN1_RX0_POS 20
510 #define STM_ISR_CAN1_RX1_POS 21
511 #define STM_ISR_CAN1_SCE_POS 22
512 #define STM_ISR_EXTI9_5_POS 23
513 #define STM_ISR_TIM1_BRK_TIM9_POS 24
514 #define STM_ISR_TIM1_UP_TIM10_POS 25
515 #define STM_ISR_TIM_TRG_COM_TIM11_POS 26
516 #define STM_ISR_TIM1_CC_POS 27
517 #define STM_ISR_TIM2_POS 28
518 #define STM_ISR_TIM3_POS 29
519 #define STM_ISR_TIM4_POS 30
520 #define STM_ISR_I2C1_EVT_POS 31
521 #define STM_ISR_I2C1_ERR_POS 32
522 #define STM_ISR_I2C2_EVT_POS 33
523 #define STM_ISR_I2C2_ERR_POS 34
524 #define STM_ISR_SPI1_POS 35
525 #define STM_ISR_SPI2_POS 36
526 #define STM_ISR_USART1_POS 37
527 #define STM_ISR_USART2_POS 38
528 #define STM_ISR_USART3_POS 39
529 #define STM_ISR_EXTI15_10_POS 40
530 #define STM_ISR_EXTI17_RTC_ALARM_POS 41
531 #define STM_ISR_EXTI18_OTG_FS_WKUP_POS 42
532 #define STM_ISR_TIM2_BRK_TIM12_POS 43
533 #define STM_ISR_TIM8_UP_TIM13_POS 44
534 #define STM_ISR_TIM8_TRG_COM_TIM14_POS 45
535 #define STM_ISR_TIM8_CC_POS 46
536 #define STM_ISR_DMA1_STREAM7_POS 47
537 #define STM_ISR_FSMC_POS 48
538 #define STM_ISR_SDIO_POS 49
539 #define STM_ISR_TIM5_POS 50
540 #define STM_ISR_SPI3_POS 41
541 #define STM_ISR_UART4_POS 52
542 #define STM_ISR_UART5_POS 53
543 #define STM_ISR_TIM6_GLB_IT_DAC1_DAC2_POS 54
544 #define STM_ISR_TIM7_POS 55
545 #define STM_ISR_DMA2_STREAM0_POS 56
546 #define STM_ISR_DMA2_STREAM1_POS 57
547 #define STM_ISR_DMA2_STREAM2_POS 58
548 #define STM_ISR_DMA2_STREAM3_POS 59
549 #define STM_ISR_DMA2_STREAM4_POS 60
550 #define STM_ISR_DFSDM1_FLT0_POS 61
551 #define STM_ISR_DFSDM1_FLT1_POS 62
552 #define STM_ISR_CAN2_TX_POS 63
553 #define STM_ISR_CAN2_RX0_POS 64
554 #define STM_ISR_CAN2_RX1_POS 65
555 #define STM_ISR_CAN2_SCE_POS 66
556 #define STM_ISR_OTG_FS_POS 67
557 #define STM_ISR_DMA2_STREAM5_POS 68
558 #define STM_ISR_DMA2_STREAM6_POS 69
559 #define STM_ISR_DMA2_STREAM7_POS 70
560 #define STM_ISR_USART6_POS 71
561 #define STM_ISR_UART7_POS 82
562 #define STM_ISR_UART9_POS 88
563 #define STM_ISR_UART10_POS 89
565 #define STM_ISR_EXTI15_10_POS 40
578 extern struct stm_flash stm_flash;
580 #define stm_flash (*((struct stm_flash *) 0x40023c00))
582 #define STM_FLASH_ACR_DCRST 12
583 #define STM_FLASH_ACR_ICRST 11
584 #define STM_FLASH_ACR_DCEN 10
585 #define STM_FLASH_ACR_ICEN 9
586 #define STM_FLASH_ACR_PRFTEN 8
587 #define STM_FLASH_ACR_LATENCY 0
589 struct stm_flash_size {
593 extern struct stm_flash_size stm_flash_size;
595 #define stm_flash_size (*((struct stm_flash_size *) 0x1fff7a22))
612 #define STM_MODER_SHIFT(pin) ((pin) << 1)
613 #define STM_MODER_MASK 3
614 #define STM_MODER_INPUT 0
615 #define STM_MODER_OUTPUT 1
616 #define STM_MODER_ALTERNATE 2
617 #define STM_MODER_ANALOG 3
620 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
621 gpio->moder = ((gpio->moder &
622 ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
623 value << STM_MODER_SHIFT(pin));
626 static inline uint32_t
627 stm_moder_get(struct stm_gpio *gpio, int pin) {
628 return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
631 #define STM_OTYPER_SHIFT(pin) (pin)
632 #define STM_OTYPER_MASK 1
633 #define STM_OTYPER_PUSH_PULL 0
634 #define STM_OTYPER_OPEN_DRAIN 1
637 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
638 gpio->otyper = ((gpio->otyper &
639 ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
640 value << STM_OTYPER_SHIFT(pin));
643 static inline uint32_t
644 stm_otyper_get(struct stm_gpio *gpio, int pin) {
645 return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
648 #define STM_OSPEEDR_SHIFT(pin) ((pin) << 1)
649 #define STM_OSPEEDR_MASK 3
650 #define STM_OSPEEDR_LOW 0 /* 2-8MHz */
651 #define STM_OSPEEDR_MEDIUM 1 /* 12.5-50MHz */
652 #define STM_OSPEEDR_FAST 2 /* 25-100MHz */
653 #define STM_OSPEEDR_HIGH 3 /* 50-100MHz */
656 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
657 gpio->ospeedr = ((gpio->ospeedr &
658 ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
659 value << STM_OSPEEDR_SHIFT(pin));
662 static inline uint32_t
663 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
664 return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
667 #define STM_PUPDR_SHIFT(pin) ((pin) << 1)
668 #define STM_PUPDR_MASK 3
669 #define STM_PUPDR_NONE 0
670 #define STM_PUPDR_PULL_UP 1
671 #define STM_PUPDR_PULL_DOWN 2
672 #define STM_PUPDR_RESERVED 3
675 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
676 gpio->pupdr = ((gpio->pupdr &
677 ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
678 value << STM_PUPDR_SHIFT(pin));
681 static inline uint32_t
682 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
683 return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
686 #define STM_AFR_SHIFT(pin) ((pin) << 2)
687 #define STM_AFR_MASK 0xf
688 #define STM_AFR_NONE 0
689 #define STM_AFR_AF0 0x0
690 #define STM_AFR_AF1 0x1
691 #define STM_AFR_AF2 0x2
692 #define STM_AFR_AF3 0x3
693 #define STM_AFR_AF4 0x4
694 #define STM_AFR_AF5 0x5
695 #define STM_AFR_AF6 0x6
696 #define STM_AFR_AF7 0x7
697 #define STM_AFR_AF8 0x8
698 #define STM_AFR_AF9 0x9
699 #define STM_AFR_AF10 0xa
700 #define STM_AFR_AF11 0xb
701 #define STM_AFR_AF12 0xc
702 #define STM_AFR_AF13 0xd
703 #define STM_AFR_AF14 0xe
704 #define STM_AFR_AF15 0xf
707 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
709 * Set alternate pin mode too
711 stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
713 gpio->afrl = ((gpio->afrl &
714 ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
715 value << STM_AFR_SHIFT(pin));
718 gpio->afrh = ((gpio->afrh &
719 ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
720 value << STM_AFR_SHIFT(pin));
724 static inline uint32_t
725 stm_afr_get(struct stm_gpio *gpio, int pin) {
727 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
730 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
735 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
736 /* Use the bit set/reset register to do this atomically */
737 gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
740 static inline uint8_t
741 stm_gpio_get(struct stm_gpio *gpio, int pin) {
742 return (gpio->idr >> pin) & 1;
745 static inline uint16_t
746 stm_gpio_get_all(struct stm_gpio *gpio) {
751 * We can't define these in registers.ld or our fancy
752 * ao_enable_gpio macro will expand into a huge pile of code
753 * as the compiler won't do correct constant folding and
754 * dead-code elimination
757 extern struct stm_gpio stm_gpioa;
758 extern struct stm_gpio stm_gpiob;
759 extern struct stm_gpio stm_gpioc;
760 extern struct stm_gpio stm_gpiod;
761 extern struct stm_gpio stm_gpioe;
762 extern struct stm_gpio stm_gpiof;
763 extern struct stm_gpio stm_gpiog;
764 extern struct stm_gpio stm_gpioh;
766 #define stm_gpioa (*((struct stm_gpio *) 0x40020000))
767 #define stm_gpiob (*((struct stm_gpio *) 0x40020400))
768 #define stm_gpioc (*((struct stm_gpio *) 0x40020800))
769 #define stm_gpiod (*((struct stm_gpio *) 0x40020c00))
770 #define stm_gpioe (*((struct stm_gpio *) 0x40021000))
771 #define stm_gpiof (*((struct stm_gpio *) 0x40021400))
772 #define stm_gpiog (*((struct stm_gpio *) 0x40021800))
773 #define stm_gpioh (*((struct stm_gpio *) 0x40021c00))
821 vuint8_t pad_d90[0xf00 - 0xd90];
826 extern struct stm_scb stm_scb;
828 #define stm_scb (*((struct stm_scb *) 0xe000ed00))
830 #define STM_SCB_CPACR_CP(n) ((n) <<1)
831 #define STM_SCB_CPACR_DENIED 0
832 #define STM_SCB_CPACR_PRIVILEGED 1
833 #define STM_SCB_CPACR_RESERVED 2
834 #define STM_SCB_CPACR_FULL 3
835 #define STM_SCB_CPACR_FP0 STM_SCB_CPACR_CP(10)
836 #define STM_SCB_CPACR_FP1 STM_SCB_CPACR_CP(11)
838 #define STM_SCB_AIRCR_VECTKEY 16
839 #define STM_SCB_AIRCR_VECTKEY_KEY 0x05fa
840 #define STM_SCB_AIRCR_PRIGROUP 8
841 #define STM_SCB_AIRCR_SYSRESETREQ 2
842 #define STM_SCB_AIRCR_VECTCLRACTIVE 1
843 #define STM_SCB_AIRCR_VECTRESET 0
845 /* The SYSTICK starts at 0xe000e010 */
854 extern struct stm_systick stm_systick;
856 #define stm_systick (*((struct stm_systick *) 0xe000e010))
858 #define STM_SYSTICK_CSR_ENABLE 0
859 #define STM_SYSTICK_CSR_TICKINT 1
860 #define STM_SYSTICK_CSR_CLKSOURCE 2
861 #define STM_SYSTICK_CSR_CLKSOURCE_AHB_8 0
862 #define STM_SYSTICK_CSR_CLKSOURCE_AHB 1
863 #define STM_SYSTICK_CSR_COUNTFLAG 16
865 #define STM_SYSCFG_EXTICR_PA 0
866 #define STM_SYSCFG_EXTICR_PB 1
867 #define STM_SYSCFG_EXTICR_PC 2
868 #define STM_SYSCFG_EXTICR_PD 3
869 #define STM_SYSCFG_EXTICR_PE 4
870 #define STM_SYSCFG_EXTICR_PF 5
871 #define STM_SYSCFG_EXTICR_PG 6
872 #define STM_SYSCFG_EXTICR_PH 7
880 extern struct stm_syscfg stm_syscfg;
882 #define stm_syscfg (*((struct stm_syscfg *) 0x40013800))
884 #define STM_SYSCFG_MEMRMP_MEM_MODE 0
885 #define STM_SYSCFG_MEMRMP_MEM_MODE_MAIN_FLASH 0
886 #define STM_SYSCFG_MEMRMP_MEM_MODE_SYSTEM_FLASH 1
887 #define STM_SYSCFG_MEMRMP_MEM_MODE_SRAM 3
888 #define STM_SYSCFG_MEMRMP_MEM_MODE_MASK 3
890 #define STM_SYSCFG_PMC_ADC1DC2 0
893 stm_exticr_set(struct stm_gpio *gpio, int pin) {
894 uint8_t reg = pin >> 2;
895 uint8_t shift = (pin & 3) << 2;
899 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN);
901 if (gpio == &stm_gpioa)
902 val = STM_SYSCFG_EXTICR_PA;
903 else if (gpio == &stm_gpiob)
904 val = STM_SYSCFG_EXTICR_PB;
905 else if (gpio == &stm_gpioc)
906 val = STM_SYSCFG_EXTICR_PC;
907 else if (gpio == &stm_gpiod)
908 val = STM_SYSCFG_EXTICR_PD;
909 else if (gpio == &stm_gpioe)
910 val = STM_SYSCFG_EXTICR_PE;
911 else if (gpio == &stm_gpiof)
912 val = STM_SYSCFG_EXTICR_PF;
913 else if (gpio == &stm_gpiog)
914 val = STM_SYSCFG_EXTICR_PG;
915 else if (gpio == &stm_gpioh)
916 val = STM_SYSCFG_EXTICR_PH;
918 stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
931 extern struct stm_exti stm_exti;
933 #define stm_exti (*((struct stm_exti *) 0x40013c00))
936 vuint32_t sr; /* status register */
937 vuint32_t dr; /* data register */
938 vuint32_t brr; /* baud rate register */
939 vuint32_t cr1; /* control register 1 */
941 vuint32_t cr2; /* control register 2 */
942 vuint32_t cr3; /* control register 3 */
943 vuint32_t gtpr; /* guard time and prescaler */
946 extern struct stm_usart stm_usart6;
948 #define stm_usart6 (*((struct stm_usart *) 0x40011400))
950 #define STM_USART_SR_CTS (9) /* CTS flag */
951 #define STM_USART_SR_LBD (8) /* LIN break detection flag */
952 #define STM_USART_SR_TXE (7) /* Transmit data register empty */
953 #define STM_USART_SR_TC (6) /* Transmission complete */
954 #define STM_USART_SR_RXNE (5) /* Read data register not empty */
955 #define STM_USART_SR_IDLE (4) /* IDLE line detected */
956 #define STM_USART_SR_ORE (3) /* Overrun error */
957 #define STM_USART_SR_NF (2) /* Noise detected flag */
958 #define STM_USART_SR_FE (1) /* Framing error */
959 #define STM_USART_SR_PE (0) /* Parity error */
961 #define STM_USART_CR1_OVER8 (15) /* Oversampling mode */
962 #define STM_USART_CR1_UE (13) /* USART enable */
963 #define STM_USART_CR1_M (12) /* Word length */
964 #define STM_USART_CR1_WAKE (11) /* Wakeup method */
965 #define STM_USART_CR1_PCE (10) /* Parity control enable */
966 #define STM_USART_CR1_PS (9) /* Parity selection */
967 #define STM_USART_CR1_PEIE (8) /* PE interrupt enable */
968 #define STM_USART_CR1_TXEIE (7) /* TXE interrupt enable */
969 #define STM_USART_CR1_TCIE (6) /* Transmission complete interrupt enable */
970 #define STM_USART_CR1_RXNEIE (5) /* RXNE interrupt enable */
971 #define STM_USART_CR1_IDLEIE (4) /* IDLE interrupt enable */
972 #define STM_USART_CR1_TE (3) /* Transmitter enable */
973 #define STM_USART_CR1_RE (2) /* Receiver enable */
974 #define STM_USART_CR1_RWU (1) /* Receiver wakeup */
975 #define STM_USART_CR1_SBK (0) /* Send break */
977 #define STM_USART_CR2_LINEN (14) /* LIN mode enable */
978 #define STM_USART_CR2_STOP (12) /* STOP bits */
979 #define STM_USART_CR2_STOP_MASK 3
980 #define STM_USART_CR2_STOP_1 0
981 #define STM_USART_CR2_STOP_0_5 1
982 #define STM_USART_CR2_STOP_2 2
983 #define STM_USART_CR2_STOP_1_5 3
985 #define STM_USART_CR2_CLKEN (11) /* Clock enable */
986 #define STM_USART_CR2_CPOL (10) /* Clock polarity */
987 #define STM_USART_CR2_CPHA (9) /* Clock phase */
988 #define STM_USART_CR2_LBCL (8) /* Last bit clock pulse */
989 #define STM_USART_CR2_LBDIE (6) /* LIN break detection interrupt enable */
990 #define STM_USART_CR2_LBDL (5) /* lin break detection length */
991 #define STM_USART_CR2_ADD (0)
992 #define STM_USART_CR2_ADD_MASK 0xf
994 #define STM_USART_CR3_ONEBIT (11) /* One sample bit method enable */
995 #define STM_USART_CR3_CTSIE (10) /* CTS interrupt enable */
996 #define STM_USART_CR3_CTSE (9) /* CTS enable */
997 #define STM_USART_CR3_RTSE (8) /* RTS enable */
998 #define STM_USART_CR3_DMAT (7) /* DMA enable transmitter */
999 #define STM_USART_CR3_DMAR (6) /* DMA enable receiver */
1000 #define STM_USART_CR3_SCEN (5) /* Smartcard mode enable */
1001 #define STM_USART_CR3_NACK (4) /* Smartcard NACK enable */
1002 #define STM_USART_CR3_HDSEL (3) /* Half-duplex selection */
1003 #define STM_USART_CR3_IRLP (2) /* IrDA low-power */
1004 #define STM_USART_CR3_IREN (1) /* IrDA mode enable */
1005 #define STM_USART_CR3_EIE (0) /* Error interrupt enable */
1032 vuint32_t ghwcfg3; /* not in docs? */
1037 vuint32_t gdfifocfg; /* not in docs? */
1039 uint8_t pad_60[0x100 - 0x60];
1041 vuint32_t hptxfsiz; /* 0x100 */
1042 vuint32_t dieptxf[0xf]; /* 0x104 5 in docs? */
1044 uint8_t pad_140[0x400 - 0x140];
1056 uint8_t pad_420[0x440-0x420];
1060 uint8_t pad_444[0x500 - 0x444];
1065 vuint32_t hcintmsk0;
1084 uint8_t pad_680[0x800 - 0x680];
1099 vuint32_t dvbuspulse;
1102 vuint32_t diepempmsk;
1104 uint8_t pad_838[0x900 - 0x838];
1118 uint8_t pad_9c0[0xb00 - 0x9c0];
1132 uint8_t pad_bc0[0xe00 - 0xbc0];
1136 uint8_t pad_e04[0x1000 - 0xe04];
1140 uint8_t pad_004[0x1000 - 0x004];
1144 extern struct stm_usb stm_usb;
1146 #define stm_usb (*((struct stm_usb *) 0x50000000))
1148 #define STM_USB_GOTGCTL_CURMOD 21
1149 #define STM_USB_GOTGCTL_OTGVER 20
1150 #define STM_USB_GOTGCTL_BSVLD 19
1151 #define STM_USB_GOTGCTL_ASVLD 18
1152 #define STM_USB_GOTGCTL_DBCT 17
1153 #define STM_USB_GOTGCTL_CIDSTS 16
1154 #define STM_USB_GOTGCTL_EHEN 12
1155 #define STM_USB_GOTGCTL_DHNPEN 11
1156 #define STM_USB_GOTGCTL_HSHNPEN 10
1157 #define STM_USB_GOTGCTL_HNPRQ 9
1158 #define STM_USB_GOTGCTL_HNGSCS 8
1159 #define STM_USB_GOTGCTL_BVALOVAL 7
1160 #define STM_USB_GOTGCTL_BVALOEN 6
1161 #define STM_USB_GOTGCTL_AVALOVAL 5
1162 #define STM_USB_GOTGCTL_AVALOEN 4
1163 #define STM_USB_GOTGCTL_VBVALOVAL 3
1164 #define STM_USB_GOTGCTL_VBVALOEN 2
1165 #define STM_USB_GOTGCTL_SRQ 1
1166 #define STM_USB_GOTGCTL_SRQSCS 0
1168 #define STM_USB_GOTGINT_IDCHNG 20
1169 #define STM_USB_GOTGINT_DBCDNE 19
1170 #define STM_USB_GOTGINT_ADTOCHG 18
1171 #define STM_USB_GOTGINT_HNGDET 17
1172 #define STM_USB_GOTGINT_HNSSCHG 9
1173 #define STM_USB_GOTGINT_SRSSCHG 8
1174 #define STM_USB_GOTGINT_SEDET 2
1176 #define STM_USB_GAHBCFG_PTXFELVL 8
1177 #define STM_USB_GAHBCFG_TXFELVL 7
1178 #define STM_USB_GAHBCFG_GINTMSK 0
1180 #define STM_USB_GUSBCFG_FDMOD 30
1181 #define STM_USB_GUSBCFG_FHMOD 29
1182 #define STM_USB_GUSBCFG_TRDT 10
1183 #define STM_USB_GUSBCFG_TRDT_MASK 0xf
1184 #define STM_USB_GUSBCFG_HNPCAP 9
1185 #define STM_USB_GUSBCFG_SRPCAP 8
1186 #define STM_USB_GUSBCFG_PHYSEL 6
1187 #define STM_USB_GUSBCFG_TOCAL 0
1188 #define STM_USB_GUSBCFG_TOCAL_MASK 0x7
1190 #define STM_USB_GRSTCTL_AHBIDL 31
1191 #define STM_USB_GRSTCTL_TXFNUM 6
1192 #define STM_USB_GRSTCTL_TXFNUM_ALL 0x10
1193 #define STM_USB_GRSTCTL_TXFNUM_MASK 0x1f
1194 #define STM_USB_GRSTCTL_TXFFLSH 5
1195 #define STM_USB_GRSTCTL_RXFFLSH 4
1196 #define STM_USB_GRSTCTL_FCRST 2
1197 #define STM_USB_GRSTCTL_PSRST 1
1198 #define STM_USB_GRSTCTL_CSRST 0
1200 #define STM_USB_GINTSTS_WKUPINT 31
1201 #define STM_USB_GINTSTS_SRQINT 30
1202 #define STM_USB_GINTSTS_DISCINT 29
1203 #define STM_USB_GINTSTS_CIDSCHG 28
1204 #define STM_USB_GINTSTS_LPMINT 27
1205 #define STM_USB_GINTSTS_PTXFE 26
1206 #define STM_USB_GINTSTS_HCINT 25
1207 #define STM_USB_GINTSTS_HPRTINT 24
1208 #define STM_USB_GINTSTS_RSTDET 23
1209 #define STM_USB_GINTSTS_IPXFER 21
1210 #define STM_USB_GINTSTS_IISOIXFR 20
1211 #define STM_USB_GINTSTS_OEPINT 19
1212 #define STM_USB_GINTSTS_IEPINT 18
1213 #define STM_USB_GINTSTS_EOPF 15
1214 #define STM_USB_GINTSTS_ISOODRP 14
1215 #define STM_USB_GINTSTS_ENUMDNE 13
1216 #define STM_USB_GINTSTS_USBRST 12
1217 #define STM_USB_GINTSTS_USBSUSP 11
1218 #define STM_USB_GINTSTS_ESUSP 10
1219 #define STM_USB_GINTSTS_GONAKEFF 7
1220 #define STM_USB_GINTSTS_GINAKEFF 6
1221 #define STM_USB_GINTSTS_NPTXFE 5
1222 #define STM_USB_GINTSTS_RXFLVL 4
1223 #define STM_USB_GINTSTS_SOF 3
1224 #define STM_USB_GINTSTS_OTGINT 2
1225 #define STM_USB_GINTSTS_MMIS 1
1226 #define STM_USB_GINTSTS_CMOD 0
1228 #define STM_USB_GINTMSK_WUIM 31
1229 #define STM_USB_GINTMSK_SRQIM 30
1230 #define STM_USB_GINTMSK_DISCINT 29
1231 #define STM_USB_GINTMSK_CIDSCHGM 28
1232 #define STM_USB_GINTMSK_LPMINTM 27
1233 #define STM_USB_GINTMSK_PTXFEM 26
1234 #define STM_USB_GINTMSK_HCIM 25
1235 #define STM_USB_GINTMSK_PRTIM 24
1236 #define STM_USB_GINTMSK_RSTDETM 23
1237 #define STM_USB_GINTMSK_IPXFERM 21 /* host mode */
1238 #define STM_USB_GINTMSK_IISOOXFRM 21 /* device mode */
1239 #define STM_USB_GINTMSK_IISOIXFRM 20
1240 #define STM_USB_GINTMSK_OEPINT 19
1241 #define STM_USB_GINTMSK_IEPINT 18
1242 #define STM_USB_GINTMSK_EOPFM 15
1243 #define STM_USB_GINTMSK_ISOODRPM 14
1244 #define STM_USB_GINTMSK_ENUMDNEM 13
1245 #define STM_USB_GINTMSK_USBRST 12
1246 #define STM_USB_GINTMSK_USBSUSPM 11
1247 #define STM_USB_GINTMSK_ESUSPM 10
1248 #define STM_USB_GINTMSK_GONAKEFFM 7
1249 #define STM_USB_GINTMSK_GINAKEFFM 6
1250 #define STM_USB_GINTMSK_NPTXFEM 5
1251 #define STM_USB_GINTMSK_RXFLVLM 4
1252 #define STM_USB_GINTMSK_SOFM 3
1253 #define STM_USB_GINTMSK_OTGINT 2
1254 #define STM_USB_GINTMSK_MMISM 1
1256 #define STM_USB_GRXSTSP_STSPHST 27
1257 #define STM_USB_GRXSTSP_FRMNUM 21
1258 #define STM_USB_GRXSTSP_FRMNUM_MASK 0xf
1259 #define STM_USB_GRXSTSP_PKTSTS 17
1260 #define STM_USB_GRXSTSP_PKTSTS_NAK 1
1261 #define STM_USB_GRXSTSP_PKTSTS_OUT_DATA 2
1262 #define STM_USB_GRXSTSP_PKTSTS_OUT_COMPLETE 3
1263 #define STM_USB_GRXSTSP_PKTSTS_SETUP_COMPLETE 4
1264 #define STM_USB_GRXSTSP_PKTSTS_SETUP_DATA 5
1265 #define STM_USB_GRXSTSP_PKTSTS_MASK 0xf
1266 #define STM_USB_GRXSTSP_DPID 15
1267 #define STM_USB_GRXSTSP_DPID_MASK 3
1268 #define STM_USB_GRXSTSP_BCNT 4
1269 #define STM_USB_GRXSTSP_BCNT 4
1270 #define STM_USB_GRXSTSP_BCNT_MASK 0x3ff
1271 #define STM_USB_GRXSTSP_EPNUM 0
1272 #define STM_USB_GRXSTSP_EPNUM_MASK 0xf
1274 #define STM_USB_GRXFSIZ_RXFD 0
1275 #define STM_USB_GRXFSIZ_RXFD_MASK 0xffff
1277 #define STM_USB_GCCFG_VBDEN 21
1278 #define STM_USB_GCCFG_SDEN 20
1279 #define STM_USB_GCCFG_PDEN 19
1280 #define STM_USB_GCCFG_DCDEN 18
1281 #define STM_USB_GCCFG_BCDEN 17
1282 #define STM_USB_GCCFG_PWRDWN 16
1283 #define STM_USB_GCCFG_PS2DET 3
1284 #define STM_USB_GCCFG_SDET 2
1285 #define STM_USB_GCCFG_PDET 1
1286 #define STM_USB_GCCFG_DCDET 0
1288 #define STM_USB_DIEPTXF0_TX0FD 16
1289 #define STM_USB_DIEPTXF0_TX0FSA 0
1291 #define STM_USB_DCFG_ERRATIM 15
1292 #define STM_USB_DCFG_PFIVL 11
1293 #define STM_USB_DCFG_PFIVL_80 0
1294 #define STM_USB_DCFG_PFIVL_85 1
1295 #define STM_USB_DCFG_PFIVL_90 2
1296 #define STM_USB_DCFG_PFIVL_95 3
1297 #define STM_USB_DCFG_PFIVL_MASK 3
1298 #define STM_USB_DCFG_DAD 4
1299 #define STM_USB_DCFG_DAD_MASK 0x7f
1300 #define STM_USB_DCFG_NZLSOHSK 2
1301 #define STM_USB_DCFG_DSPD 0
1302 #define STM_USB_DCFG_DSPD_FULL_SPEED 3
1303 #define STM_USB_DCFG_DSPD_MASK 3
1304 #define STM_USB_DCFG_
1305 #define STM_USB_DCFG_
1306 #define STM_USB_DCFG_
1307 #define STM_USB_DCFG_
1308 #define STM_USB_DCFG_
1309 #define STM_USB_DCFG_
1310 #define STM_USB_DCFG_
1312 #define STM_USB_DCTL_DSBESLRJCT 18
1313 #define STM_USB_DCTL_POPRGDNE 11
1314 #define STM_USB_DCTL_CGONAK 10
1315 #define STM_USB_DCTL_SGONAK 9
1316 #define STM_USB_DCTL_CGINAK 8
1317 #define STM_USB_DCTL_SGINAK 7
1318 #define STM_USB_DCTL_TCTL 4
1319 #define STM_USB_DCTL_GONSTS 3
1320 #define STM_USB_DCTL_GINSTS 2
1321 #define STM_USB_DCTL_SDIS 1
1322 #define STM_USB_DCTL_RWUSIG 0
1324 #define STM_USB_DSTS_DEVLNSTS 22
1325 #define STM_USB_DSTS_DEVLNSTS_MASK 0x3
1326 #define STM_USB_DSTS_FNSOF 8
1327 #define STM_USB_DSTS_FNSOF_MASK 0x3fff
1328 #define STM_USB_DSTS_EERR 3
1329 #define STM_USB_DSTS_ENUMSPD 1
1330 #define STM_USB_DSTS_ENUMSPD_MASK 3
1331 #define STM_USB_DSTS_SUSPSTS 0
1333 #define STM_USB_DIEPMSK_NAKM 13
1334 #define STM_USB_DIEPMSK_TXFURM 8
1335 #define STM_USB_DIEPMSK_INEPNEM 6
1336 #define STM_USB_DIEPMSK_INEPNMM 5
1337 #define STM_USB_DIEPMSK_ITTXFEMSK 4
1338 #define STM_USB_DIEPMSK_TOM 3
1339 #define STM_USB_DIEPMSK_EPDM 1
1340 #define STM_USB_DIEPMSK_XFRCM 0
1342 #define STM_USB_DOEPMSK_NYETMSK 14
1343 #define STM_USB_DOEPMSK_NAKMSK 13
1344 #define STM_USB_DOEPMSK_BERRM 12
1345 #define STM_USB_DOEPMSK_OUTPKTERRM 8
1346 #define STM_USB_DOEPMSK_STSPHSRXM 5
1347 #define STM_USB_DOEPMSK_OTEPDM 4
1348 #define STM_USB_DOEPMSK_STUPM 3
1349 #define STM_USB_DOEPMSK_EPDM 1
1350 #define STM_USB_DOEPMSK_XFRCM 0
1352 #define STM_USB_DAINT_OEPINT 16
1353 #define STM_USB_DAINT_OEPINT_MASK 0xffff
1354 #define STM_USB_DAINT_IEPINT 16
1355 #define STM_USB_DAINT_IEPINT_MASK 0xffff
1357 #define STM_USB_DAINTMSK_OEPM 16
1358 #define STM_USB_DAINTMSK_OEPM_MASK 0xffff
1359 #define STM_USB_DAINTMSK_IEPM 0
1360 #define STM_USB_DAINTMSK_IEPM_MASK 0xffff
1362 #define STM_USB_DIEPCTL_EPENA 31
1363 #define STM_USB_DIEPCTL_EPDIS 30
1364 #define STM_USB_DIEPCTL_SNAK 27
1365 #define STM_USB_DIEPCTL_CNAK 26
1366 #define STM_USB_DIEPCTL_TXFNUM 22
1367 #define STM_USB_DIEPCTL_TXFNUM_MASK 0xf
1368 #define STM_USB_DIEPCTL_STALL 21
1369 #define STM_USB_DIEPCTL_EPTYP 18
1370 #define STM_USB_DIEPCTL_EPTYP_CONTROL 0
1371 #define STM_USB_DIEPCTL_EPTYP_ISOCHRONOUS 1
1372 #define STM_USB_DIEPCTL_EPTYP_BULK 2
1373 #define STM_USB_DIEPCTL_EPTYP_INTERRUPT 3
1374 #define STM_USB_DIEPCTL_EPTYP_MASK 3
1375 #define STM_USB_DIEPCTL_NAKSTS 17
1376 #define STM_USB_DIEPCTL_EONUM 16
1377 #define STM_USB_DIEPCTL_USBAEP 15
1378 #define STM_USB_DIEPCTL_MPSIZ 0
1379 #define STM_USB_DIEPCTL_MPSIZ0_64 0
1380 #define STM_USB_DIEPCTL_MPSIZ0_32 1
1381 #define STM_USB_DIEPCTL_MPSIZ0_16 2
1382 #define STM_USB_DIEPCTL_MPSIZ0_8 3
1383 #define STM_USB_DIEPCTL_MPSIZ0_MASK 3
1384 #define STM_USB_DIEPCTL_MPSIZ_MASK 0x7f
1386 #define STM_USB_DIEPINT_NAK 13
1387 #define STM_USB_DIEPINT_PKTDRPSTS 11
1388 #define STM_USB_DIEPINT_TXFIFOUDRN 8
1389 #define STM_USB_DIEPINT_TXFE 7
1390 #define STM_USB_DIEPINT_INEPNE 6
1391 #define STM_USB_DIEPINT_INEPNM 5
1392 #define STM_USB_DIEPINT_ITTXFE 4
1393 #define STM_USB_DIEPINT_TOC 3
1394 #define STM_USB_DIEPINT_EPDISD 1
1395 #define STM_USB_DIEPINT_XFRC 0
1397 #define STM_USB_DIEPTSIZ_MCNT 29
1398 #define STM_USB_DIEPTSIZ_MCNT_MASK 3
1399 #define STM_USB_DIEPTSIZ_PKTCNT 19
1400 #define STM_USB_DIEPTSIZ_PKTCNT0_MASK 3
1401 #define STM_USB_DIEPTSIZ_PKTCNT_MASK 0x3ff
1402 #define STM_USB_DIEPTSIZ_XFRSIZ 0
1403 #define STM_USB_DIEPTSIZ_XFRSIZ0_MASK 0x7f
1404 #define STM_USB_DIEPTSIZ_XFRSIZ_MASK 0x7ffff
1406 #define STM_USB_DOEPCTL_EPENA 31
1407 #define STM_USB_DOEPCTL_EPDIS 30
1408 #define STM_USB_DOEPCTL_SNAK 27
1409 #define STM_USB_DOEPCTL_CNAK 26
1410 #define STM_USB_DOEPCTL_STALL 21
1411 #define STM_USB_DOEPCTL_SNPM 20
1412 #define STM_USB_DOEPCTL_EPTYP 18
1413 #define STM_USB_DOEPCTL_EPTYP_CONTROL 0
1414 #define STM_USB_DOEPCTL_EPTYP_ISOCHRONOUS 1
1415 #define STM_USB_DOEPCTL_EPTYP_BULK 2
1416 #define STM_USB_DOEPCTL_EPTYP_INTERRUPT 3
1417 #define STM_USB_DOEPCTL_EPTYP_MASK 3
1418 #define STM_USB_DOEPCTL_NAKSTS 17
1419 #define STM_USB_DOEPCTL_USBAEP 15
1420 #define STM_USB_DOEPCTL_MPSIZ 0
1421 #define STM_USB_DOEPCTL_MPSIZ0_64 0
1422 #define STM_USB_DOEPCTL_MPSIZ0_32 1
1423 #define STM_USB_DOEPCTL_MPSIZ0_16 2
1424 #define STM_USB_DOEPCTL_MPSIZ0_8 3
1425 #define STM_USB_DOEPCTL_MPSIZ0_MASK 3
1427 #define STM_USB_DOEPINT_NAK 13
1428 #define STM_USB_DOEPINT_BERR 12
1429 #define STM_USB_DOEPINT_OUTPKTERR 8
1430 #define STM_USB_DOEPINT_STSPHSRX 5
1431 #define STM_USB_DOEPINT_OTEPDIS 4
1432 #define STM_USB_DOEPINT_STUP 3
1433 #define STM_USB_DOEPINT_EPDISD 1
1434 #define STM_USB_DOEPINT_XFRC 0
1436 #define STM_USB_DOEPTSIZ_STUPCNT 29
1437 #define STM_USB_DOEPTSIZ_STUPCNT_MASK 3
1438 #define STM_USB_DOEPTSIZ_PKTCNT 19
1439 #define STM_USB_DOEPTSIZ_XFRSIZ 0
1440 #define STM_USB_DOEPTSIZ_XFRSIZ_MASK 0x7f
1444 Delay after an RCC peripheral clock enabling
1448 A delay between an RCC peripheral clock enable and the effective
1449 peripheral enabling should be taken into account in order to manage
1450 the peripheral read/write to registers.
1452 This delay depends on the peripheral’s mapping:
1454 • If the peripheral is mapped on AHB: the delay should be equal to
1457 • If the peripheral is mapped on APB: the delay should be equal to
1458 1 + (AHB/APB prescaler) cycles.
1462 1. Use the DSB instruction to stall the Cortex-M4 CPU pipeline
1463 until the instruction is completed.
1465 2. Insert “n” NOPs between the RCC enable bit write and the
1466 peripheral register writes
1470 stm32f4_set_rcc(uint32_t *rcc, uint32_t value)
1478 In some specific cases, DMA2 data corruption occurs when managing
1479 AHB and APB2 peripherals in a concurrent way
1483 When the DMA2 is managing concurrent requests of AHB and APB2
1484 peripherals, the transfer on the AHB could be performed several
1487 Impacted peripheral are:
1489 • Quad-SPI: indirect mode read and write transfers
1491 • FSMC: read and write operation with external device having FIFO
1493 • GPIO: DMA2 transfers to GPIO registers (in memory-to-peripheral
1494 transfer mode).The transfers from GPIOs register are not
1498 The data corruption is due to multiple DMA2 accesses over AHB
1499 peripheral port impacting peripherals embedding a FIFO.
1501 For transfer to the internal SRAM through the DMA2 AHB peripheral
1502 port the accesses could be performed several times but without data
1503 corruptions in cases of concurrent requests.
1507 • The DMA2 AHB memory port must be used when reading/writing
1508 from/to Quad-SPI and FSMC instead of DMA2 AHB default peripheral
1511 • The DMA2 AHB memory port must be used when writing to GPIOs
1512 instead of DMA2 AHB default peripheral port.
1514 Refer to application note AN4031 section “Take benefits of DMA2
1515 controller and system architecture flexibility” for more details
1516 about DMA controller feature.
1522 #endif /* _STM32F4_H_ */