2 * Copyright © 2018 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
20 typedef volatile uint32_t vuint32_t;
21 typedef volatile void * vvoid_t;
22 typedef volatile uint16_t vuint16_t;
23 typedef volatile uint8_t vuint8_t;
30 extern struct stm_pwr stm_pwr;
32 #define stm_pwr (*((struct stm_pwr *) 0x40007000))
34 #define STM_PWR_CR_FISSR 21
35 #define STM_PWR_CR_FMSSR 20
36 #define STM_PWR_CR_VOS 14
37 #define STM_PWR_CR_VOS_SCALE_MODE_3 1
38 #define STM_PWR_CR_VOS_SCALE_MODE_2 2
39 #define STM_PWR_CR_VOS_SCALE_MODE_1 3
40 #define STM_PWR_CR_VOS_SCALE_MODE_MASK 3
41 #define STM_PWR_CR_ADCDC1 13
42 #define STM_PWR_CR_MRLVDS 11
43 #define STM_PWR_CR_LPLVDS 10
44 #define STM_PWR_CR_FPDS 9
45 #define STM_PWR_CR_DBP 8
46 #define STM_PWR_CR_PLS 5
47 #define STM_PWR_CR_PVDE 4
48 #define STM_PWR_CR_CSBF 3
49 #define STM_PWR_CR_CWUF 2
50 #define STM_PWR_CR_PDDS 1
51 #define STM_PWR_CR_LPDS 0
103 extern struct stm_rcc stm_rcc;
105 #define stm_rcc (*((struct stm_rcc *) 0x40023800))
107 /* Internal HSI is 16MHz */
108 #define STM_HSI_FREQ 16000000
110 #define STM_RCC_CR_PLLI2SRDY (27)
111 #define STM_RCC_CR_PLLI2SON (26)
112 #define STM_RCC_CR_PLLRDY (25)
113 #define STM_RCC_CR_PLLON (24)
114 #define STM_RCC_CR_CSSON (19)
115 #define STM_RCC_CR_HSEBYP (18)
116 #define STM_RCC_CR_HSERDY (17)
117 #define STM_RCC_CR_HSEON (16)
118 #define STM_RCC_CR_HSICAL (8)
119 #define STM_RCC_CR_HSITRIM (3)
120 #define STM_RCC_CR_HSIRDY (1)
121 #define STM_RCC_CR_HSION (0)
123 #define STM_RCC_PLLCFGR_PLLM 0
124 #define STM_RCC_PLLCFGR_PLLM_MASK 0x3f
125 #define STM_RCC_PLLCFGR_PLLN 6
126 #define STM_RCC_PLLCFGR_PLLN_MASK 0x1ff
127 #define STM_RCC_PLLCFGR_PLLP 16
128 #define STM_RCC_PLLCFGR_PLLP_MASK 0x3
129 #define STM_RCC_PLLCFGR_PLLSRC 22
130 #define STM_RCC_PLLCFGR_PLLSRC_HSI 0
131 #define STM_RCC_PLLCFGR_PLLSRC_HSE 1
132 #define STM_RCC_PLLCFGR_PLLQ 24
133 #define STM_RCC_PLLCFGR_PLLQ_MASK 0xf
134 #define STM_RCC_PLLCFGR_PLLR 28
135 #define STM_RCC_PLLCFGR_PLLR_MASK 0x7
137 #define STM_RCC_CFGR_MCO2 (30)
138 #define STM_RCC_CFGR_MCO2PRE (27)
139 #define STM_RCC_CFGR_MCO1PRE (24)
140 #define STM_RCC_CFGR_MCO1 (21)
141 #define STM_RCC_CFGR_RTCPRE (16)
143 #define STM_RCC_CFGR_PPRE2 (13)
144 #define STM_RCC_CFGR_PPRE2_DIV_1 0
145 #define STM_RCC_CFGR_PPRE2_DIV_2 4
146 #define STM_RCC_CFGR_PPRE2_DIV_4 5
147 #define STM_RCC_CFGR_PPRE2_DIV_8 6
148 #define STM_RCC_CFGR_PPRE2_DIV_16 7
149 #define STM_RCC_CFGR_PPRE2_MASK 7
151 #define STM_RCC_CFGR_PPRE1 (10)
152 #define STM_RCC_CFGR_PPRE1_DIV_1 0
153 #define STM_RCC_CFGR_PPRE1_DIV_2 4
154 #define STM_RCC_CFGR_PPRE1_DIV_4 5
155 #define STM_RCC_CFGR_PPRE1_DIV_8 6
156 #define STM_RCC_CFGR_PPRE1_DIV_16 7
157 #define STM_RCC_CFGR_PPRE1_MASK 7
159 #define STM_RCC_CFGR_HPRE (4)
160 #define STM_RCC_CFGR_HPRE_DIV_1 0x0
161 #define STM_RCC_CFGR_HPRE_DIV_2 0x8
162 #define STM_RCC_CFGR_HPRE_DIV_4 0x9
163 #define STM_RCC_CFGR_HPRE_DIV_8 0xa
164 #define STM_RCC_CFGR_HPRE_DIV_16 0xb
165 #define STM_RCC_CFGR_HPRE_DIV_64 0xc
166 #define STM_RCC_CFGR_HPRE_DIV_128 0xd
167 #define STM_RCC_CFGR_HPRE_DIV_256 0xe
168 #define STM_RCC_CFGR_HPRE_DIV_512 0xf
169 #define STM_RCC_CFGR_HPRE_MASK 0xf
171 #define STM_RCC_CFGR_SWS (2)
172 #define STM_RCC_CFGR_SWS_HSI 0
173 #define STM_RCC_CFGR_SWS_HSE 1
174 #define STM_RCC_CFGR_SWS_PLL 2
175 #define STM_RCC_CFGR_SWS_MASK 3
177 #define STM_RCC_CFGR_SW (0)
178 #define STM_RCC_CFGR_SW_HSI 0
179 #define STM_RCC_CFGR_SW_HSE 1
180 #define STM_RCC_CFGR_SW_PLL 2
181 #define STM_RCC_CFGR_SW_MASK 3
183 #define STM_RCC_AHB1ENR_IOPAEN 0
184 #define STM_RCC_AHB1ENR_IOPBEN 1
185 #define STM_RCC_AHB1ENR_IOPCEN 2
186 #define STM_RCC_AHB1ENR_IOPDEN 3
187 #define STM_RCC_AHB1ENR_IOPEEN 4
188 #define STM_RCC_AHB1ENR_IOPFEN 5
189 #define STM_RCC_AHB1ENR_IOPGEN 6
190 #define STM_RCC_AHB1ENR_IOPHEN 7
192 #define STM_RCC_APB1ENR_UART8EN 31
193 #define STM_RCC_APB1ENR_UART7EN 30
194 #define STM_RCC_APB1ENR_DACEN 29
195 #define STM_RCC_APB1ENR_PWREN 28
196 #define STM_RCC_APB1ENR_CAN3EN 27
197 #define STM_RCC_APB1ENR_CAN2EN 26
198 #define STM_RCC_APB1ENR_CAN1EN 25
199 #define STM_RCC_APB1ENR_I2CFMP1EN 24
200 #define STM_RCC_APB1ENR_I2C3EN 23
201 #define STM_RCC_APB1ENR_I2C2EN 22
202 #define STM_RCC_APB1ENR_I2C1EN 21
203 #define STM_RCC_APB1ENR_UART5EN 20
204 #define STM_RCC_APB1ENR_UART4EN 19
205 #define STM_RCC_APB1ENR_USART3EN 18
206 #define STM_RCC_APB1ENR_USART2EN 17
207 #define STM_RCC_APB1ENR_SPI3EN 15
208 #define STM_RCC_APB1ENR_SPI2EN 14
209 #define STM_RCC_APB1ENR_WWDGEN 11
210 #define STM_RCC_APB1ENR_RTCAPBEN 10
211 #define STM_RCC_APB1ENR_LPTIMER1EN 9
212 #define STM_RCC_APB1ENR_TIM14EN 8
213 #define STM_RCC_APB1ENR_TIM13EN 7
214 #define STM_RCC_APB1ENR_TIM12EN 6
215 #define STM_RCC_APB1ENR_TIM7EN 5
216 #define STM_RCC_APB1ENR_TIM6EN 4
217 #define STM_RCC_APB1ENR_TIM5EN 3
218 #define STM_RCC_APB1ENR_TIM4EN 2
219 #define STM_RCC_APB1ENR_TIM3EN 1
220 #define STM_RCC_APB1ENR_TIM2EN 0
222 #define STM_RCC_CSR_RMVF 24
228 extern struct stm_ictr stm_ictr;
230 #define stm_ictr (*((struct stm_ictr *) 0xe000e004))
232 #define STM_ICTR_ICTR_INTLINESNUM 0
233 #define STM_ICTR_ICTR_INTLINESNUM_MASK 0xf
236 vuint32_t iser[8]; /* 0x000 0xe000e100 Set Enable Register */
238 uint8_t _unused020[0x080 - 0x020];
240 vuint32_t icer[8]; /* 0x080 0xe000e180 Clear Enable Register */
242 uint8_t _unused0a0[0x100 - 0x0a0];
244 vuint32_t ispr[8]; /* 0x100 0xe000e200 Set Pending Register */
246 uint8_t _unused120[0x180 - 0x120];
248 vuint32_t icpr[8]; /* 0x180 0xe000e280 Clear Pending Register */
250 uint8_t _unused1a0[0x200 - 0x1a0];
252 vuint32_t iabr[8]; /* 0x200 0xe000e300 Active Bit Register */
254 uint8_t _unused220[0x300 - 0x220];
256 vuint32_t ipr[60]; /* 0x300 0xe000e400 Priority Register */
259 extern struct stm_nvic stm_nvic;
261 #define stm_nvic (*((struct stm_nvic *) 0xe000e100))
263 #define IRQ_REG(irq) ((irq) >> 5)
264 #define IRQ_BIT(irq) ((irq) & 0x1f)
265 #define IRQ_MASK(irq) (1 << IRQ_BIT(irq))
266 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
269 stm_nvic_set_enable(int irq) {
270 stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
274 stm_nvic_clear_enable(int irq) {
275 stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
279 stm_nvic_enabled(int irq) {
280 return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
284 stm_nvic_set_pending(int irq) {
285 stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
289 stm_nvic_clear_pending(int irq) {
290 stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
294 stm_nvic_pending(int irq) {
295 return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
299 stm_nvic_active(int irq) {
300 return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
303 #define IRQ_PRIO_REG(irq) ((irq) >> 2)
304 #define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3)
305 #define IRQ_PRIO_MASK(irq) (0xff << IRQ_PRIO_BIT(irq))
308 stm_nvic_set_priority(int irq, uint8_t prio) {
309 int n = IRQ_PRIO_REG(irq);
313 v &= ~IRQ_PRIO_MASK(irq);
314 v |= (prio) << IRQ_PRIO_BIT(irq);
318 static inline uint8_t
319 stm_nvic_get_priority(int irq) {
320 return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
334 extern struct stm_flash stm_flash;
336 #define stm_flash (*((struct stm_flash *) 0x40023c00))
338 #define STM_FLASH_ACR_DCRST 12
339 #define STM_FLASH_ACR_ICRST 11
340 #define STM_FLASH_ACR_DCEN 10
341 #define STM_FLASH_ACR_ICEN 9
342 #define STM_FLASH_ACR_PRFTEN 8
343 #define STM_FLASH_ACR_LATENCY 0
345 struct stm_flash_size {
349 extern struct stm_flash_size stm_flash_size;
351 #define stm_flash_size (*((struct stm_flash_size *) 0x1fff7a22))
368 #define STM_MODER_SHIFT(pin) ((pin) << 1)
369 #define STM_MODER_MASK 3
370 #define STM_MODER_INPUT 0
371 #define STM_MODER_OUTPUT 1
372 #define STM_MODER_ALTERNATE 2
373 #define STM_MODER_ANALOG 3
376 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
377 gpio->moder = ((gpio->moder &
378 ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
379 value << STM_MODER_SHIFT(pin));
382 static inline uint32_t
383 stm_moder_get(struct stm_gpio *gpio, int pin) {
384 return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
387 #define STM_OTYPER_SHIFT(pin) (pin)
388 #define STM_OTYPER_MASK 1
389 #define STM_OTYPER_PUSH_PULL 0
390 #define STM_OTYPER_OPEN_DRAIN 1
393 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
394 gpio->otyper = ((gpio->otyper &
395 ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
396 value << STM_OTYPER_SHIFT(pin));
399 static inline uint32_t
400 stm_otyper_get(struct stm_gpio *gpio, int pin) {
401 return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
404 #define STM_OSPEEDR_SHIFT(pin) ((pin) << 1)
405 #define STM_OSPEEDR_MASK 3
406 #define STM_OSPEEDR_LOW 0 /* 2-8MHz */
407 #define STM_OSPEEDR_MEDIUM 1 /* 12.5-50MHz */
408 #define STM_OSPEEDR_FAST 2 /* 25-100MHz */
409 #define STM_OSPEEDR_HIGH 3 /* 50-100MHz */
412 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
413 gpio->ospeedr = ((gpio->ospeedr &
414 ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
415 value << STM_OSPEEDR_SHIFT(pin));
418 static inline uint32_t
419 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
420 return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
423 #define STM_PUPDR_SHIFT(pin) ((pin) << 1)
424 #define STM_PUPDR_MASK 3
425 #define STM_PUPDR_NONE 0
426 #define STM_PUPDR_PULL_UP 1
427 #define STM_PUPDR_PULL_DOWN 2
428 #define STM_PUPDR_RESERVED 3
431 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
432 gpio->pupdr = ((gpio->pupdr &
433 ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
434 value << STM_PUPDR_SHIFT(pin));
437 static inline uint32_t
438 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
439 return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
442 #define STM_AFR_SHIFT(pin) ((pin) << 2)
443 #define STM_AFR_MASK 0xf
444 #define STM_AFR_NONE 0
445 #define STM_AFR_AF0 0x0
446 #define STM_AFR_AF1 0x1
447 #define STM_AFR_AF2 0x2
448 #define STM_AFR_AF3 0x3
449 #define STM_AFR_AF4 0x4
450 #define STM_AFR_AF5 0x5
451 #define STM_AFR_AF6 0x6
452 #define STM_AFR_AF7 0x7
453 #define STM_AFR_AF8 0x8
454 #define STM_AFR_AF9 0x9
455 #define STM_AFR_AF10 0xa
456 #define STM_AFR_AF11 0xb
457 #define STM_AFR_AF12 0xc
458 #define STM_AFR_AF13 0xd
459 #define STM_AFR_AF14 0xe
460 #define STM_AFR_AF15 0xf
463 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
465 * Set alternate pin mode too
467 stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
469 gpio->afrl = ((gpio->afrl &
470 ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
471 value << STM_AFR_SHIFT(pin));
474 gpio->afrh = ((gpio->afrh &
475 ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
476 value << STM_AFR_SHIFT(pin));
480 static inline uint32_t
481 stm_afr_get(struct stm_gpio *gpio, int pin) {
483 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
486 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
491 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
492 /* Use the bit set/reset register to do this atomically */
493 gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
496 static inline uint8_t
497 stm_gpio_get(struct stm_gpio *gpio, int pin) {
498 return (gpio->idr >> pin) & 1;
501 static inline uint16_t
502 stm_gpio_get_all(struct stm_gpio *gpio) {
507 * We can't define these in registers.ld or our fancy
508 * ao_enable_gpio macro will expand into a huge pile of code
509 * as the compiler won't do correct constant folding and
510 * dead-code elimination
513 extern struct stm_gpio stm_gpioa;
514 extern struct stm_gpio stm_gpiob;
515 extern struct stm_gpio stm_gpioc;
516 extern struct stm_gpio stm_gpiod;
517 extern struct stm_gpio stm_gpioe;
518 extern struct stm_gpio stm_gpiof;
519 extern struct stm_gpio stm_gpiog;
520 extern struct stm_gpio stm_gpioh;
522 #define stm_gpioa (*((struct stm_gpio *) 0x40020000))
523 #define stm_gpiob (*((struct stm_gpio *) 0x40020400))
524 #define stm_gpioc (*((struct stm_gpio *) 0x40020800))
525 #define stm_gpiod (*((struct stm_gpio *) 0x40020c00))
526 #define stm_gpioe (*((struct stm_gpio *) 0x40021000))
527 #define stm_gpiof (*((struct stm_gpio *) 0x40021400))
528 #define stm_gpiog (*((struct stm_gpio *) 0x40021800))
529 #define stm_gpioh (*((struct stm_gpio *) 0x40021c00))
577 vuint8_t pad_d90[0xf00 - 0xd90];
582 extern struct stm_scb stm_scb;
584 #define stm_scb (*((struct stm_scb *) 0xe000ed00))
586 #define STM_SCB_CPACR_CP(n) ((n) <<1)
587 #define STM_SCB_CPACR_DENIED 0
588 #define STM_SCB_CPACR_PRIVILEGED 1
589 #define STM_SCB_CPACR_RESERVED 2
590 #define STM_SCB_CPACR_FULL 3
591 #define STM_SCB_CPACR_FP0 STM_SCB_CPACR_CP(10)
592 #define STM_SCB_CPACR_FP1 STM_SCB_CPACR_CP(11)
594 /* The SYSTICK starts at 0xe000e010 */
603 extern struct stm_systick stm_systick;
605 #define stm_systick (*((struct stm_systick *) 0xe000e010))
607 #define STM_SYSTICK_CSR_ENABLE 0
608 #define STM_SYSTICK_CSR_TICKINT 1
609 #define STM_SYSTICK_CSR_CLKSOURCE 2
610 #define STM_SYSTICK_CSR_CLKSOURCE_AHB_8 0
611 #define STM_SYSTICK_CSR_CLKSOURCE_AHB 1
612 #define STM_SYSTICK_CSR_COUNTFLAG 16
616 Delay after an RCC peripheral clock enabling
620 A delay between an RCC peripheral clock enable and the effective
621 peripheral enabling should be taken into account in order to manage
622 the peripheral read/write to registers.
624 This delay depends on the peripheral’s mapping:
626 • If the peripheral is mapped on AHB: the delay should be equal to
629 • If the peripheral is mapped on APB: the delay should be equal to
630 1 + (AHB/APB prescaler) cycles.
634 1. Use the DSB instruction to stall the Cortex-M4 CPU pipeline
635 until the instruction is completed.
637 2. Insert “n” NOPs between the RCC enable bit write and the
638 peripheral register writes
642 stm32f4_set_rcc(uint32_t *rcc, uint32_t value)
650 In some specific cases, DMA2 data corruption occurs when managing
651 AHB and APB2 peripherals in a concurrent way
655 When the DMA2 is managing concurrent requests of AHB and APB2
656 peripherals, the transfer on the AHB could be performed several
659 Impacted peripheral are:
661 • Quad-SPI: indirect mode read and write transfers
663 • FSMC: read and write operation with external device having FIFO
665 • GPIO: DMA2 transfers to GPIO registers (in memory-to-peripheral
666 transfer mode).The transfers from GPIOs register are not
670 The data corruption is due to multiple DMA2 accesses over AHB
671 peripheral port impacting peripherals embedding a FIFO.
673 For transfer to the internal SRAM through the DMA2 AHB peripheral
674 port the accesses could be performed several times but without data
675 corruptions in cases of concurrent requests.
679 • The DMA2 AHB memory port must be used when reading/writing
680 from/to Quad-SPI and FSMC instead of DMA2 AHB default peripheral
683 • The DMA2 AHB memory port must be used when writing to GPIOs
684 instead of DMA2 AHB default peripheral port.
686 Refer to application note AN4031 section “Take benefits of DMA2
687 controller and system architecture flexibility” for more details
688 about DMA controller feature.
694 #endif /* _STM32F4_H_ */