2 * Copyright © 2023 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
24 typedef volatile uint32_t vuint32_t;
25 typedef volatile uint16_t vuint16_t;
26 typedef volatile void * vvoid_t;
45 extern struct stm_rcc stm_rcc;
47 //#define stm_rcc (*((struct stm_rcc *) 0x40021000))
49 #define STM_RCC_CR_RTCPRE (29)
50 #define STM_RCC_CR_RTCPRE_HSE_DIV_2 0
51 #define STM_RCC_CR_RTCPRE_HSE_DIV_4 1
52 #define STM_RCC_CR_RTCPRE_HSE_DIV_8 2
53 #define STM_RCC_CR_RTCPRE_HSE_DIV_16 3
54 #define STM_RCC_CR_RTCPRE_HSE_MASK 3UL
56 #define STM_RCC_CR_PLL3RDY (29)
57 #define STM_RCC_CR_PLL3ON (28)
58 #define STM_RCC_CR_PLL2RDY (27)
59 #define STM_RCC_CR_PLL2ON (26)
60 #define STM_RCC_CR_PLLRDY (25)
61 #define STM_RCC_CR_PLLON (24)
62 #define STM_RCC_CR_CSSON (19)
63 #define STM_RCC_CR_HSEBYP (18)
64 #define STM_RCC_CR_HSERDY (17)
65 #define STM_RCC_CR_HSEON (16)
66 #define STM_RCC_CR_HSICAL (8)
67 #define STM_RCC_CR_HSITRIM (3)
68 #define STM_RCC_CR_HSIRDY (1)
69 #define STM_RCC_CR_HSION (0)
71 #define STM_RCC_CFGR_MCO (24)
72 #define STM_RCC_CFGR_MCO_DISABLE 0
73 #define STM_RCC_CFGR_MCO_SYSCLK 4
74 #define STM_RCC_CFGR_MCO_HSI 5
75 #define STM_RCC_CFGR_MCO_HSE 6
76 #define STM_RCC_CFGR_MCO_PLL_2 7
77 #define STM_RCC_CFGR_MCO_MASK 7UL
79 #define STM_RCC_CFGR_USBPRE (22)
80 #define STM_RCC_CFGR_USBPRE_1_5 0
81 #define STM_RCC_CFGR_USBPRE_1 1
83 #define STM_RCC_CFGR_PLLMUL (18)
84 #define STM_RCC_CFGR_PLLMUL_2 0
85 #define STM_RCC_CFGR_PLLMUL_3 1
86 #define STM_RCC_CFGR_PLLMUL_4 2
87 #define STM_RCC_CFGR_PLLMUL_5 3
88 #define STM_RCC_CFGR_PLLMUL_6 4
89 #define STM_RCC_CFGR_PLLMUL_7 5
90 #define STM_RCC_CFGR_PLLMUL_8 6
91 #define STM_RCC_CFGR_PLLMUL_9 7
92 #define STM_RCC_CFGR_PLLMUL_10 8
93 #define STM_RCC_CFGR_PLLMUL_11 9
94 #define STM_RCC_CFGR_PLLMUL_12 10
95 #define STM_RCC_CFGR_PLLMUL_13 11
96 #define STM_RCC_CFGR_PLLMUL_14 12
97 #define STM_RCC_CFGR_PLLMUL_15 13
98 #define STM_RCC_CFGR_PLLMUL_16 14
99 #define STM_RCC_CFGR_PLLMUL_MASK 0xfUL
101 #define STM_RCC_CFGR_PLLXTPRE (17)
102 #define STM_RCC_CFGR_PLLXTPRE_1 0
103 #define STM_RCC_CFGR_PLLXTPRE_2 1
104 #define STM_RCC_CFGR_PLLXTPRE_MASK 1UL
106 #define STM_RCC_CFGR_PLLSRC (16)
107 #define STM_RCC_CFGR_PLLSRC_HSI_2 0
108 #define STM_RCC_CFGR_PLLSRC_HSE 1
110 #define STM_RCC_CFGR_ADCPRE (14)
111 #define STM_RCC_CFGR_ADCPRE_2 0
112 #define STM_RCC_CFGR_ADCPRE_4 1
113 #define STM_RCC_CFGR_ADCPRE_6 2
114 #define STM_RCC_CFGR_ADCPRE_8 3
115 #define STM_RCC_CFGR_ADCPRE_MASK 3UL
117 #define STM_RCC_CFGR_PPRE2 (11)
118 #define STM_RCC_CFGR_PPRE2_DIV_1 0
119 #define STM_RCC_CFGR_PPRE2_DIV_2 4
120 #define STM_RCC_CFGR_PPRE2_DIV_4 5
121 #define STM_RCC_CFGR_PPRE2_DIV_8 6
122 #define STM_RCC_CFGR_PPRE2_DIV_16 7
123 #define STM_RCC_CFGR_PPRE2_MASK 7UL
125 #define STM_RCC_CFGR_PPRE1 (8)
126 #define STM_RCC_CFGR_PPRE1_DIV_1 0
127 #define STM_RCC_CFGR_PPRE1_DIV_2 4
128 #define STM_RCC_CFGR_PPRE1_DIV_4 5
129 #define STM_RCC_CFGR_PPRE1_DIV_8 6
130 #define STM_RCC_CFGR_PPRE1_DIV_16 7
131 #define STM_RCC_CFGR_PPRE1_MASK 7UL
133 #define STM_RCC_CFGR_HPRE (4)
134 #define STM_RCC_CFGR_HPRE_DIV_1 0
135 #define STM_RCC_CFGR_HPRE_DIV_2 8
136 #define STM_RCC_CFGR_HPRE_DIV_4 9
137 #define STM_RCC_CFGR_HPRE_DIV_8 0xa
138 #define STM_RCC_CFGR_HPRE_DIV_16 0xb
139 #define STM_RCC_CFGR_HPRE_DIV_64 0xc
140 #define STM_RCC_CFGR_HPRE_DIV_128 0xd
141 #define STM_RCC_CFGR_HPRE_DIV_256 0xe
142 #define STM_RCC_CFGR_HPRE_DIV_512 0xf
143 #define STM_RCC_CFGR_HPRE_MASK 0xfUL
145 #define STM_RCC_CFGR_SWS (2)
146 #define STM_RCC_CFGR_SWS_HSI 0
147 #define STM_RCC_CFGR_SWS_HSE 1
148 #define STM_RCC_CFGR_SWS_PLL 2
149 #define STM_RCC_CFGR_SWS_MASK 3UL
151 #define STM_RCC_CFGR_SW (0)
152 #define STM_RCC_CFGR_SW_HSI 0
153 #define STM_RCC_CFGR_SW_HSE 1
154 #define STM_RCC_CFGR_SW_PLL 2
155 #define STM_RCC_CFGR_SW_MASK 3UL
157 #define STM_RCC_AHBENR_CRCEN 6
158 #define STM_RCC_AHBENR_FLITFEN 4
159 #define STM_RCC_AHBENR_SRAMEN 2
160 #define STM_RCC_AHBENR_DMA2EN 1
161 #define STM_RCC_AHBENR_DMA1EN 0
164 #define STM_RCC_APB2ENR_USART1EN 14
165 #define STM_RCC_APB2ENR_SPI1EN 12
166 #define STM_RCC_APB2ENR_TIM1EN 11
167 #define STM_RCC_APB2ENR_ADC2EN 10
168 #define STM_RCC_APB2ENR_ADC1EN 9
169 #define STM_RCC_APB2ENR_IOPEEN 6
170 #define STM_RCC_APB2ENR_IOPDEN 5
171 #define STM_RCC_APB2ENR_IOPCEN 4
172 #define STM_RCC_APB2ENR_IOPBEN 3
173 #define STM_RCC_APB2ENR_IOPAEN 2
174 #define STM_RCC_APB2ENR_AFIOEN 0
176 #define STM_RCC_APB1ENR_DACEN 29
177 #define STM_RCC_APB1ENR_PWREN 28
178 #define STM_RCC_APB1ENR_BKPEN 27
179 #define STM_RCC_APB1ENR_CANEN 26
180 #define STM_RCC_APB1ENR_USBEN 23
181 #define STM_RCC_APB1ENR_I2C2EN 22
182 #define STM_RCC_APB1ENR_I2C1EN 21
183 #define STM_RCC_APB1ENR_UART5EN 20
184 #define STM_RCC_APB1ENR_UART4EN 19
185 #define STM_RCC_APB1ENR_USART3EN 18
186 #define STM_RCC_APB1ENR_USART2EN 17
187 #define STM_RCC_APB1ENR_SPI3EN 15
188 #define STM_RCC_APB1ENR_SPI2EN 14
189 #define STM_RCC_APB1ENR_WWDGEN 11
190 #define STM_RCC_APB1ENR_TIM7EN 5
191 #define STM_RCC_APB1ENR_TIM6EN 4
192 #define STM_RCC_APB1ENR_TIM5EN 3
193 #define STM_RCC_APB1ENR_TIM4EN 2
194 #define STM_RCC_APB1ENR_TIM3EN 1
195 #define STM_RCC_APB1ENR_TIM2EN 0
197 #define STM_RCC_CSR_LPWRRSTF (31)
198 #define STM_RCC_CSR_WWDGRSTF (30)
199 #define STM_RCC_CSR_IWDGRSTF (29)
200 #define STM_RCC_CSR_SFTRSTF (28)
201 #define STM_RCC_CSR_PORRSTF (27)
202 #define STM_RCC_CSR_PINRSTF (26)
203 #define STM_RCC_CSR_RMVF (24)
204 #define STM_RCC_CSR_LSIRDY (1)
205 #define STM_RCC_CSR_LSION (0)
214 extern struct stm_systick stm_systick;
216 //#define stm_systick (*((struct stm_systick *) 0xe000e010))
218 #define STM_SYSTICK_CTRL_ENABLE 0
219 #define STM_SYSTICK_CTRL_TICKINT 1
220 #define STM_SYSTICK_CTRL_CLKSOURCE 2
221 #define STM_SYSTICK_CTRL_CLKSOURCE_HCLK_8 0
222 #define STM_SYSTICK_CTRL_CLKSOURCE_HCLK 1
223 #define STM_SYSTICK_CTRL_COUNTFLAG 16
225 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
228 vuint32_t iser[3]; /* 0x000 0xe000e100 Set Enable Register */
230 uint8_t _unused00c[0x080 - 0x00c];
232 vuint32_t icer[3]; /* 0x080 0xe000e180 Clear Enable Register */
234 uint8_t _unused08c[0x100 - 0x08c];
236 vuint32_t ispr[3]; /* 0x100 0xe000e200 Set Pending Register */
238 uint8_t _unused10c[0x180 - 0x10c];
240 vuint32_t icpr[3]; /* 0x180 0xe000e280 Clear Pending Register */
242 uint8_t _unused18c[0x200 - 0x18c];
244 vuint32_t iabr[3]; /* 0x200 0xe000e300 Active Bit Register */
246 uint8_t _unused20c[0x300 - 0x20c];
248 vuint32_t ipr[31]; /* 0x300 0xe000e400 Priority Register */
250 uint8_t _unused37c[0xe00 - 0x37c]; /* covers SCB */
252 vuint32_t stir; /* 0xe00 0xe000ee00 Software Trigger Interrupt Register */
255 extern struct stm_nvic stm_nvic;
257 //#define stm_nvic (*((struct stm_nvic *) 0xe000e100))
259 #define IRQ_REG(irq) ((irq) >> 5)
260 #define IRQ_BIT(irq) ((irq) & 0x1f)
261 #define IRQ_MASK(irq) (1 << IRQ_BIT(irq))
262 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
265 stm_nvic_set_enable(int irq) {
266 stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
270 stm_nvic_clear_enable(int irq) {
271 stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
275 stm_nvic_enabled(int irq) {
276 return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
280 stm_nvic_set_pending(int irq) {
281 stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
285 stm_nvic_clear_pending(int irq) {
286 stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
290 stm_nvic_pending(int irq) {
291 return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
295 stm_nvic_active(int irq) {
296 return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
299 #define IRQ_PRIO_REG(irq) ((irq) >> 2)
300 #define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3)
301 #define IRQ_PRIO_MASK(irq) (0xff << IRQ_PRIO_BIT(irq))
304 stm_nvic_set_priority(int irq, uint8_t prio) {
305 int n = IRQ_PRIO_REG(irq);
309 v &= (uint32_t) ~IRQ_PRIO_MASK(irq);
310 v |= (prio) << IRQ_PRIO_BIT(irq);
314 static inline uint8_t
315 stm_nvic_get_priority(int irq) {
316 return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
340 extern struct stm_scb stm_scb;
342 #define STM_SCB_AIRCR_VECTKEY 16
343 #define STM_SCB_AIRCR_VECTKEY_KEY 0x05fa
344 #define STM_SCB_AIRCR_PRIGROUP 8
345 #define STM_SCB_AIRCR_SYSRESETREQ 2
346 #define STM_SCB_AIRCR_VECTCLRACTIVE 1
347 #define STM_SCB_AIRCR_VECTRESET 0
353 extern struct stm_dbgmcu stm_dbgmcu;
355 static inline uint16_t
357 return stm_dbgmcu.idcode & 0xfff;
374 extern struct stm_flash stm_flash;
376 //#define stm_flash (*((struct stm_flash *) 0x40022000))
378 #define STM_FLASH_ACR_PRFTBS 5
379 #define STM_FLASH_ACR_PRFTBE 4
380 #define STM_FLASH_ACR_HLFCYA 3
381 #define STM_FLASH_ACR_LATENCY 0
382 #define STM_FLASH_ACR_LATENCY_0 0
383 #define STM_FLASH_ACR_LATENCY_1 1
384 #define STM_FLASH_ACR_LATENCY_2 2
386 #define STM_FLASH_SR_EOP 5
387 #define STM_FLASH_SR_WRPRTERR 4
388 #define STM_FLASH_SR_PGERR 2
389 #define STM_FLASH_SR_BSY 0
391 #define STM_FLASH_CR_EOPIE 12
392 #define STM_FLASH_CR_ERRIE 10
393 #define STM_FLASH_CR_OPTWRE 9
394 #define STM_FLASH_CR_LOCK 7
395 #define STM_FLASH_CR_STRT 6
396 #define STM_FLASH_CR_OPTER 5
397 #define STM_FLASH_CR_OPTPG 4
398 #define STM_FLASH_CR_MER 2
399 #define STM_FLASH_CR_PER 1
400 #define STM_FLASH_CR_PG 0
402 #define STM_FLASH_RDPRT_KEY 0x00A5
403 #define STM_FLASH_KEYR_KEY1 0x45670123
404 #define STM_FLASH_KEYR_KEY2 0xCDEF89AB
407 struct stm_flash_data {
411 vuint32_t device_id[3];
414 extern struct stm_flash_data stm_flash_data;
416 static inline uint32_t stm_flash_size(void) { return (uint32_t) stm_flash_data.f_size * 1024; }
418 //#define stm_flash_data (*((struct stm_flash_data *) 0x1ffff7e0))
430 #define STM_GPIO_CR(y) ((uint8_t) (y) >> 3)
431 #define STM_GPIO_CR_CNF(y) ((((uint8_t) (y) & 7) << 2) + 2)
432 #define STM_GPIO_CR_CNF_INPUT_ANALOG 0
433 #define STM_GPIO_CR_CNF_INPUT_FLOATING 1
434 #define STM_GPIO_CR_CNF_INPUT_PULL 2
435 #define STM_GPIO_CR_CNF_OUTPUT_PUSH_PULL 0
436 #define STM_GPIO_CR_CNF_OUTPUT_OPEN_DRAIN 1
437 #define STM_GPIO_CR_CNF_OUTPUT_AF_PUSH_PULL 2
438 #define STM_GPIO_CR_CNF_OUTPUT_AF_OPEN_DRAIN 3
439 #define STM_GPIO_CR_CNF_MASK 3U
440 #define STM_GPIO_CR_MODE(y) ((((y) & 7) << 2))
441 #define STM_GPIO_CR_MODE_INPUT 0
442 #define STM_GPIO_CR_MODE_OUTPUT_10MHZ 1
443 #define STM_GPIO_CR_MODE_OUTPUT_2MHZ 2
444 #define STM_GPIO_CR_MODE_OUTPUT_50MHZ 3
445 #define STM_GPIO_CR_MODE_MASK 3U
448 stm_gpio_conf(struct stm_gpio *gpio, int pin, uint8_t mode, uint8_t cnf)
450 uint8_t cr = STM_GPIO_CR(pin);
451 uint32_t v = gpio->cr[cr];
453 v &= ~((STM_GPIO_CR_CNF_MASK << STM_GPIO_CR_CNF(pin)) |
454 (STM_GPIO_CR_MODE_MASK << STM_GPIO_CR_MODE(pin)));
455 v |= (mode << STM_GPIO_CR_MODE(pin)) | (cnf << STM_GPIO_CR_CNF(pin));
460 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
461 /* Use the bit set/reset register to do this atomically */
462 gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
466 stm_gpio_set_mask(struct stm_gpio *gpio, uint16_t bits, uint16_t mask) {
467 /* Use the bit set/reset register to do this atomically */
468 gpio->bsrr = ((uint32_t) (~bits & mask) << 16) | ((uint32_t) (bits & mask));
472 stm_gpio_set_bits(struct stm_gpio *gpio, uint16_t bits) {
477 stm_gpio_clr_bits(struct stm_gpio *gpio, uint16_t bits) {
478 gpio->bsrr = ((uint32_t) bits) << 16;
481 static inline uint8_t
482 stm_gpio_get(struct stm_gpio *gpio, int pin) {
483 return (gpio->idr >> pin) & 1;
486 static inline uint16_t
487 stm_gpio_get_all(struct stm_gpio *gpio) {
488 return (uint16_t) gpio->idr;
491 extern struct stm_gpio stm_gpioa;
492 extern struct stm_gpio stm_gpiob;
493 extern struct stm_gpio stm_gpioc;
494 extern struct stm_gpio stm_gpiod;
495 extern struct stm_gpio stm_gpioe;
497 #define stm_gpioe (*((struct stm_gpio *) 0x40011800))
498 #define stm_gpiod (*((struct stm_gpio *) 0x40011400))
499 #define stm_gpioc (*((struct stm_gpio *) 0x40011000))
500 #define stm_gpiob (*((struct stm_gpio *) 0x40010c00))
501 #define stm_gpioa (*((struct stm_gpio *) 0x40010800))
510 extern struct stm_afio stm_afio;
512 #define stm_afio (*((struct stm_afio *) 0x40010000))
514 #define STM_AFIO_MAPR_SWJ_CFG 24
515 #define STM_AFIO_MAPR_SWJ_CFG_FULL_SWJ 0
516 #define STM_AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJTRST 1
517 #define STM_AFIO_MAPR_SWJ_CFG_SW_DP 2
518 #define STM_AFIO_MAPR_SWJ_CFG_DISABLE 4
519 #define STM_AFIO_MAPR_SWJ_CFG_MASK 7UL
520 #define STM_AFIO_MAPR_ADC2_ETRGREG_REMAP 20
521 #define STM_AFIO_MAPR_ADC2_ETRGINJ_REMAP 19
522 #define STM_AFIO_MAPR_ADC1_ETRGREG_REMAP 18
523 #define STM_AFIO_MAPR_ADC1_ETRGINJ_REMAP 17
524 #define STM_AFIO_MAPR_TIM5CH4_IREMAP 16
525 #define STM_AFIO_MAPR_PD01_REMAP 15
526 #define STM_AFIO_MAPR_CAN_REMAP 13
527 #define STM_AFIO_MAPR_CAN_REMAP_PA11_PA12 0
528 #define STM_AFIO_MAPR_CAN_REMAP_PB8_PB9 2
529 #define STM_AFIO_MAPR_CAN_REMAP_PD0_PD1 3
530 #define STM_AFIO_MAPR_CAN_REMAP_MASK 3UL
531 #define STM_AFIO_MAPR_TIM4_REMAP 12
532 #define STM_AFIO_MAPR_TIM3_REMAP 10
533 #define STM_AFIO_MAPR_TIM3_REMAP_PA6_PA7_PB0_PB1 0
534 #define STM_AFIO_MAPR_TIM3_REMAP_PB4_PB5_PB0_PB1 2
535 #define STM_AFIO_MAPR_TIM3_REMAP_PC6_PC7_PC8_PC9 3
536 #define STM_AFIO_MAPR_TIM3_REMAP_MASK 3UL
537 #define STM_AFIO_MAPR_TIM2_REMAP 8
538 #define STM_AFIO_MAPR_TIM2_REMAP_PA0_PA1_PA2_PA3 0
539 #define STM_AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3 1
540 #define STM_AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 2
541 #define STM_AFIO_MAPR_TIM2_REMAP_PA15_PB3_PB10_PB11 3
542 #define STM_AFIO_MAPR_TIM2_REMAP_MASK 3UL
543 #define STM_AFIO_MAPR_TIM1_REMAP 6
544 #define STM_AFIO_MAPR_TIM1_REMAP_PA12_PA8_PA9_PA10_PA11_PB12_PB13_PB14_PB15 0
545 #define STM_AFIO_MAPR_TIM1_REMAP_PA12_PA8_PA9_PA10_PA11_PA6_PA7_PB0_PB1 1
546 #define STM_AFIO_MAPR_TIM1_REMAP_PE7_PE9_PE11_PE13_PE14_PE15_PE8_PE10_PE12 3
547 #define STM_AFIO_MAPR_TIM1_REMAP_MASK 3
548 #define STM_AFIO_MAPR_USART3_REMAP 4
549 #define STM_AFIO_MAPR_USART3_REMAP_PB10_PB11_PB12_PB13_PB14 0
550 #define STM_AFIO_MAPR_USART3_REMAP_PC10_PC11_PC12_PB13_PB14 1
551 #define STM_AFIO_MAPR_USART3_REMAP_PD8_PD9_PD10_PD11_PD12 3
552 #define STM_AFIO_MAPR_USART3_REMAP_MASK 3
553 #define STM_AFIO_MAPR_USART2_REMAP 3
554 #define STM_AFIO_MAPR_USART2_REMAP_PA0_PA1_PA2_PA3_PA4 0
555 #define STM_AFIO_MAPR_USART2_REMAP_PD3_PD4_PD5_PD6_PD7 1
556 #define STM_AFIO_MAPR_USART2_REMAP_MASK 1
557 #define STM_AFIO_MAPR_USART1_REMAP 2
558 #define STM_AFIO_MAPR_USART1_REMAP_PA9_PA10 0
559 #define STM_AFIO_MAPR_USART1_REMAP_PB6_PB7 1
560 #define STM_AFIO_MAPR_USART1_REMAP_MASK 1
561 #define STM_AFIO_MAPR_I2C1_REMAP 1
562 #define STM_AFIO_MAPR_I2C1_REMAP_PB6_PB7 0
563 #define STM_AFIO_MAPR_I2C1_REMAP_PB8_PB9 1
564 #define STM_AFIO_MAPR_I2C1_REMAP_MASK 1
565 #define STM_AFIO_MAPR_SPI1_REMAP 0
566 #define STM_AFIO_MAPR_SPI1_REMAP_PA4_PA5_PA6_PA7 0
567 #define STM_AFIO_MAPR_SPI1_REMAP_PA15_PB3_PB4_PB5 1
568 #define STM_AFIO_MAPR_SPI1_REMAP_MASK 1
570 #define STM_AFIO_EXTICR_PA 0
571 #define STM_AFIO_EXTICR_PB 1
572 #define STM_AFIO_EXTICR_PC 2
573 #define STM_AFIO_EXTICR_PD 3
574 #define STM_AFIO_EXTICR_PE 4
575 #define STM_AFIO_EXTICR_PF 5
576 #define STM_AFIO_EXTICR_PG 6
579 stm_set_afio_mapr(uint8_t bit, uint32_t val, uint32_t mask) {
580 uint32_t mapr = stm_afio.mapr;
582 mapr &= ~(mask << bit);
583 mapr |= (val << bit);
584 stm_afio.mapr = mapr;
588 vuint32_t sr; /* status register */
589 vuint32_t dr; /* data register */
590 vuint32_t brr; /* baud rate register */
591 vuint32_t cr1; /* control register 1 */
593 vuint32_t cr2; /* control register 2 */
594 vuint32_t cr3; /* control register 3 */
595 vuint32_t gtpr; /* guard time and prescaler */
598 extern struct stm_usart stm_usart1;
599 extern struct stm_usart stm_usart2;
600 extern struct stm_usart stm_usart3;
602 //#define stm_usart1 (*((struct stm_usart *) 0x40013800))
603 //#define stm_usart2 (*((struct stm_usart *) 0x40004800))
604 //#define stm_usart3 (*((struct stm_usart *) 0x40004400))
606 #define STM_USART_SR_CTS (9) /* CTS flag */
607 #define STM_USART_SR_LBD (8) /* LIN break detection flag */
608 #define STM_USART_SR_TXE (7) /* Transmit data register empty */
609 #define STM_USART_SR_TC (6) /* Transmission complete */
610 #define STM_USART_SR_RXNE (5) /* Read data register not empty */
611 #define STM_USART_SR_IDLE (4) /* IDLE line detected */
612 #define STM_USART_SR_ORE (3) /* Overrun error */
613 #define STM_USART_SR_NE (2) /* Noise detected flag */
614 #define STM_USART_SR_FE (1) /* Framing error */
615 #define STM_USART_SR_PE (0) /* Parity error */
617 #define STM_USART_BRR_DIV_MANTISSA (4)
618 #define STM_USART_BRR_DIV_FRACTION (0)
620 #define STM_USART_CR1_UE (13) /* USART enable */
621 #define STM_USART_CR1_M (12) /* Word length */
622 #define STM_USART_CR1_WAKE (11) /* Wakeup method */
623 #define STM_USART_CR1_PCE (10) /* Parity control enable */
624 #define STM_USART_CR1_PS (9) /* Parity selection */
625 #define STM_USART_CR1_PEIE (8) /* PE interrupt enable */
626 #define STM_USART_CR1_TXEIE (7) /* TXE interrupt enable */
627 #define STM_USART_CR1_TCIE (6) /* Transmission complete interrupt enable */
628 #define STM_USART_CR1_RXNEIE (5) /* RXNE interrupt enable */
629 #define STM_USART_CR1_IDLEIE (4) /* IDLE interrupt enable */
630 #define STM_USART_CR1_TE (3) /* Transmitter enable */
631 #define STM_USART_CR1_RE (2) /* Receiver enable */
632 #define STM_USART_CR1_RWU (1) /* Receiver wakeup */
633 #define STM_USART_CR1_SBK (0) /* Send break */
635 #define STM_USART_CR2_LINEN (14) /* LIN mode enable */
636 #define STM_USART_CR2_STOP (12) /* STOP bits */
637 #define STM_USART_CR2_STOP_MASK 3UL
638 #define STM_USART_CR2_STOP_1 0
639 #define STM_USART_CR2_STOP_0_5 1
640 #define STM_USART_CR2_STOP_2 2
641 #define STM_USART_CR2_STOP_1_5 3
643 #define STM_USART_CR2_CLKEN (11) /* Clock enable */
644 #define STM_USART_CR2_CPOL (10) /* Clock polarity */
645 #define STM_USART_CR2_CPHA (9) /* Clock phase */
646 #define STM_USART_CR2_LBCL (8) /* Last bit clock pulse */
647 #define STM_USART_CR2_LBDIE (6) /* LIN break detection interrupt enable */
648 #define STM_USART_CR2_LBDL (5) /* lin break detection length */
649 #define STM_USART_CR2_ADD (0)
650 #define STM_USART_CR2_ADD_MASK 0xfUL
652 #define STM_USART_CR3_CTSIE (10) /* CTS interrupt enable */
653 #define STM_USART_CR3_CTSE (9) /* CTS enable */
654 #define STM_USART_CR3_RTSE (8) /* RTS enable */
655 #define STM_USART_CR3_DMAT (7) /* DMA enable transmitter */
656 #define STM_USART_CR3_DMAR (6) /* DMA enable receiver */
657 #define STM_USART_CR3_SCEN (5) /* Smartcard mode enable */
658 #define STM_USART_CR3_NACK (4) /* Smartcard NACK enable */
659 #define STM_USART_CR3_HDSEL (3) /* Half-duplex selection */
660 #define STM_USART_CR3_IRLP (2) /* IrDA low-power */
661 #define STM_USART_CR3_IREN (1) /* IrDA mode enable */
662 #define STM_USART_CR3_EIE (0) /* Error interrupt enable */
666 uint8_t reserved_20[0x40 - 0x20];
678 * Need a pull-up on a separate GPIO
680 #define STM_USB_EPR_CTR_RX 15
681 #define STM_USB_EPR_CTR_RX_WRITE_INVARIANT 1
682 #define STM_USB_EPR_DTOG_RX 14
683 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT 0
684 #define STM_USB_EPR_STAT_RX 12
685 #define STM_USB_EPR_STAT_RX_DISABLED 0
686 #define STM_USB_EPR_STAT_RX_STALL 1
687 #define STM_USB_EPR_STAT_RX_NAK 2
688 #define STM_USB_EPR_STAT_RX_VALID 3
689 #define STM_USB_EPR_STAT_RX_MASK 3UL
690 #define STM_USB_EPR_STAT_RX_WRITE_INVARIANT 0
691 #define STM_USB_EPR_SETUP 11
692 #define STM_USB_EPR_EP_TYPE 9
693 #define STM_USB_EPR_EP_TYPE_BULK 0
694 #define STM_USB_EPR_EP_TYPE_CONTROL 1
695 #define STM_USB_EPR_EP_TYPE_ISO 2
696 #define STM_USB_EPR_EP_TYPE_INTERRUPT 3
697 #define STM_USB_EPR_EP_TYPE_MASK 3UL
698 #define STM_USB_EPR_EP_KIND 8
699 #define STM_USB_EPR_EP_KIND_DBL_BUF 1 /* Bulk */
700 #define STM_USB_EPR_EP_KIND_STATUS_OUT 1 /* Control */
701 #define STM_USB_EPR_CTR_TX 7
702 #define STM_USB_CTR_TX_WRITE_INVARIANT 1
703 #define STM_USB_EPR_DTOG_TX 6
704 #define STM_USB_EPR_DTOG_TX_WRITE_INVARIANT 0
705 #define STM_USB_EPR_STAT_TX 4
706 #define STM_USB_EPR_STAT_TX_DISABLED 0
707 #define STM_USB_EPR_STAT_TX_STALL 1
708 #define STM_USB_EPR_STAT_TX_NAK 2
709 #define STM_USB_EPR_STAT_TX_VALID 3
710 #define STM_USB_EPR_STAT_TX_WRITE_INVARIANT 0
711 #define STM_USB_EPR_STAT_TX_MASK 3UL
712 #define STM_USB_EPR_EA 0
713 #define STM_USB_EPR_EA_MASK 0xfUL
715 #define STM_USB_CNTR_CTRM 15
716 #define STM_USB_CNTR_PMAOVRM 14
717 #define STM_USB_CNTR_ERRM 13
718 #define STM_USB_CNTR_WKUPM 12
719 #define STM_USB_CNTR_SUSPM 11
720 #define STM_USB_CNTR_RESETM 10
721 #define STM_USB_CNTR_SOFM 9
722 #define STM_USB_CNTR_ESOFM 8
723 #define STM_USB_CNTR_RESUME 4
724 #define STM_USB_CNTR_FSUSP 3
725 #define STM_USB_CNTR_LP_MODE 2
726 #define STM_USB_CNTR_PDWN 1
727 #define STM_USB_CNTR_FRES 0
729 #define STM_USB_ISTR_CTR 15
730 #define STM_USB_ISTR_PMAOVR 14
731 #define STM_USB_ISTR_ERR 13
732 #define STM_USB_ISTR_WKUP 12
733 #define STM_USB_ISTR_SUSP 11
734 #define STM_USB_ISTR_RESET 10
735 #define STM_USB_ISTR_SOF 9
736 #define STM_USB_ISTR_ESOF 8
737 #define STM_USB_ISTR_DIR 4
738 #define STM_USB_ISTR_EP_ID 0
739 #define STM_USB_ISTR_EP_ID_MASK 0xfUL
741 #define STM_USB_FNR_RXDP 15
742 #define STM_USB_FNR_RXDM 14
743 #define STM_USB_FNR_LCK 13
744 #define STM_USB_FNR_LSOF 11
745 #define STM_USB_FNR_LSOF_MASK 0x3UL
746 #define STM_USB_FNR_FN 0
747 #define STM_USB_FNR_FN_MASK 0x7ffUL
749 #define STM_USB_DADDR_EF 7
750 #define STM_USB_DADDR_ADD 0
751 #define STM_USB_DADDR_ADD_MASK 0x7fUL
753 extern struct stm_usb stm_usb;
755 #define stm_usb (*((struct stm_usb *) 0x40005c00))
774 #define STM_USB_BDT_COUNT_RX_BL_SIZE 15
775 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK 10
776 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK 0x1fUL
777 #define STM_USB_BDT_COUNT_RX_COUNT_RX 0
778 #define STM_USB_BDT_COUNT_RX_COUNT_RX_MASK 0x3ffUL
780 #define STM_USB_BDT_SIZE 8
782 extern uint8_t stm_usb_sram[] __attribute__ ((aligned(4)));
784 //#define stm_usb_sram ((uint8_t *)0x40006000)
786 struct stm_dma_channel {
794 #define STM_NUM_DMA 7
799 struct stm_dma_channel channel[STM_NUM_DMA];
802 extern struct stm_dma stm_dma;
804 #define stm_dma (*((struct stm_dma *) 0x40020000))
806 /* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
809 #define STM_DMA_INDEX(channel) ((channel) - 1)
811 #define STM_DMA_ISR(index) ((index) << 2)
812 #define STM_DMA_ISR_MASK 0xfUL
813 #define STM_DMA_ISR_TEIF 3
814 #define STM_DMA_ISR_HTIF 2
815 #define STM_DMA_ISR_TCIF 1
816 #define STM_DMA_ISR_GIF 0
818 #define STM_DMA_IFCR(index) ((index) << 2)
819 #define STM_DMA_IFCR_MASK 0xfUL
820 #define STM_DMA_IFCR_CTEIF 3
821 #define STM_DMA_IFCR_CHTIF 2
822 #define STM_DMA_IFCR_CTCIF 1
823 #define STM_DMA_IFCR_CGIF 0
825 #define STM_DMA_CCR_MEM2MEM (14)
827 #define STM_DMA_CCR_PL (12)
828 #define STM_DMA_CCR_PL_LOW (0)
829 #define STM_DMA_CCR_PL_MEDIUM (1)
830 #define STM_DMA_CCR_PL_HIGH (2)
831 #define STM_DMA_CCR_PL_VERY_HIGH (3)
832 #define STM_DMA_CCR_PL_MASK (3)
834 #define STM_DMA_CCR_MSIZE (10)
835 #define STM_DMA_CCR_MSIZE_8 (0)
836 #define STM_DMA_CCR_MSIZE_16 (1)
837 #define STM_DMA_CCR_MSIZE_32 (2)
838 #define STM_DMA_CCR_MSIZE_MASK (3)
840 #define STM_DMA_CCR_PSIZE (8)
841 #define STM_DMA_CCR_PSIZE_8 (0)
842 #define STM_DMA_CCR_PSIZE_16 (1)
843 #define STM_DMA_CCR_PSIZE_32 (2)
844 #define STM_DMA_CCR_PSIZE_MASK (3)
846 #define STM_DMA_CCR_MINC (7)
847 #define STM_DMA_CCR_PINC (6)
848 #define STM_DMA_CCR_CIRC (5)
849 #define STM_DMA_CCR_DIR (4)
850 #define STM_DMA_CCR_DIR_PER_TO_MEM 0
851 #define STM_DMA_CCR_DIR_MEM_TO_PER 1
852 #define STM_DMA_CCR_TEIE (3)
853 #define STM_DMA_CCR_HTIE (2)
854 #define STM_DMA_CCR_TCIE (1)
855 #define STM_DMA_CCR_EN (0)
857 #define STM_DMA_CHANNEL_ADC1 1
858 #define STM_DMA_CHANNEL_SPI1_RX 2
859 #define STM_DMA_CHANNEL_SPI1_TX 3
860 #define STM_DMA_CHANNEL_SPI2_RX 4
861 #define STM_DMA_CHANNEL_SPI2_TX 5
862 #define STM_DMA_CHANNEL_USART3_TX 2
863 #define STM_DMA_CHANNEL_USART3_RX 3
864 #define STM_DMA_CHANNEL_USART1_TX 4
865 #define STM_DMA_CHANNEL_USART1_RX 5
866 #define STM_DMA_CHANNEL_USART2_RX 6
867 #define STM_DMA_CHANNEL_USART2_TX 7
868 #define STM_DMA_CHANNEL_I2C2_TX 4
869 #define STM_DMA_CHANNEL_I2C2_RX 5
870 #define STM_DMA_CHANNEL_I2C1_TX 6
871 #define STM_DMA_CHANNEL_I2C1_RX 7
872 #define STM_DMA_CHANNEL_TIM1_CH1 2
873 #define STM_DMA_CHANNEL_TIM1_CH4 4
874 #define STM_DMA_CHANNEL_TIM1_TRIG 4
875 #define STM_DMA_CHANNEL_TIM1_COM 4
876 #define STM_DMA_CHANNEL_TIM1_UP 5
877 #define STM_DMA_CHANNEL_TIM1_CH3 6
878 #define STM_DMA_CHANNEL_TIM2_CH3 1
879 #define STM_DMA_CHANNEL_TIM2_UP 2
880 #define STM_DMA_CHANNEL_TIM2_CH1 5
881 #define STM_DMA_CHANNEL_TIM2_CH2 7
882 #define STM_DMA_CHANNEL_TIM2_CH4 7
883 #define STM_DMA_CHANNEL_TIM3_CH3 2
884 #define STM_DMA_CHANNEL_TIM3_CH4 3
885 #define STM_DMA_CHANNEL_TIM3_UP 3
886 #define STM_DMA_CHANNEL_TIM3_CH1 6
887 #define STM_DMA_CHANNEL_TIM3_TRIG 6
888 #define STM_DMA_CHANNEL_TIM4_CH1 1
889 #define STM_DMA_CHANNEL_TIM4_CH2 4
890 #define STM_DMA_CHANNEL_TIM4_CH3 5
891 #define STM_DMA_CHANNEL_TIM4_UP 7
893 /* high density, xl-density and connectivity devices also have dma2 */
895 #define STM_DMA2_CHANNEL_ADC3 5
896 #define STM_DMA2_CHANNEL_SPI3_RX 1
897 #define STM_DMA2_CHANNEL_SPI3_TX 2
898 #define STM_DMA2_CHANNEL_UART4_RX 3
899 #define STM_DMA2_CHANNEL_UART4_TX 5
900 #define STM_DMA2_CHANNEL_TIM5_CH4 1
901 #define STM_DMA2_CHANNEL_TIM5_TRIG 1
902 #define STM_DMA2_CHANNEL_TIM5_CH3 2
903 #define STM_DMA2_CHANNEL_TIM5_UP 2
904 #define STM_DMA2_CHANNEL_TIM5_CH2 4
905 #define STM_DMA2_CHANNEL_TIM5_CH1 5
906 #define STM_DMA2_CHANNEL_TIM6_UP 3
907 #define STM_DMA2_CHANNEL_DAC_CHANNEL1 3
908 #define STM_DMA2_CHANNEL_TIM7_UP 4
909 #define STM_DMA2_CHANNEL_DAC_CHANNEL2 4
910 #define STM_DMA2_CHANNEL_TIM8_CH3 1
911 #define STM_DMA2_CHANNEL_TIM8_UP 1
912 #define STM_DMA2_CHANNEL_TIM8_CH4 2
913 #define STM_DMA2_CHANNEL_TIM8_TRIG 2
914 #define STM_DMA2_CHANNEL_TIM8_COM 2
915 #define STM_DMA2_CHANNEL_TIM8_CH1 3
916 #define STM_DMA2_CHANNEL_TIM8_CH2 5
932 extern struct stm_spi stm_spi1, stm_spi2;
934 #define stm_spi1 (*((struct stm_spi *) 0x40013000))
935 #define stm_spi2 (*((struct stm_spi *) 0x40003800))
937 /* SPI channels go from 1 to 2, instead of 0 to 1 (sigh)
940 #define STM_NUM_SPI 2
942 #define STM_SPI_INDEX(channel) ((channel) - 1)
944 #define STM_SPI_CR1_BIDIMODE 15
945 #define STM_SPI_CR1_BIDIOE 14
946 #define STM_SPI_CR1_CRCEN 13
947 #define STM_SPI_CR1_CRCNEXT 12
948 #define STM_SPI_CR1_DFF 11
949 #define STM_SPI_CR1_RXONLY 10
950 #define STM_SPI_CR1_SSM 9
951 #define STM_SPI_CR1_SSI 8
952 #define STM_SPI_CR1_LSBFIRST 7
953 #define STM_SPI_CR1_SPE 6
954 #define STM_SPI_CR1_BR 3
955 #define STM_SPI_CR1_BR_PCLK_2 0
956 #define STM_SPI_CR1_BR_PCLK_4 1
957 #define STM_SPI_CR1_BR_PCLK_8 2
958 #define STM_SPI_CR1_BR_PCLK_16 3
959 #define STM_SPI_CR1_BR_PCLK_32 4
960 #define STM_SPI_CR1_BR_PCLK_64 5
961 #define STM_SPI_CR1_BR_PCLK_128 6
962 #define STM_SPI_CR1_BR_PCLK_256 7
963 #define STM_SPI_CR1_BR_MASK 7UL
965 #define STM_SPI_CR1_MSTR 2
966 #define STM_SPI_CR1_CPOL 1
967 #define STM_SPI_CR1_CPHA 0
969 #define STM_SPI_CR2_TXEIE 7
970 #define STM_SPI_CR2_RXNEIE 6
971 #define STM_SPI_CR2_ERRIE 5
972 #define STM_SPI_CR2_SSOE 2
973 #define STM_SPI_CR2_TXDMAEN 1
974 #define STM_SPI_CR2_RXDMAEN 0
976 #define STM_SPI_SR_FRE 8
977 #define STM_SPI_SR_BSY 7
978 #define STM_SPI_SR_OVR 6
979 #define STM_SPI_SR_MODF 5
980 #define STM_SPI_SR_CRCERR 4
981 #define STM_SPI_SR_UDR 3
982 #define STM_SPI_SR_CHSIDE 2
983 #define STM_SPI_SR_TXE 1
984 #define STM_SPI_SR_RXNE 0
986 #define STM_NUM_I2C 2
988 #define STM_I2C_INDEX(channel) ((channel) - 1)
1002 extern struct stm_i2c stm_i2c1, stm_i2c2;
1004 #define stm_i2c1 (*((struct stm_i2c *) 0x40005400))
1005 #define stm_i2c2 (*((struct stm_i2c *) 0x40005800))
1007 #define STM_I2C_CR1_SWRST 15
1008 #define STM_I2C_CR1_ALERT 13
1009 #define STM_I2C_CR1_PEC 12
1010 #define STM_I2C_CR1_POS 11
1011 #define STM_I2C_CR1_ACK 10
1012 #define STM_I2C_CR1_STOP 9
1013 #define STM_I2C_CR1_START 8
1014 #define STM_I2C_CR1_NOSTRETCH 7
1015 #define STM_I2C_CR1_ENGC 6
1016 #define STM_I2C_CR1_ENPEC 5
1017 #define STM_I2C_CR1_ENARP 4
1018 #define STM_I2C_CR1_SMBTYPE 3
1019 #define STM_I2C_CR1_SMBUS 1
1020 #define STM_I2C_CR1_PE 0
1022 #define STM_I2C_CR2_LAST 12
1023 #define STM_I2C_CR2_DMAEN 11
1024 #define STM_I2C_CR2_ITBUFEN 10
1025 #define STM_I2C_CR2_ITEVTEN 9
1026 #define STM_I2C_CR2_ITERREN 8
1027 #define STM_I2C_CR2_FREQ 0
1028 #define STM_I2C_CR2_FREQ_MASK 0x3fUL
1030 #define STM_I2C_SR1_SMBALERT 15
1031 #define STM_I2C_SR1_TIMEOUT 14
1032 #define STM_I2C_SR1_PECERR 12
1033 #define STM_I2C_SR1_OVR 11
1034 #define STM_I2C_SR1_AF 10
1035 #define STM_I2C_SR1_ARLO 9
1036 #define STM_I2C_SR1_BERR 8
1037 #define STM_I2C_SR1_TXE 7
1038 #define STM_I2C_SR1_RXNE 6
1039 #define STM_I2C_SR1_STOPF 4
1040 #define STM_I2C_SR1_ADD10 3
1041 #define STM_I2C_SR1_BTF 2
1042 #define STM_I2C_SR1_ADDR 1
1043 #define STM_I2C_SR1_SB 0
1045 #define STM_I2C_SR2_PEC 8
1046 #define STM_I2C_SR2_PEC_MASK 0xff00UL
1047 #define STM_I2C_SR2_DUALF 7
1048 #define STM_I2C_SR2_SMBHOST 6
1049 #define STM_I2C_SR2_SMBDEFAULT 5
1050 #define STM_I2C_SR2_GENCALL 4
1051 #define STM_I2C_SR2_TRA 2
1052 #define STM_I2C_SR2_BUSY 1
1053 #define STM_I2C_SR2_MSL 0
1055 #define STM_I2C_CCR_FS 15
1056 #define STM_I2C_CCR_DUTY 14
1057 #define STM_I2C_CCR_CCR 0
1058 #define STM_I2C_CCR_MASK 0x7ffUL
1087 extern struct stm_adc stm_adc1;
1089 //#define stm_adc1 (*((struct stm_adc *) 0x40012400))
1091 #define STM_ADC_SQ_TEMP 16
1092 #define STM_ADC_SQ_V_REF 17
1094 #define STM_ADC_SR_STRT 4
1095 #define STM_ADC_SR_JSTRT 3
1096 #define STM_ADC_SR_JEOC 2
1097 #define STM_ADC_SR_EOC 1
1098 #define STM_ADC_SR_AWD 0
1100 #define STM_ADC_CR1_AWDEN 23
1101 #define STM_ADC_CR1_JAWDEN 22
1102 #define STM_ADC_CR1_DUALMOD 16
1103 # define STM_ADC_CR1_DUALMOD_INDEPENDENT 0
1104 # define STM_ADC_CR1_DUALMOD_COMB_REG_SIM_INJ_SIM 1
1105 # define STM_ADC_CR1_DUALMOD_COMB_REG_SIM_ALT_TRIG 2
1106 # define STM_ADC_CR1_DUALMOD_COMB_INJ_SIM_FAST_INT 3
1107 # define STM_ADC_CR1_DUALMOD_COMB_INJ_SIM_SLOW_INT 4
1108 # define STM_ADC_CR1_DUALMOD_INJ_SIM 5
1109 # define STM_ADC_CR1_DUALMOD_REG_SIM 6
1110 # define STM_ADC_CR1_DUALMOD_FAST_INT 7
1111 # define STM_ADC_CR1_DUALMOD_SLOW_INT 8
1112 # define STM_ADC_CR1_DUALMOD_ALT_TRIG 9
1114 #define STM_ADC_CR1_DISCNUM 13
1115 #define STM_ADC_CR1_DISCNUM_1 0
1116 #define STM_ADC_CR1_DISCNUM_2 1
1117 #define STM_ADC_CR1_DISCNUM_3 2
1118 #define STM_ADC_CR1_DISCNUM_4 3
1119 #define STM_ADC_CR1_DISCNUM_5 4
1120 #define STM_ADC_CR1_DISCNUM_6 5
1121 #define STM_ADC_CR1_DISCNUM_7 6
1122 #define STM_ADC_CR1_DISCNUM_8 7
1123 #define STM_ADC_CR1_DISCNUM_MASK 7UL
1124 #define STM_ADC_CR1_JDISCEN 12
1125 #define STM_ADC_CR1_DISCEN 11
1126 #define STM_ADC_CR1_JAUTO 10
1127 #define STM_ADC_CR1_AWDSGL 9
1128 #define STM_ADC_CR1_SCAN 8
1129 #define STM_ADC_CR1_JEOCIE 7
1130 #define STM_ADC_CR1_AWDIE 6
1131 #define STM_ADC_CR1_EOCIE 5
1132 #define STM_ADC_CR1_AWDCH 0
1133 #define STM_ADC_CR1_AWDCH_MASK 0x1fUL
1135 #define STM_ADC_CR2_TSVREFE 23
1136 #define STM_ADC_CR2_SWSTART 22
1137 #define STM_ADC_CR2_JWSTART 21
1138 #define STM_ADC_CR2_EXTTRIG 20
1139 #define STM_ADC_CR2_EXTSEL 17
1140 #define STM_ADC_CR2_EXTSEL_TIM1_CC1 0
1141 #define STM_ADC_CR2_EXTSEL_TIM1_CC2 1
1142 #define STM_ADC_CR2_EXTSEL_TIM1_CC3 2
1143 #define STM_ADC_CR2_EXTSEL_TIM2_CC2 3
1144 #define STM_ADC_CR2_EXTSEL_TIM3_TRGO 4
1145 #define STM_ADC_CR2_EXTSEL_TIM4_CC4 5
1146 #define STM_ADC_CR2_EXTSEL_EXTI 6
1147 #define STM_ADC_CR2_EXTSEL_SWSTART 7
1148 #define STM_ADC_CR2_EXTSEL_MASK 7UL
1149 #define STM_ADC_CR2_JEXTTRIG 15
1150 #define STM_ADC_CR2_JEXTSEL 12
1151 #define STM_ADC_CR2_JEXTSEL_TIM1_TRGO 0
1152 #define STM_ADC_CR2_JEXTSEL_TIM1_CC4 1
1153 #define STM_ADC_CR2_JEXTSEL_TIM2_TRGO 2
1154 #define STM_ADC_CR2_JEXTSEL_TIM2_CC1 3
1155 #define STM_ADC_CR2_JEXTSEL_TIM3_CC4 4
1156 #define STM_ADC_CR2_JEXTSEL_TIM4_TRGO 5
1157 #define STM_ADC_CR2_JEXTSEL_EXTI_15 6
1158 #define STM_ADC_CR2_JEXTSEL_JSWSTART 7
1159 #define STM_ADC_CR2_JEXTSEL_MASK 7UL
1160 #define STM_ADC_CR2_ALIGN 11
1161 #define STM_ADC_CR2_DMA 8
1162 #define STM_ADC_CR2_RSTCAL 3
1163 #define STM_ADC_CR2_CAL 2
1164 #define STM_ADC_CR2_CONT 1
1165 #define STM_ADC_CR2_ADON 0
1177 extern struct stm_exti stm_exti;
1179 #define stm_exti (*((struct stm_exti *) 0x40010400))
1182 stm_exticr_set(struct stm_gpio *gpio, int pin) {
1183 uint8_t reg = (uint8_t) (pin >> 2);
1184 uint8_t shift = (pin & 3) << 2;
1187 if (gpio == &stm_gpioa)
1188 val = STM_AFIO_EXTICR_PA;
1189 else if (gpio == &stm_gpiob)
1190 val = STM_AFIO_EXTICR_PB;
1191 else if (gpio == &stm_gpioc)
1192 val = STM_AFIO_EXTICR_PC;
1193 else if (gpio == &stm_gpiod)
1194 val = STM_AFIO_EXTICR_PD;
1195 else if (gpio == &stm_gpioe)
1196 val = STM_AFIO_EXTICR_PE;
1198 stm_afio.exticr[reg] = (stm_afio.exticr[reg] & (uint32_t) ~(0xf << shift)) | val << shift;
1228 extern struct stm_tim18 stm_tim1, stm_tim8;
1230 #define stm_tim1 (*((struct stm_tim18 *) 0x40012c00))
1231 #define stm_tim8 (*((struct stm_tim18 *) 0x40013400))
1233 #define STM_TIM18_CR1_CKD 8
1234 #define STM_TIM18_CR1_CKD_1 0
1235 #define STM_TIM18_CR1_CKD_2 1
1236 #define STM_TIM18_CR1_CKD_4 2
1237 #define STM_TIM18_CR1_CKD_MASK 3UL
1238 #define STM_TIM18_CR1_ARPE 7
1239 #define STM_TIM18_CR1_CMS 5
1240 #define STM_TIM18_CR1_CMS_EDGE 0
1241 #define STM_TIM18_CR1_CMS_CENTER_1 1
1242 #define STM_TIM18_CR1_CMS_CENTER_2 2
1243 #define STM_TIM18_CR1_CMS_CENTER_3 3
1244 #define STM_TIM18_CR1_CMS_MASK 3UL
1245 #define STM_TIM18_CR1_DIR 4
1246 #define STM_TIM18_CR1_DIR_UP 0
1247 #define STM_TIM18_CR1_DIR_DOWN 1
1248 #define STM_TIM18_CR1_OPM 3
1249 #define STM_TIM18_CR1_URS 2
1250 #define STM_TIM18_CR1_UDIS 1
1251 #define STM_TIM18_CR1_CEN 0
1253 #define STM_TIM18_CR2_TI1S 7
1254 #define STM_TIM18_CR2_MMS 4
1255 #define STM_TIM18_CR2_MMS_RESET 0
1256 #define STM_TIM18_CR2_MMS_ENABLE 1
1257 #define STM_TIM18_CR2_MMS_UPDATE 2
1258 #define STM_TIM18_CR2_MMS_COMPARE_PULSE 3
1259 #define STM_TIM18_CR2_MMS_COMPARE_OC1REF 4
1260 #define STM_TIM18_CR2_MMS_COMPARE_OC2REF 5
1261 #define STM_TIM18_CR2_MMS_COMPARE_OC3REF 6
1262 #define STM_TIM18_CR2_MMS_COMPARE_OC4REF 7
1263 #define STM_TIM18_CR2_MMS_MASK 7UL
1264 #define STM_TIM18_CR2_CCDS 3
1266 #define STM_TIM18_SMCR_ETP 15
1267 #define STM_TIM18_SMCR_ECE 14
1268 #define STM_TIM18_SMCR_ETPS 12
1269 #define STM_TIM18_SMCR_ETPS_OFF 0
1270 #define STM_TIM18_SMCR_ETPS_DIV_2 1
1271 #define STM_TIM18_SMCR_ETPS_DIV_4 2
1272 #define STM_TIM18_SMCR_ETPS_DIV_8 3
1273 #define STM_TIM18_SMCR_ETPS_MASK 3UL
1274 #define STM_TIM18_SMCR_ETF 8
1275 #define STM_TIM18_SMCR_ETF_NONE 0
1276 #define STM_TIM18_SMCR_ETF_INT_N_2 1
1277 #define STM_TIM18_SMCR_ETF_INT_N_4 2
1278 #define STM_TIM18_SMCR_ETF_INT_N_8 3
1279 #define STM_TIM18_SMCR_ETF_DTS_2_N_6 4
1280 #define STM_TIM18_SMCR_ETF_DTS_2_N_8 5
1281 #define STM_TIM18_SMCR_ETF_DTS_4_N_6 6
1282 #define STM_TIM18_SMCR_ETF_DTS_4_N_8 7
1283 #define STM_TIM18_SMCR_ETF_DTS_8_N_6 8
1284 #define STM_TIM18_SMCR_ETF_DTS_8_N_8 9
1285 #define STM_TIM18_SMCR_ETF_DTS_16_N_5 10
1286 #define STM_TIM18_SMCR_ETF_DTS_16_N_6 11
1287 #define STM_TIM18_SMCR_ETF_DTS_16_N_8 12
1288 #define STM_TIM18_SMCR_ETF_DTS_32_N_5 13
1289 #define STM_TIM18_SMCR_ETF_DTS_32_N_6 14
1290 #define STM_TIM18_SMCR_ETF_DTS_32_N_8 15
1291 #define STM_TIM18_SMCR_ETF_MASK 15UL
1292 #define STM_TIM18_SMCR_MSM 7
1293 #define STM_TIM18_SMCR_TS 4
1294 #define STM_TIM18_SMCR_TS_ITR0 0
1295 #define STM_TIM18_SMCR_TS_ITR1 1
1296 #define STM_TIM18_SMCR_TS_ITR2 2
1297 #define STM_TIM18_SMCR_TS_ITR3 3
1298 #define STM_TIM18_SMCR_TS_TI1F_ED 4
1299 #define STM_TIM18_SMCR_TS_TI1FP1 5
1300 #define STM_TIM18_SMCR_TS_TI2FP2 6
1301 #define STM_TIM18_SMCR_TS_ETRF 7
1302 #define STM_TIM18_SMCR_TS_MASK 7UL
1303 #define STM_TIM18_SMCR_SMS 0
1304 #define STM_TIM18_SMCR_SMS_DISABLE 0
1305 #define STM_TIM18_SMCR_SMS_ENCODER_MODE_1 1
1306 #define STM_TIM18_SMCR_SMS_ENCODER_MODE_2 2
1307 #define STM_TIM18_SMCR_SMS_ENCODER_MODE_3 3
1308 #define STM_TIM18_SMCR_SMS_RESET_MODE 4
1309 #define STM_TIM18_SMCR_SMS_GATED_MODE 5
1310 #define STM_TIM18_SMCR_SMS_TRIGGER_MODE 6
1311 #define STM_TIM18_SMCR_SMS_EXTERNAL_CLOCK 7
1312 #define STM_TIM18_SMCR_SMS_MASK 7UL
1314 #define STM_TIM18_DIER_TDE 14
1315 #define STM_TIM18_DIER_CC4DE 12
1316 #define STM_TIM18_DIER_CC3DE 11
1317 #define STM_TIM18_DIER_CC2DE 10
1318 #define STM_TIM18_DIER_CC1DE 9
1319 #define STM_TIM18_DIER_UDE 8
1321 #define STM_TIM18_DIER_TIE 6
1322 #define STM_TIM18_DIER_CC4IE 4
1323 #define STM_TIM18_DIER_CC3IE 3
1324 #define STM_TIM18_DIER_CC2IE 2
1325 #define STM_TIM18_DIER_CC1IE 1
1326 #define STM_TIM18_DIER_UIE 0
1328 #define STM_TIM18_SR_CC4OF 12
1329 #define STM_TIM18_SR_CC3OF 11
1330 #define STM_TIM18_SR_CC2OF 10
1331 #define STM_TIM18_SR_CC1OF 9
1332 #define STM_TIM18_SR_TIF 6
1333 #define STM_TIM18_SR_CC4IF 4
1334 #define STM_TIM18_SR_CC3IF 3
1335 #define STM_TIM18_SR_CC2IF 2
1336 #define STM_TIM18_SR_CC1IF 1
1337 #define STM_TIM18_SR_UIF 0
1339 #define STM_TIM18_EGR_TG 6
1340 #define STM_TIM18_EGR_CC4G 4
1341 #define STM_TIM18_EGR_CC3G 3
1342 #define STM_TIM18_EGR_CC2G 2
1343 #define STM_TIM18_EGR_CC1G 1
1344 #define STM_TIM18_EGR_UG 0
1346 #define STM_TIM18_CCMR1_OC2CE 15
1347 #define STM_TIM18_CCMR1_OC2M 12
1348 #define STM_TIM18_CCMR1_OC2M_FROZEN 0
1349 #define STM_TIM18_CCMR1_OC2M_SET_HIGH_ON_MATCH 1
1350 #define STM_TIM18_CCMR1_OC2M_SET_LOW_ON_MATCH 2
1351 #define STM_TIM18_CCMR1_OC2M_TOGGLE 3
1352 #define STM_TIM18_CCMR1_OC2M_FORCE_LOW 4
1353 #define STM_TIM18_CCMR1_OC2M_FORCE_HIGH 5
1354 #define STM_TIM18_CCMR1_OC2M_PWM_MODE_1 6
1355 #define STM_TIM18_CCMR1_OC2M_PWM_MODE_2 7
1356 #define STM_TIM18_CCMR1_OC2M_MASK 7UL
1357 #define STM_TIM18_CCMR1_OC2PE 11
1358 #define STM_TIM18_CCMR1_OC2FE 10
1359 #define STM_TIM18_CCMR1_CC2S 8
1360 #define STM_TIM18_CCMR1_CC2S_OUTPUT 0
1361 #define STM_TIM18_CCMR1_CC2S_INPUT_TI2 1
1362 #define STM_TIM18_CCMR1_CC2S_INPUT_TI1 2
1363 #define STM_TIM18_CCMR1_CC2S_INPUT_TRC 3
1364 #define STM_TIM18_CCMR1_CC2S_MASK 3UL
1366 #define STM_TIM18_CCMR1_OC1CE 7
1367 #define STM_TIM18_CCMR1_OC1M 4
1368 #define STM_TIM18_CCMR1_OC1M_FROZEN 0
1369 #define STM_TIM18_CCMR1_OC1M_SET_HIGH_ON_MATCH 1
1370 #define STM_TIM18_CCMR1_OC1M_SET_LOW_ON_MATCH 2
1371 #define STM_TIM18_CCMR1_OC1M_TOGGLE 3
1372 #define STM_TIM18_CCMR1_OC1M_FORCE_LOW 4
1373 #define STM_TIM18_CCMR1_OC1M_FORCE_HIGH 5
1374 #define STM_TIM18_CCMR1_OC1M_PWM_MODE_1 6
1375 #define STM_TIM18_CCMR1_OC1M_PWM_MODE_2 7
1376 #define STM_TIM18_CCMR1_OC1M_MASK 7UL
1377 #define STM_TIM18_CCMR1_OC1PE 3
1378 #define STM_TIM18_CCMR1_OC1FE 2
1379 #define STM_TIM18_CCMR1_CC1S 0
1380 #define STM_TIM18_CCMR1_CC1S_OUTPUT 0
1381 #define STM_TIM18_CCMR1_CC1S_INPUT_TI1 1
1382 #define STM_TIM18_CCMR1_CC1S_INPUT_TI2 2
1383 #define STM_TIM18_CCMR1_CC1S_INPUT_TRC 3
1384 #define STM_TIM18_CCMR1_CC1S_MASK 3UL
1386 #define STM_TIM18_CCMR1_IC2F 12
1387 #define STM_TIM18_CCMR1_IC2F_NONE 0
1388 #define STM_TIM18_CCMR1_IC2F_CK_INT_N_2 1
1389 #define STM_TIM18_CCMR1_IC2F_CK_INT_N_4 2
1390 #define STM_TIM18_CCMR1_IC2F_CK_INT_N_8 3
1391 #define STM_TIM18_CCMR1_IC2F_DTS_2_N_6 4
1392 #define STM_TIM18_CCMR1_IC2F_DTS_2_N_8 5
1393 #define STM_TIM18_CCMR1_IC2F_DTS_4_N_6 6
1394 #define STM_TIM18_CCMR1_IC2F_DTS_4_N_8 7
1395 #define STM_TIM18_CCMR1_IC2F_DTS_8_N_6 8
1396 #define STM_TIM18_CCMR1_IC2F_DTS_8_N_8 9
1397 #define STM_TIM18_CCMR1_IC2F_DTS_16_N_5 10
1398 #define STM_TIM18_CCMR1_IC2F_DTS_16_N_6 11
1399 #define STM_TIM18_CCMR1_IC2F_DTS_16_N_8 12
1400 #define STM_TIM18_CCMR1_IC2F_DTS_32_N_5 13
1401 #define STM_TIM18_CCMR1_IC2F_DTS_32_N_6 14
1402 #define STM_TIM18_CCMR1_IC2F_DTS_32_N_8 15
1403 #define STM_TIM18_CCMR1_IC2PSC 10
1404 #define STM_TIM18_CCMR1_IC2PSC_NONE 0
1405 #define STM_TIM18_CCMR1_IC2PSC_2 1
1406 #define STM_TIM18_CCMR1_IC2PSC_4 2
1407 #define STM_TIM18_CCMR1_IC2PSC_8 3
1408 #define STM_TIM18_CCMR1_IC1F 4
1409 #define STM_TIM18_CCMR1_IC1F_NONE 0
1410 #define STM_TIM18_CCMR1_IC1F_CK_INT_N_2 1
1411 #define STM_TIM18_CCMR1_IC1F_CK_INT_N_4 2
1412 #define STM_TIM18_CCMR1_IC1F_CK_INT_N_8 3
1413 #define STM_TIM18_CCMR1_IC1F_DTS_2_N_6 4
1414 #define STM_TIM18_CCMR1_IC1F_DTS_2_N_8 5
1415 #define STM_TIM18_CCMR1_IC1F_DTS_4_N_6 6
1416 #define STM_TIM18_CCMR1_IC1F_DTS_4_N_8 7
1417 #define STM_TIM18_CCMR1_IC1F_DTS_8_N_6 8
1418 #define STM_TIM18_CCMR1_IC1F_DTS_8_N_8 9
1419 #define STM_TIM18_CCMR1_IC1F_DTS_16_N_5 10
1420 #define STM_TIM18_CCMR1_IC1F_DTS_16_N_6 11
1421 #define STM_TIM18_CCMR1_IC1F_DTS_16_N_8 12
1422 #define STM_TIM18_CCMR1_IC1F_DTS_32_N_5 13
1423 #define STM_TIM18_CCMR1_IC1F_DTS_32_N_6 14
1424 #define STM_TIM18_CCMR1_IC1F_DTS_32_N_8 15
1425 #define STM_TIM18_CCMR1_IC1PSC 2
1426 #define STM_TIM18_CCMR1_IC1PSC_NONE 0
1427 #define STM_TIM18_CCMR1_IC1PSC_2 1
1428 #define STM_TIM18_CCMR1_IC1PSC_4 2
1429 #define STM_TIM18_CCMR1_IC1PSC_8 3
1431 #define STM_TIM18_CCMR2_OC4CE 15
1432 #define STM_TIM18_CCMR2_OC4M 12
1433 #define STM_TIM18_CCMR2_OC4M_FROZEN 0
1434 #define STM_TIM18_CCMR2_OC4M_SET_HIGH_ON_MATCH 1
1435 #define STM_TIM18_CCMR2_OC4M_SET_LOW_ON_MATCH 2
1436 #define STM_TIM18_CCMR2_OC4M_TOGGLE 3
1437 #define STM_TIM18_CCMR2_OC4M_FORCE_LOW 4
1438 #define STM_TIM18_CCMR2_OC4M_FORCE_HIGH 5
1439 #define STM_TIM18_CCMR2_OC4M_PWM_MODE_1 6
1440 #define STM_TIM18_CCMR2_OC4M_PWM_MODE_2 7
1441 #define STM_TIM18_CCMR2_OC4M_MASK 7UL
1442 #define STM_TIM18_CCMR2_OC4PE 11
1443 #define STM_TIM18_CCMR2_OC4FE 10
1444 #define STM_TIM18_CCMR2_CC4S 8
1445 #define STM_TIM18_CCMR2_CC4S_OUTPUT 0
1446 #define STM_TIM18_CCMR2_CC4S_INPUT_TI4 1
1447 #define STM_TIM18_CCMR2_CC4S_INPUT_TI3 2
1448 #define STM_TIM18_CCMR2_CC4S_INPUT_TRC 3
1449 #define STM_TIM18_CCMR2_CC4S_MASK 3UL
1451 #define STM_TIM18_CCMR2_OC3CE 7
1452 #define STM_TIM18_CCMR2_OC3M 4
1453 #define STM_TIM18_CCMR2_OC3M_FROZEN 0
1454 #define STM_TIM18_CCMR2_OC3M_SET_HIGH_ON_MATCH 1
1455 #define STM_TIM18_CCMR2_OC3M_SET_LOW_ON_MATCH 2
1456 #define STM_TIM18_CCMR2_OC3M_TOGGLE 3
1457 #define STM_TIM18_CCMR2_OC3M_FORCE_LOW 4
1458 #define STM_TIM18_CCMR2_OC3M_FORCE_HIGH 5
1459 #define STM_TIM18_CCMR2_OC3M_PWM_MODE_1 6
1460 #define STM_TIM18_CCMR2_OC3M_PWM_MODE_2 7
1461 #define STM_TIM18_CCMR2_OC3M_MASK 7UL
1462 #define STM_TIM18_CCMR2_OC3PE 3
1463 #define STM_TIM18_CCMR2_OC3FE 2
1464 #define STM_TIM18_CCMR2_CC3S 0
1465 #define STM_TIM18_CCMR2_CC3S_OUTPUT 0
1466 #define STM_TIM18_CCMR2_CC3S_INPUT_TI3 1
1467 #define STM_TIM18_CCMR2_CC3S_INPUT_TI4 2
1468 #define STM_TIM18_CCMR2_CC3S_INPUT_TRC 3
1469 #define STM_TIM18_CCMR2_CC3S_MASK 3UL
1471 #define STM_TIM18_CCER_CC4NP 15
1472 #define STM_TIM18_CCER_CC4P 13
1473 #define STM_TIM18_CCER_CC4P_ACTIVE_HIGH 0
1474 #define STM_TIM18_CCER_CC4P_ACTIVE_LOW 1
1475 #define STM_TIM18_CCER_CC4E 12
1476 #define STM_TIM18_CCER_CC3NP 11
1477 #define STM_TIM18_CCER_CC3P 9
1478 #define STM_TIM18_CCER_CC3P_ACTIVE_HIGH 0
1479 #define STM_TIM18_CCER_CC3P_ACTIVE_LOW 1
1480 #define STM_TIM18_CCER_CC3E 8
1481 #define STM_TIM18_CCER_CC2NP 7
1482 #define STM_TIM18_CCER_CC2P 5
1483 #define STM_TIM18_CCER_CC2P_ACTIVE_HIGH 0
1484 #define STM_TIM18_CCER_CC2P_ACTIVE_LOW 1
1485 #define STM_TIM18_CCER_CC2E 4
1486 #define STM_TIM18_CCER_CC1NP 3
1487 #define STM_TIM18_CCER_CC1P 1
1488 #define STM_TIM18_CCER_CC1P_ACTIVE_HIGH 0
1489 #define STM_TIM18_CCER_CC1P_ACTIVE_LOW 1
1490 #define STM_TIM18_CCER_CC1E 0
1508 uint32_t reserved_30;
1514 uint32_t reserved_44;
1519 extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
1521 #define stm_tim2 (*((struct stm_tim234 *) 0x40000000))
1522 #define stm_tim3 (*((struct stm_tim234 *) 0x40000400))
1523 #define stm_tim4 (*((struct stm_tim234 *) 0x40000800))
1525 #define STM_TIM234_CR1_CKD 8
1526 #define STM_TIM234_CR1_CKD_1 0
1527 #define STM_TIM234_CR1_CKD_2 1
1528 #define STM_TIM234_CR1_CKD_4 2
1529 #define STM_TIM234_CR1_CKD_MASK 3UL
1530 #define STM_TIM234_CR1_ARPE 7
1531 #define STM_TIM234_CR1_CMS 5
1532 #define STM_TIM234_CR1_CMS_EDGE 0
1533 #define STM_TIM234_CR1_CMS_CENTER_1 1
1534 #define STM_TIM234_CR1_CMS_CENTER_2 2
1535 #define STM_TIM234_CR1_CMS_CENTER_3 3
1536 #define STM_TIM234_CR1_CMS_MASK 3UL
1537 #define STM_TIM234_CR1_DIR 4
1538 #define STM_TIM234_CR1_DIR_UP 0
1539 #define STM_TIM234_CR1_DIR_DOWN 1
1540 #define STM_TIM234_CR1_OPM 3
1541 #define STM_TIM234_CR1_URS 2
1542 #define STM_TIM234_CR1_UDIS 1
1543 #define STM_TIM234_CR1_CEN 0
1545 #define STM_TIM234_CR2_TI1S 7
1546 #define STM_TIM234_CR2_MMS 4
1547 #define STM_TIM234_CR2_MMS_RESET 0
1548 #define STM_TIM234_CR2_MMS_ENABLE 1
1549 #define STM_TIM234_CR2_MMS_UPDATE 2
1550 #define STM_TIM234_CR2_MMS_COMPARE_PULSE 3
1551 #define STM_TIM234_CR2_MMS_COMPARE_OC1REF 4
1552 #define STM_TIM234_CR2_MMS_COMPARE_OC2REF 5
1553 #define STM_TIM234_CR2_MMS_COMPARE_OC3REF 6
1554 #define STM_TIM234_CR2_MMS_COMPARE_OC4REF 7
1555 #define STM_TIM234_CR2_MMS_MASK 7UL
1556 #define STM_TIM234_CR2_CCDS 3
1558 #define STM_TIM234_SMCR_ETP 15
1559 #define STM_TIM234_SMCR_ECE 14
1560 #define STM_TIM234_SMCR_ETPS 12
1561 #define STM_TIM234_SMCR_ETPS_OFF 0
1562 #define STM_TIM234_SMCR_ETPS_DIV_2 1
1563 #define STM_TIM234_SMCR_ETPS_DIV_4 2
1564 #define STM_TIM234_SMCR_ETPS_DIV_8 3
1565 #define STM_TIM234_SMCR_ETPS_MASK 3UL
1566 #define STM_TIM234_SMCR_ETF 8
1567 #define STM_TIM234_SMCR_ETF_NONE 0
1568 #define STM_TIM234_SMCR_ETF_INT_N_2 1
1569 #define STM_TIM234_SMCR_ETF_INT_N_4 2
1570 #define STM_TIM234_SMCR_ETF_INT_N_8 3
1571 #define STM_TIM234_SMCR_ETF_DTS_2_N_6 4
1572 #define STM_TIM234_SMCR_ETF_DTS_2_N_8 5
1573 #define STM_TIM234_SMCR_ETF_DTS_4_N_6 6
1574 #define STM_TIM234_SMCR_ETF_DTS_4_N_8 7
1575 #define STM_TIM234_SMCR_ETF_DTS_8_N_6 8
1576 #define STM_TIM234_SMCR_ETF_DTS_8_N_8 9
1577 #define STM_TIM234_SMCR_ETF_DTS_16_N_5 10
1578 #define STM_TIM234_SMCR_ETF_DTS_16_N_6 11
1579 #define STM_TIM234_SMCR_ETF_DTS_16_N_8 12
1580 #define STM_TIM234_SMCR_ETF_DTS_32_N_5 13
1581 #define STM_TIM234_SMCR_ETF_DTS_32_N_6 14
1582 #define STM_TIM234_SMCR_ETF_DTS_32_N_8 15
1583 #define STM_TIM234_SMCR_ETF_MASK 15UL
1584 #define STM_TIM234_SMCR_MSM 7
1585 #define STM_TIM234_SMCR_TS 4
1586 #define STM_TIM234_SMCR_TS_ITR0 0
1587 #define STM_TIM234_SMCR_TS_ITR1 1
1588 #define STM_TIM234_SMCR_TS_ITR2 2
1589 #define STM_TIM234_SMCR_TS_ITR3 3
1590 #define STM_TIM234_SMCR_TS_TI1F_ED 4
1591 #define STM_TIM234_SMCR_TS_TI1FP1 5
1592 #define STM_TIM234_SMCR_TS_TI2FP2 6
1593 #define STM_TIM234_SMCR_TS_ETRF 7
1594 #define STM_TIM234_SMCR_TS_MASK 7UL
1595 #define STM_TIM234_SMCR_SMS 0
1596 #define STM_TIM234_SMCR_SMS_DISABLE 0
1597 #define STM_TIM234_SMCR_SMS_ENCODER_MODE_1 1
1598 #define STM_TIM234_SMCR_SMS_ENCODER_MODE_2 2
1599 #define STM_TIM234_SMCR_SMS_ENCODER_MODE_3 3
1600 #define STM_TIM234_SMCR_SMS_RESET_MODE 4
1601 #define STM_TIM234_SMCR_SMS_GATED_MODE 5
1602 #define STM_TIM234_SMCR_SMS_TRIGGER_MODE 6
1603 #define STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK 7
1604 #define STM_TIM234_SMCR_SMS_MASK 7UL
1606 #define STM_TIM234_DIER_TDE 14
1607 #define STM_TIM234_DIER_CC4DE 12
1608 #define STM_TIM234_DIER_CC3DE 11
1609 #define STM_TIM234_DIER_CC2DE 10
1610 #define STM_TIM234_DIER_CC1DE 9
1611 #define STM_TIM234_DIER_UDE 8
1613 #define STM_TIM234_DIER_TIE 6
1614 #define STM_TIM234_DIER_CC4IE 4
1615 #define STM_TIM234_DIER_CC3IE 3
1616 #define STM_TIM234_DIER_CC2IE 2
1617 #define STM_TIM234_DIER_CC1IE 1
1618 #define STM_TIM234_DIER_UIE 0
1620 #define STM_TIM234_SR_CC4OF 12
1621 #define STM_TIM234_SR_CC3OF 11
1622 #define STM_TIM234_SR_CC2OF 10
1623 #define STM_TIM234_SR_CC1OF 9
1624 #define STM_TIM234_SR_TIF 6
1625 #define STM_TIM234_SR_CC4IF 4
1626 #define STM_TIM234_SR_CC3IF 3
1627 #define STM_TIM234_SR_CC2IF 2
1628 #define STM_TIM234_SR_CC1IF 1
1629 #define STM_TIM234_SR_UIF 0
1631 #define STM_TIM234_EGR_TG 6
1632 #define STM_TIM234_EGR_CC4G 4
1633 #define STM_TIM234_EGR_CC3G 3
1634 #define STM_TIM234_EGR_CC2G 2
1635 #define STM_TIM234_EGR_CC1G 1
1636 #define STM_TIM234_EGR_UG 0
1638 #define STM_TIM234_CCMR1_OC2CE 15
1639 #define STM_TIM234_CCMR1_OC2M 12
1640 #define STM_TIM234_CCMR1_OC2M_FROZEN 0
1641 #define STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH 1
1642 #define STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH 2
1643 #define STM_TIM234_CCMR1_OC2M_TOGGLE 3
1644 #define STM_TIM234_CCMR1_OC2M_FORCE_LOW 4
1645 #define STM_TIM234_CCMR1_OC2M_FORCE_HIGH 5
1646 #define STM_TIM234_CCMR1_OC2M_PWM_MODE_1 6
1647 #define STM_TIM234_CCMR1_OC2M_PWM_MODE_2 7
1648 #define STM_TIM234_CCMR1_OC2M_MASK 7UL
1649 #define STM_TIM234_CCMR1_OC2PE 11
1650 #define STM_TIM234_CCMR1_OC2FE 10
1651 #define STM_TIM234_CCMR1_CC2S 8
1652 #define STM_TIM234_CCMR1_CC2S_OUTPUT 0
1653 #define STM_TIM234_CCMR1_CC2S_INPUT_TI2 1
1654 #define STM_TIM234_CCMR1_CC2S_INPUT_TI1 2
1655 #define STM_TIM234_CCMR1_CC2S_INPUT_TRC 3
1656 #define STM_TIM234_CCMR1_CC2S_MASK 3UL
1658 #define STM_TIM234_CCMR1_OC1CE 7
1659 #define STM_TIM234_CCMR1_OC1M 4
1660 #define STM_TIM234_CCMR1_OC1M_FROZEN 0
1661 #define STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH 1
1662 #define STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH 2
1663 #define STM_TIM234_CCMR1_OC1M_TOGGLE 3
1664 #define STM_TIM234_CCMR1_OC1M_FORCE_LOW 4
1665 #define STM_TIM234_CCMR1_OC1M_FORCE_HIGH 5
1666 #define STM_TIM234_CCMR1_OC1M_PWM_MODE_1 6
1667 #define STM_TIM234_CCMR1_OC1M_PWM_MODE_2 7
1668 #define STM_TIM234_CCMR1_OC1M_MASK 7UL
1669 #define STM_TIM234_CCMR1_OC1PE 3
1670 #define STM_TIM234_CCMR1_OC1FE 2
1671 #define STM_TIM234_CCMR1_CC1S 0
1672 #define STM_TIM234_CCMR1_CC1S_OUTPUT 0
1673 #define STM_TIM234_CCMR1_CC1S_INPUT_TI1 1
1674 #define STM_TIM234_CCMR1_CC1S_INPUT_TI2 2
1675 #define STM_TIM234_CCMR1_CC1S_INPUT_TRC 3
1676 #define STM_TIM234_CCMR1_CC1S_MASK 3UL
1678 #define STM_TIM234_CCMR1_IC2F 12
1679 #define STM_TIM234_CCMR1_IC2F_NONE 0
1680 #define STM_TIM234_CCMR1_IC2F_CK_INT_N_2 1
1681 #define STM_TIM234_CCMR1_IC2F_CK_INT_N_4 2
1682 #define STM_TIM234_CCMR1_IC2F_CK_INT_N_8 3
1683 #define STM_TIM234_CCMR1_IC2F_DTS_2_N_6 4
1684 #define STM_TIM234_CCMR1_IC2F_DTS_2_N_8 5
1685 #define STM_TIM234_CCMR1_IC2F_DTS_4_N_6 6
1686 #define STM_TIM234_CCMR1_IC2F_DTS_4_N_8 7
1687 #define STM_TIM234_CCMR1_IC2F_DTS_8_N_6 8
1688 #define STM_TIM234_CCMR1_IC2F_DTS_8_N_8 9
1689 #define STM_TIM234_CCMR1_IC2F_DTS_16_N_5 10
1690 #define STM_TIM234_CCMR1_IC2F_DTS_16_N_6 11
1691 #define STM_TIM234_CCMR1_IC2F_DTS_16_N_8 12
1692 #define STM_TIM234_CCMR1_IC2F_DTS_32_N_5 13
1693 #define STM_TIM234_CCMR1_IC2F_DTS_32_N_6 14
1694 #define STM_TIM234_CCMR1_IC2F_DTS_32_N_8 15
1695 #define STM_TIM234_CCMR1_IC2PSC 10
1696 #define STM_TIM234_CCMR1_IC2PSC_NONE 0
1697 #define STM_TIM234_CCMR1_IC2PSC_2 1
1698 #define STM_TIM234_CCMR1_IC2PSC_4 2
1699 #define STM_TIM234_CCMR1_IC2PSC_8 3
1700 #define STM_TIM234_CCMR1_IC1F 4
1701 #define STM_TIM234_CCMR1_IC1F_NONE 0
1702 #define STM_TIM234_CCMR1_IC1F_CK_INT_N_2 1
1703 #define STM_TIM234_CCMR1_IC1F_CK_INT_N_4 2
1704 #define STM_TIM234_CCMR1_IC1F_CK_INT_N_8 3
1705 #define STM_TIM234_CCMR1_IC1F_DTS_2_N_6 4
1706 #define STM_TIM234_CCMR1_IC1F_DTS_2_N_8 5
1707 #define STM_TIM234_CCMR1_IC1F_DTS_4_N_6 6
1708 #define STM_TIM234_CCMR1_IC1F_DTS_4_N_8 7
1709 #define STM_TIM234_CCMR1_IC1F_DTS_8_N_6 8
1710 #define STM_TIM234_CCMR1_IC1F_DTS_8_N_8 9
1711 #define STM_TIM234_CCMR1_IC1F_DTS_16_N_5 10
1712 #define STM_TIM234_CCMR1_IC1F_DTS_16_N_6 11
1713 #define STM_TIM234_CCMR1_IC1F_DTS_16_N_8 12
1714 #define STM_TIM234_CCMR1_IC1F_DTS_32_N_5 13
1715 #define STM_TIM234_CCMR1_IC1F_DTS_32_N_6 14
1716 #define STM_TIM234_CCMR1_IC1F_DTS_32_N_8 15
1717 #define STM_TIM234_CCMR1_IC1PSC 2
1718 #define STM_TIM234_CCMR1_IC1PSC_NONE 0
1719 #define STM_TIM234_CCMR1_IC1PSC_2 1
1720 #define STM_TIM234_CCMR1_IC1PSC_4 2
1721 #define STM_TIM234_CCMR1_IC1PSC_8 3
1723 #define STM_TIM234_CCMR2_OC4CE 15
1724 #define STM_TIM234_CCMR2_OC4M 12
1725 #define STM_TIM234_CCMR2_OC4M_FROZEN 0
1726 #define STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH 1
1727 #define STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH 2
1728 #define STM_TIM234_CCMR2_OC4M_TOGGLE 3
1729 #define STM_TIM234_CCMR2_OC4M_FORCE_LOW 4
1730 #define STM_TIM234_CCMR2_OC4M_FORCE_HIGH 5
1731 #define STM_TIM234_CCMR2_OC4M_PWM_MODE_1 6
1732 #define STM_TIM234_CCMR2_OC4M_PWM_MODE_2 7
1733 #define STM_TIM234_CCMR2_OC4M_MASK 7UL
1734 #define STM_TIM234_CCMR2_OC4PE 11
1735 #define STM_TIM234_CCMR2_OC4FE 10
1736 #define STM_TIM234_CCMR2_CC4S 8
1737 #define STM_TIM234_CCMR2_CC4S_OUTPUT 0
1738 #define STM_TIM234_CCMR2_CC4S_INPUT_TI4 1
1739 #define STM_TIM234_CCMR2_CC4S_INPUT_TI3 2
1740 #define STM_TIM234_CCMR2_CC4S_INPUT_TRC 3
1741 #define STM_TIM234_CCMR2_CC4S_MASK 3UL
1743 #define STM_TIM234_CCMR2_OC3CE 7
1744 #define STM_TIM234_CCMR2_OC3M 4
1745 #define STM_TIM234_CCMR2_OC3M_FROZEN 0
1746 #define STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH 1
1747 #define STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH 2
1748 #define STM_TIM234_CCMR2_OC3M_TOGGLE 3
1749 #define STM_TIM234_CCMR2_OC3M_FORCE_LOW 4
1750 #define STM_TIM234_CCMR2_OC3M_FORCE_HIGH 5
1751 #define STM_TIM234_CCMR2_OC3M_PWM_MODE_1 6
1752 #define STM_TIM234_CCMR2_OC3M_PWM_MODE_2 7
1753 #define STM_TIM234_CCMR2_OC3M_MASK 7UL
1754 #define STM_TIM234_CCMR2_OC3PE 3
1755 #define STM_TIM234_CCMR2_OC3FE 2
1756 #define STM_TIM234_CCMR2_CC3S 0
1757 #define STM_TIM234_CCMR2_CC3S_OUTPUT 0
1758 #define STM_TIM234_CCMR2_CC3S_INPUT_TI3 1
1759 #define STM_TIM234_CCMR2_CC3S_INPUT_TI4 2
1760 #define STM_TIM234_CCMR2_CC3S_INPUT_TRC 3
1761 #define STM_TIM234_CCMR2_CC3S_MASK 3UL
1763 #define STM_TIM234_CCER_CC4NP 15
1764 #define STM_TIM234_CCER_CC4P 13
1765 #define STM_TIM234_CCER_CC4P_ACTIVE_HIGH 0
1766 #define STM_TIM234_CCER_CC4P_ACTIVE_LOW 1
1767 #define STM_TIM234_CCER_CC4E 12
1768 #define STM_TIM234_CCER_CC3NP 11
1769 #define STM_TIM234_CCER_CC3P 9
1770 #define STM_TIM234_CCER_CC3P_ACTIVE_HIGH 0
1771 #define STM_TIM234_CCER_CC3P_ACTIVE_LOW 1
1772 #define STM_TIM234_CCER_CC3E 8
1773 #define STM_TIM234_CCER_CC2NP 7
1774 #define STM_TIM234_CCER_CC2P 5
1775 #define STM_TIM234_CCER_CC2P_ACTIVE_HIGH 0
1776 #define STM_TIM234_CCER_CC2P_ACTIVE_LOW 1
1777 #define STM_TIM234_CCER_CC2E 4
1778 #define STM_TIM234_CCER_CC1NP 3
1779 #define STM_TIM234_CCER_CC1P 1
1780 #define STM_TIM234_CCER_CC1P_ACTIVE_HIGH 0
1781 #define STM_TIM234_CCER_CC1P_ACTIVE_LOW 1
1782 #define STM_TIM234_CCER_CC1E 0
1787 uint32_t _unused_08;
1792 uint32_t _unused_18;
1793 uint32_t _unused_1c;
1795 uint32_t _unused_20;
1801 extern struct stm_tim67 stm_tim6;
1803 #define STM_TIM67_CR1_ARPE (7)
1804 #define STM_TIM67_CR1_OPM (3)
1805 #define STM_TIM67_CR1_URS (2)
1806 #define STM_TIM67_CR1_UDIS (1)
1807 #define STM_TIM67_CR1_CEN (0)
1809 #define STM_TIM67_CR2_MMS (4)
1810 #define STM_TIM67_CR2_MMS_RESET 0
1811 #define STM_TIM67_CR2_MMS_ENABLE 1
1812 #define STM_TIM67_CR2_MMS_UPDATE 2
1813 #define STM_TIM67_CR2_MMS_MASK 7UL
1815 #define STM_TIM67_DIER_UDE (8)
1816 #define STM_TIM67_DIER_UIE (0)
1818 #define STM_TIM67_SR_UIF (0)
1820 #define STM_TIM67_EGR_UG (0)
1822 #define isr_decl(name) void stm_ ## name ## _isr(void)
1828 isr_decl(hardfault);
1829 isr_decl(memmanage);
1831 isr_decl(usagefault);
1838 isr_decl(tamper_stamp);
1847 isr_decl(dma1_channel1);
1848 isr_decl(dma1_channel2);
1849 isr_decl(dma1_channel3);
1850 isr_decl(dma1_channel4);
1851 isr_decl(dma1_channel5);
1852 isr_decl(dma1_channel6);
1853 isr_decl(dma1_channel7);
1862 isr_decl(tim1_trg_com);
1876 isr_decl(exti15_10);
1877 isr_decl(rtc_alarm);
1878 isr_decl(usb_wakeup);
1881 isr_decl(tim8_trg_com);
1892 isr_decl(dma2_channel1);
1893 isr_decl(dma2_channel2);
1894 isr_decl(dma2_channel3);
1895 isr_decl(dma2_channel4_5);
1899 #define STM_ISR_WWDG_POS 0
1900 #define STM_ISR_PVD_POS 1
1901 #define STM_ISR_TAMPER_STAMP_POS 2
1902 #define STM_ISR_RTC_WKUP_POS 3
1903 #define STM_ISR_FLASH_POS 4
1904 #define STM_ISR_RCC_POS 5
1905 #define STM_ISR_EXTI0_POS 6
1906 #define STM_ISR_EXTI1_POS 7
1907 #define STM_ISR_EXTI2_POS 8
1908 #define STM_ISR_EXTI3_POS 9
1909 #define STM_ISR_EXTI4_POS 10
1910 #define STM_ISR_DMA1_CHANNEL1_POS 11
1911 #define STM_ISR_DMA1_CHANNEL2_POS 12
1912 #define STM_ISR_DMA1_CHANNEL3_POS 13
1913 #define STM_ISR_DMA1_CHANNEL4_POS 14
1914 #define STM_ISR_DMA1_CHANNEL5_POS 15
1915 #define STM_ISR_DMA1_CHANNEL6_POS 16
1916 #define STM_ISR_DMA1_CHANNEL7_POS 17
1917 #define STM_ISR_ADC1_2_POS 18
1918 #define STM_ISR_USB_HP_POS 19
1919 #define STM_ISR_USB_LP_POS 20
1920 #define STM_ISR_CAN_RX1_POS 21
1921 #define STM_ISR_CAN_SCE_POS 22
1922 #define STM_ISR_EXTI9_5_POS 23
1923 #define STM_ISR_TIM1_BRK_POS 24
1924 #define STM_ISR_TIM1_UP_POS 25
1925 #define STM_ISR_TIM1_TRG_COM_POS 26
1926 #define STM_ISR_TIM1_CC_POS 27
1927 #define STM_ISR_TIM2_POS 28
1928 #define STM_ISR_TIM3_POS 29
1929 #define STM_ISR_TIM4_POS 30
1930 #define STM_ISR_I2C1_EV_POS 31
1931 #define STM_ISR_I2C1_ER_POS 32
1932 #define STM_ISR_I2C2_EV_POS 33
1933 #define STM_ISR_I2C2_ER_POS 34
1934 #define STM_ISR_SPI1_POS 35
1935 #define STM_ISR_SPI2_POS 36
1936 #define STM_ISR_USART1_POS 37
1937 #define STM_ISR_USART2_POS 38
1938 #define STM_ISR_USART3_POS 39
1939 #define STM_ISR_EXTI15_10_POS 40
1940 #define STM_ISR_RTC_ALARM_POS 41
1941 #define STM_ISR_USB_WAKEUP_POS 42
1942 #define STM_ISR_TIM8_BRK_POS 43
1943 #define STM_ISR_TIM8_UP_POS 44
1944 #define STM_ISR_TIM8_TRG_COM_POS 45
1945 #define STM_ISR_TIM8_CC_POS 46
1946 #define STM_ISR_ADC3_POS 47
1947 #define STM_ISR_FSMC_POS 48
1948 #define STM_ISR_SDIO_POS 49
1949 #define STM_ISR_TIM5_POS 50
1950 #define STM_ISR_SPI3_POS 51
1951 #define STM_ISR_UART4_POS 52
1952 #define STM_ISR_UART5_POS 53
1953 #define STM_ISR_TIM6_POS 54
1954 #define STM_ISR_TIM7_POS 55
1955 #define STM_ISR_DMA2_CHANNEL1_POS 56
1956 #define STM_ISR_DMA2_CHANNEL2_POS 57
1957 #define STM_ISR_DMA2_CHANNEL3_POS 58
1958 #define STM_ISR_DMA3_CHANNEL4_5_POS 59