2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 struct ao_i2c_stm_info {
24 struct stm_i2c *stm_i2c;
29 #define I2C_TIMEOUT 100
35 static uint8_t ao_i2c_state[STM_NUM_I2C];
36 static uint16_t ao_i2c_addr[STM_NUM_I2C];
37 uint8_t ao_i2c_mutex[STM_NUM_I2C];
39 # define I2C_HIGH_SLOW 5000 /* ns, 100kHz clock */
41 # define I2C_HIGH_FAST 2000 /* ns, 167kHz clock */
43 # define I2C_HIGH_FAST 1000 /* ns, 333kHz clock */
46 # define I2C_RISE_SLOW 500 /* ns */
47 # define I2C_RISE_FAST 100 /* ns */
49 /* Clock period in ns */
50 #define CYCLES(period) (((period) * (AO_PCLK1 / 1000)) / 1000000)
52 #define max(a,b) ((a) > (b) ? (a) : (b))
53 #define I2C_CCR_HIGH_SLOW max(4,CYCLES(I2C_HIGH_SLOW))
54 #define I2C_CCR_HIGH_FAST max(4,CYCLES(I2C_HIGH_FAST))
55 #define I2C_TRISE_SLOW (CYCLES(I2C_RISE_SLOW) + 1)
56 #define I2C_TRISE_FAST (CYCLES(I2C_RISE_FAST) + 1)
59 #define I2C_TRISE I2C_TRISE_FAST
60 #define I2C_CCR_HIGH I2C_CCR_HIGH_FAST
62 #define I2C_TRISE I2C_TRISE_SLOW
63 #define I2C_CCR_HIGH I2C_CCR_HIGH_SLOW
66 #define AO_STM_I2C_CR2_FREQ (AO_APB1CLK / 1000000)
68 #define AO_STM_I2C_CR1 ((0 << STM_I2C_CR1_SWRST) | \
69 (0 << STM_I2C_CR1_ALERT) | \
70 (0 << STM_I2C_CR1_PEC) | \
71 (0 << STM_I2C_CR1_POS) | \
72 (0 << STM_I2C_CR1_ACK) | \
73 (0 << STM_I2C_CR1_STOP) | \
74 (0 << STM_I2C_CR1_START) | \
75 (0 << STM_I2C_CR1_NOSTRETCH) | \
76 (0 << STM_I2C_CR1_ENGC) | \
77 (0 << STM_I2C_CR1_ENPEC) | \
78 (0 << STM_I2C_CR1_ENARP) | \
79 (0 << STM_I2C_CR1_SMBTYPE) | \
80 (0 << STM_I2C_CR1_SMBUS) | \
81 (1 << STM_I2C_CR1_PE))
83 #define AO_STM_I2C_CR2 ((0 << STM_I2C_CR2_LAST) | \
84 (0 << STM_I2C_CR2_DMAEN) | \
85 (0 << STM_I2C_CR2_ITBUFEN) | \
86 (0 << STM_I2C_CR2_ITEVTEN) | \
87 (0 << STM_I2C_CR2_ITERREN) | \
88 (AO_STM_I2C_CR2_FREQ << STM_I2C_CR2_FREQ))
90 static const struct ao_i2c_stm_info ao_i2c_stm_info[STM_NUM_I2C] = {
92 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_TX),
93 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_RX),
97 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_TX),
98 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_RX),
103 static uint8_t *ao_i2c_recv_data[STM_NUM_I2C];
104 static uint16_t ao_i2c_recv_len[STM_NUM_I2C];
105 static uint16_t ev_count;
108 ao_i2c_ev_isr(uint8_t index)
110 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
115 if (sr1 & (1 << STM_I2C_SR1_SB))
116 stm_i2c->dr = ao_i2c_addr[index];
117 if (sr1 & (1 << STM_I2C_SR1_ADDR)) {
118 stm_i2c->cr2 &= ~(1UL << STM_I2C_CR2_ITEVTEN);
119 ao_i2c_state[index] = I2C_RUNNING;
120 ao_wakeup(&ao_i2c_state[index]);
122 if (sr1 & (1 << STM_I2C_SR1_BTF)) {
123 stm_i2c->cr2 &= ~(1UL << STM_I2C_CR2_ITEVTEN);
124 ao_wakeup(&ao_i2c_state[index]);
126 if (sr1 & (1 << STM_I2C_SR1_RXNE)) {
127 if (ao_i2c_recv_len[index]) {
128 *(ao_i2c_recv_data[index]++) = (uint8_t) stm_i2c->dr;
129 if (!--ao_i2c_recv_len[index])
130 ao_wakeup(&ao_i2c_recv_len[index]);
135 void stm_i2c1_ev_isr(void) { ao_i2c_ev_isr(0); }
136 void stm_i2c2_ev_isr(void) { ao_i2c_ev_isr(1); }
139 ao_i2c_er_isr(uint8_t index)
141 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
145 if (sr1 & (1 << STM_I2C_SR1_AF)) {
146 ao_i2c_state[index] = I2C_ERROR;
147 stm_i2c->sr1 = sr1 & ~(1UL << STM_I2C_SR1_AF);
148 ao_wakeup(&ao_i2c_state[index]);
152 void stm_i2c1_er_isr(void) { ao_i2c_er_isr(0); }
153 void stm_i2c2_er_isr(void) { ao_i2c_er_isr(1); }
156 ao_i2c_get(uint8_t index)
158 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
159 ao_mutex_get(&ao_i2c_mutex[index]);
166 ao_i2c_put(uint8_t index)
168 ao_mutex_put(&ao_i2c_mutex[index]);
172 ao_i2c_start(uint8_t index, uint16_t addr)
174 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
177 ao_i2c_state[index] = I2C_IDLE;
178 ao_i2c_addr[index] = addr;
179 stm_i2c->cr2 = AO_STM_I2C_CR2;
180 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_START);
181 for (t = 0; t < I2C_TIMEOUT; t++) {
182 if (!(stm_i2c->cr1 & (1 << STM_I2C_CR1_START)))
185 ao_arch_block_interrupts();
186 stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN);
187 ao_i2c_ev_isr(index);
188 while (ao_i2c_state[index] == I2C_IDLE)
189 if (ao_sleep_for(&ao_i2c_state[index], AO_MS_TO_TICKS(250)))
191 ao_arch_release_interrupts();
192 return ao_i2c_state[index] == I2C_RUNNING;
196 ao_i2c_wait_stop(uint8_t index)
198 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
201 for (t = 0; t < I2C_TIMEOUT; t++) {
202 if (!(stm_i2c->cr1 & (1 << STM_I2C_CR1_STOP)))
206 ao_i2c_state[index] = I2C_IDLE;
210 ao_i2c_wait_addr(uint8_t index)
212 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
215 for (t = 0; t < I2C_TIMEOUT; t++)
216 if (!(stm_i2c->sr1 & (1 << STM_I2C_SR1_ADDR)))
219 printf ("wait_addr %d\n", t);
223 ao_i2c_send(void *block, uint16_t len, uint8_t index, uint8_t stop)
225 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
226 uint8_t tx_dma_index = ao_i2c_stm_info[index].tx_dma_index;
228 /* Clear any pending ADDR bit */
230 ao_i2c_wait_addr(index);
231 stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_DMAEN);
232 ao_dma_set_transfer(tx_dma_index,
236 (0 << STM_DMA_CCR_MEM2MEM) |
237 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
238 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
239 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
240 (1 << STM_DMA_CCR_MINC) |
241 (0 << STM_DMA_CCR_PINC) |
242 (0 << STM_DMA_CCR_CIRC) |
243 (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
245 ao_dma_start(tx_dma_index);
246 ao_arch_block_interrupts();
247 while (!ao_dma_done[tx_dma_index])
248 if (ao_sleep_for(&ao_dma_done[tx_dma_index], 1 + len))
250 ao_dma_done_transfer(tx_dma_index);
251 stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN);
252 while ((stm_i2c->sr1 & (1 << STM_I2C_SR1_BTF)) == 0)
253 if (ao_sleep_for(&ao_i2c_state[index], 1 + len))
255 stm_i2c->cr2 = AO_STM_I2C_CR2;
256 ao_arch_release_interrupts();
258 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
259 ao_i2c_wait_stop(index);
265 ao_i2c_recv_dma_isr(int index)
268 struct stm_i2c *stm_i2c = NULL;
270 for (i = 0; i < STM_NUM_I2C; i++)
271 if (index == ao_i2c_stm_info[i].rx_dma_index) {
272 stm_i2c = ao_i2c_stm_info[i].stm_i2c;
277 stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_LAST);
278 ao_dma_done[index] = 1;
279 ao_wakeup(&ao_dma_done[index]);
283 ao_i2c_recv(void *block, uint16_t len, uint8_t index, uint8_t stop)
285 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
291 ao_i2c_recv_data[index] = block;
292 ao_i2c_recv_len[index] = 1;
293 stm_i2c->cr1 = AO_STM_I2C_CR1;
295 /* Clear any pending ADDR bit */
297 ao_i2c_wait_addr(index);
299 /* Enable interrupts to transfer the byte */
300 stm_i2c->cr2 = (AO_STM_I2C_CR2 |
301 (1 << STM_I2C_CR2_ITEVTEN) |
302 (1 << STM_I2C_CR2_ITERREN) |
303 (1 << STM_I2C_CR2_ITBUFEN));
305 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
307 ao_arch_block_interrupts();
308 while (ao_i2c_recv_len[index])
309 if (ao_sleep_for(&ao_i2c_recv_len[index], 1))
311 ao_arch_release_interrupts();
312 ret = ao_i2c_recv_len[index] == 0;
314 uint8_t rx_dma_index = ao_i2c_stm_info[index].rx_dma_index;
315 ao_dma_set_transfer(rx_dma_index,
319 (0 << STM_DMA_CCR_MEM2MEM) |
320 (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
321 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
322 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
323 (1 << STM_DMA_CCR_MINC) |
324 (0 << STM_DMA_CCR_PINC) |
325 (0 << STM_DMA_CCR_CIRC) |
326 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
328 /* XXX ao_i2c_recv_dma_isr hasn't ever been used, so it
329 * doesn't appear to be necessary. Testing with a device
330 * that uses i2c would really be useful here to discover
331 * whether this function is necessary or not.
334 ao_dma_set_isr(rx_dma_index, ao_i2c_recv_dma_isr);
336 (void) ao_i2c_recv_dma_isr;
338 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_ACK);
339 stm_i2c->cr2 = AO_STM_I2C_CR2 |
340 (1 << STM_I2C_CR2_DMAEN) | (1 << STM_I2C_CR2_LAST);
341 /* Clear any pending ADDR bit */
343 ao_i2c_wait_addr(index);
345 ao_dma_start(rx_dma_index);
346 ao_arch_block_interrupts();
347 while (!ao_dma_done[rx_dma_index])
348 if (ao_sleep_for(&ao_dma_done[rx_dma_index], len))
350 ao_arch_release_interrupts();
351 ret = ao_dma_done[rx_dma_index];
352 ao_dma_done_transfer(rx_dma_index);
353 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
356 ao_i2c_wait_stop(index);
361 ao_i2c_channel_init(uint8_t index)
363 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
366 /* Turn I2C off while configuring */
367 stm_i2c->cr1 = (1 << STM_I2C_CR1_SWRST);
368 for (i = 0; i < 100; i++)
371 stm_i2c->cr2 = AO_STM_I2C_CR2;
380 stm_i2c->ccr = ((I2C_FAST << STM_I2C_CCR_FS) |
381 (0 << STM_I2C_CCR_DUTY) |
382 (I2C_CCR_HIGH << STM_I2C_CCR_CCR));
384 stm_i2c->trise = I2C_TRISE;
386 stm_i2c->cr1 = AO_STM_I2C_CR1;
390 i2c_pin_set(struct stm_gpio *gpio, int pin)
392 ao_enable_port(gpio);
393 stm_gpio_conf(gpio, pin,
394 STM_GPIO_CR_MODE_OUTPUT_2MHZ,
395 STM_GPIO_CR_CNF_OUTPUT_AF_OPEN_DRAIN);
403 stm_set_afio_mapr(STM_AFIO_MAPR_I2C1_REMAP,
404 STM_AFIO_MAPR_I2C1_REMAP_PB6_PB7,
405 STM_AFIO_MAPR_I2C1_REMAP_MASK);
406 i2c_pin_set(&stm_gpiob, 6);
407 i2c_pin_set(&stm_gpiob, 7);
410 stm_set_afio_mapr(STM_AFIO_MAPR_I2C1_REMAP,
411 STM_AFIO_MAPR_I2C1_REMAP_PB8_PB9,
412 STM_AFIO_MAPR_I2C1_REMAP_MASK);
413 i2c_pin_set(&stm_gpiob, 8);
414 i2c_pin_set(&stm_gpiob, 9);
416 # error "No I2C_1 port configuration specified"
420 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C1EN);
421 ao_i2c_channel_init(0);
423 stm_nvic_set_enable(STM_ISR_I2C1_EV_POS);
424 stm_nvic_set_priority(STM_ISR_I2C1_EV_POS, AO_STM_NVIC_MED_PRIORITY);
425 stm_nvic_set_enable(STM_ISR_I2C1_ER_POS);
426 stm_nvic_set_priority(STM_ISR_I2C1_ER_POS, AO_STM_NVIC_MED_PRIORITY);
431 i2c_pin_set(&stm_gpiob, 10);
432 i2c_pin_set(&stm_gpiob, 11);
434 # error "No I2C_2 port configuration specified"
436 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C2EN);
437 ao_i2c_channel_init(1);
439 stm_nvic_set_enable(STM_ISR_I2C2_EV_POS);
440 stm_nvic_set_priority(STM_ISR_I2C2_EV_POS, AO_STM_NVIC_MED_PRIORITY);
441 stm_nvic_set_enable(STM_ISR_I2C2_ER_POS);
442 stm_nvic_set_priority(STM_ISR_I2C2_ER_POS, AO_STM_NVIC_MED_PRIORITY);