2 * Copyright © 2023 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #ifndef _AO_ARCH_FUNCS_H_
20 #define _AO_ARCH_FUNCS_H_
22 #define AO_EXTI_MODE_RISING 1
23 #define AO_EXTI_MODE_FALLING 2
24 #define AO_EXTI_MODE_PULL_NONE 0
25 #define AO_EXTI_MODE_PULL_UP 4
26 #define AO_EXTI_MODE_PULL_DOWN 8
27 #define AO_EXTI_PRIORITY_LOW 16
28 #define AO_EXTI_PRIORITY_MED 0
29 #define AO_EXTI_PRIORITY_HIGH 32
30 #define AO_EXTI_PIN_NOCONFIGURE 64
33 ao_enable_port(struct stm_gpio *port)
35 if ((port) == &stm_gpioa)
36 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_IOPAEN);
37 else if ((port) == &stm_gpiob)
38 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_IOPBEN);
39 else if ((port) == &stm_gpioc)
40 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_IOPCEN);
41 else if ((port) == &stm_gpiod)
42 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_IOPDEN);
43 else if ((port) == &stm_gpioe)
44 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_IOPEEN);
48 ao_disable_port(struct stm_gpio *port)
50 if ((port) == &stm_gpioa)
51 stm_rcc.apb2enr &= ~(1UL << STM_RCC_APB2ENR_IOPAEN);
52 else if ((port) == &stm_gpiob)
53 stm_rcc.apb2enr &= ~(1UL << STM_RCC_APB2ENR_IOPBEN);
54 else if ((port) == &stm_gpioc)
55 stm_rcc.apb2enr &= ~(1UL << STM_RCC_APB2ENR_IOPCEN);
56 else if ((port) == &stm_gpiod)
57 stm_rcc.apb2enr &= ~(1UL << STM_RCC_APB2ENR_IOPDEN);
58 else if ((port) == &stm_gpioe)
59 stm_rcc.apb2enr &= ~(1UL << STM_RCC_APB2ENR_IOPEEN);
62 #define ao_gpio_set(port, bit, v) stm_gpio_set(port, bit, v)
64 #define ao_gpio_get(port, bit) stm_gpio_get(port, bit)
66 #define ao_gpio_set_bits(port, bits) stm_gpio_set_bits(port, bits)
68 #define ao_gpio_set_mask(port, bits, mask) stm_gpio_set_mask(port, bits, mask)
70 #define ao_gpio_clr_bits(port, bits) stm_gpio_clr_bits(port, bits);
72 #define ao_gpio_get_all(port) stm_gpio_get_all(port)
75 ao_enable_output(struct stm_gpio *port, int bit, uint8_t v)
78 ao_gpio_set(port, bit, v);
79 stm_gpio_conf(port, bit,
80 STM_GPIO_CR_MODE_OUTPUT_10MHZ,
81 STM_GPIO_CR_CNF_OUTPUT_PUSH_PULL);
85 ao_gpio_set_mode(struct stm_gpio *port, int bit, int mode)
89 if (mode == AO_EXTI_MODE_PULL_NONE)
90 cnf = STM_GPIO_CR_CNF_INPUT_FLOATING;
92 cnf = STM_GPIO_CR_CNF_INPUT_PULL;
93 ao_gpio_set(port, bit, mode == AO_EXTI_MODE_PULL_UP);
95 stm_gpio_conf(port, bit,
96 STM_GPIO_CR_MODE_INPUT,
101 ao_enable_input(struct stm_gpio *port, int bit, int mode)
103 ao_enable_port(port);
104 ao_gpio_set_mode(port, bit, mode);
108 ao_enable_cs(struct stm_gpio *port, int bit)
110 ao_enable_output(port, bit, 1);
113 #if USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_SW_FLOW || USE_SERIAL_3_SW_FLOW
114 #define HAS_SERIAL_SW_FLOW 1
116 #define HAS_SERIAL_SW_FLOW 0
119 #if USE_SERIAL_1_FLOW && !USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_FLOW && !USE_SERIAL_2_SW_FLOW || USE_SERIAL_3_FLOW && !USE_SERIAL_3_SW_FLOW
120 #define HAS_SERIAL_HW_FLOW 1
122 #define HAS_SERIAL_HW_FLOW 0
125 /* ao_serial_stm.c */
126 struct ao_stm_usart {
127 struct ao_fifo rx_fifo;
128 struct ao_fifo tx_fifo;
129 struct stm_usart *reg;
132 #if HAS_SERIAL_SW_FLOW
133 /* RTS - 0 if we have FIFO space, 1 if not
134 * CTS - 0 if we can send, 0 if not
136 struct stm_gpio *gpio_rts;
137 struct stm_gpio *gpio_cts;
145 ao_debug_out(char c);
148 extern struct ao_stm_usart ao_stm_usart1;
152 extern struct ao_stm_usart ao_stm_usart2;
156 extern struct ao_stm_usart ao_stm_usart3;
159 #define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
161 typedef uint32_t ao_arch_irq_t;
164 ao_arch_block_interrupts(void) {
165 #ifdef AO_NONMASK_INTERRUPTS
166 asm("msr basepri,%0" : : "r" (AO_STM_NVIC_BASEPRI_MASK));
173 ao_arch_release_interrupts(void) {
174 #ifdef AO_NONMASK_INTERRUPTS
175 asm("msr basepri,%0" : : "r" (0x0));
181 static inline uint32_t
182 ao_arch_irqsave(void) {
184 #ifdef AO_NONMASK_INTERRUPTS
185 asm("mrs %0,basepri" : "=r" (val));
187 asm("mrs %0,primask" : "=r" (val));
189 ao_arch_block_interrupts();
194 ao_arch_irqrestore(uint32_t basepri) {
195 #ifdef AO_NONMASK_INTERRUPTS
196 asm("msr basepri,%0" : : "r" (basepri));
198 asm("msr primask,%0" : : "r" (basepri));
203 ao_arch_memory_barrier(void) {
204 asm volatile("" ::: "memory");
208 ao_arch_irq_check(void) {
209 #ifdef AO_NONMASK_INTERRUPTS
211 asm("mrs %0,basepri" : "=r" (basepri));
213 ao_panic(AO_PANIC_IRQ);
216 asm("mrs %0,primask" : "=r" (primask));
217 if ((primask & 1) == 0)
218 ao_panic(AO_PANIC_IRQ);
224 ao_arch_init_stack(struct ao_task *task, uint32_t *sp, void *start)
226 uint32_t a = (uint32_t) start;
229 /* Return address (goes into LR) */
232 /* Clear register values r0-r12 */
240 /* BASEPRI with interrupts enabled */
246 static inline void ao_arch_save_regs(void) {
247 /* Save general registers */
248 asm("push {r0-r12,lr}\n");
254 #ifdef AO_NONMASK_INTERRUPTS
256 asm("mrs r0,basepri");
259 asm("mrs r0,primask");
264 static inline void ao_arch_save_stack(void) {
266 asm("mov %0,sp" : "=&r" (sp) );
267 ao_cur_task->sp32 = (sp);
270 static inline void ao_arch_restore_stack(void) {
272 asm("mov sp, %0" : : "r" (ao_cur_task->sp32) );
274 #ifdef AO_NONMASK_INTERRUPTS
275 /* Restore BASEPRI */
277 asm("msr basepri,r0");
279 /* Restore PRIMASK */
281 asm("msr primask,r0");
286 asm("msr apsr_nczvq,r0");
288 /* Restore general registers */
289 asm("pop {r0-r12,lr}\n");
291 /* Return to calling function */
294 #define HAS_ARCH_START_SCHEDULER 1
296 static inline void ao_arch_start_scheduler(void) {
300 asm("mrs %0,msp" : "=&r" (sp));
301 asm("msr psp,%0" : : "r" (sp));
302 asm("mrs %0,control" : "=r" (control));
304 asm("msr control,%0" : : "r" (control));
308 #define ao_arch_isr_stack()
310 #endif /* HAS_TASK */
313 ao_arch_wait_interrupt(void) {
314 #ifdef AO_NONMASK_INTERRUPTS
316 "dsb\n" /* Serialize data */
317 "isb\n" /* Serialize instructions */
318 "cpsid i\n" /* Block all interrupts */
319 "msr basepri,%0\n" /* Allow all interrupts through basepri */
320 "wfi\n" /* Wait for an interrupt */
321 "cpsie i\n" /* Allow all interrupts */
322 "msr basepri,%1\n" /* Block interrupts through basepri */
323 : : "r" (0), "r" (AO_STM_NVIC_BASEPRI_MASK));
326 ao_arch_release_interrupts();
327 ao_arch_block_interrupts();
331 #define ao_arch_critical(b) do { \
332 uint32_t __mask = ao_arch_irqsave(); \
333 do { b } while (0); \
334 ao_arch_irqrestore(__mask); \
337 #define ao_arch_reboot() \
338 (stm_scb.aircr = ((STM_SCB_AIRCR_VECTKEY_KEY << STM_SCB_AIRCR_VECTKEY) | \
339 (1 << STM_SCB_AIRCR_SYSRESETREQ)))
344 extern uint8_t ao_dma_done[STM_NUM_DMA];
347 ao_dma_set_transfer(uint8_t index,
348 volatile void *peripheral,
354 ao_dma_mutex_get(uint8_t index);
357 ao_dma_mutex_put(uint8_t index);
360 ao_dma_set_isr(uint8_t index, void (*isr)(int index));
363 ao_dma_start(uint8_t index);
366 ao_dma_done_transfer(uint8_t index);
369 ao_dma_alloc(uint8_t index);
377 #define AO_SPI_CPOL_BIT 4
378 #define AO_SPI_CPHA_BIT 5
380 #define AO_SPI_CONFIG_1 0x00
381 #define AO_SPI_1_CONFIG_PA5_PA6_PA7 AO_SPI_CONFIG_1
382 #define AO_SPI_2_CONFIG_PB13_PB14_PB15 AO_SPI_CONFIG_1
384 #define AO_SPI_CONFIG_2 0x04
385 #define AO_SPI_1_CONFIG_PB3_PB4_PB5 AO_SPI_CONFIG_2
386 #define AO_SPI_2_CONFIG_PD1_PD3_PD4 AO_SPI_CONFIG_2
388 #define AO_SPI_CONFIG_3 0x08
389 #define AO_SPI_1_CONFIG_PE13_PE14_PE15 AO_SPI_CONFIG_3
391 #define AO_SPI_CONFIG_NONE 0x0c
393 #define AO_SPI_INDEX_MASK 0x01
394 #define AO_SPI_CONFIG_MASK 0x0c
396 #define AO_SPI_1_PA5_PA6_PA7 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA5_PA6_PA7)
397 #define AO_SPI_1_PB3_PB4_PB5 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PB3_PB4_PB5)
398 #define AO_SPI_1_PE13_PE14_PE15 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PE13_PE14_PE15)
400 #define AO_SPI_2_PB13_PB14_PB15 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PB13_PB14_PB15)
401 #define AO_SPI_2_PD1_PD3_PD4 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PD1_PD3_PD4)
403 #define AO_SPI_INDEX(id) ((id) & AO_SPI_INDEX_MASK)
404 #define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
405 #define AO_SPI_PIN_CONFIG(id) ((id) & (AO_SPI_INDEX_MASK | AO_SPI_CONFIG_MASK))
406 #define AO_SPI_CPOL(id) ((uint32_t) (((id) >> AO_SPI_CPOL_BIT) & 1))
407 #define AO_SPI_CPHA(id) ((uint32_t) (((id) >> AO_SPI_CPHA_BIT) & 1))
409 #define AO_SPI_MAKE_MODE(pol,pha) (((pol) << AO_SPI_CPOL_BIT) | ((pha) << AO_SPI_CPHA_BIT))
410 #define AO_SPI_MODE_0 AO_SPI_MAKE_MODE(0,0)
411 #define AO_SPI_MODE_1 AO_SPI_MAKE_MODE(0,1)
412 #define AO_SPI_MODE_2 AO_SPI_MAKE_MODE(1,0)
413 #define AO_SPI_MODE_3 AO_SPI_MAKE_MODE(1,1)
415 /* SPI1 is on APB2, SPI2 is on APB1 */
416 #define AO_SPI_FREQ(bus, div) ((AO_SPI_INDEX(bus) == 0 ? AO_APB2CLK : AO_APB1CLK) / (div))
418 static inline uint32_t
419 ao_spi_speed(int num, uint32_t hz)
421 if (hz >= AO_SPI_FREQ(num, 2)) return STM_SPI_CR1_BR_PCLK_2;
422 if (hz >= AO_SPI_FREQ(num, 4)) return STM_SPI_CR1_BR_PCLK_4;
423 if (hz >= AO_SPI_FREQ(num, 8)) return STM_SPI_CR1_BR_PCLK_8;
424 if (hz >= AO_SPI_FREQ(num, 16)) return STM_SPI_CR1_BR_PCLK_16;
425 if (hz >= AO_SPI_FREQ(num, 32)) return STM_SPI_CR1_BR_PCLK_32;
426 if (hz >= AO_SPI_FREQ(num, 64)) return STM_SPI_CR1_BR_PCLK_64;
427 if (hz >= AO_SPI_FREQ(num, 128)) return STM_SPI_CR1_BR_PCLK_128;
428 return STM_SPI_CR1_BR_PCLK_256;
432 ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id);
435 ao_spi_get(uint8_t spi_index, uint32_t speed);
438 ao_spi_put(uint8_t spi_index);
441 ao_spi_put_pins(uint8_t spi_index);
444 ao_spi_send(const void *block, uint16_t len, uint8_t spi_index);
447 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
450 ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index);
453 ao_spi_start_bytes(uint8_t spi_index);
456 ao_spi_stop_bytes(uint8_t spi_index);
459 ao_spi_send_byte(uint8_t byte, uint8_t spi_index)
461 struct stm_spi *stm_spi;
463 switch (AO_SPI_INDEX(spi_index)) {
472 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
475 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
480 static inline uint8_t
481 ao_spi_recv_byte(uint8_t spi_index)
483 struct stm_spi *stm_spi;
485 switch (AO_SPI_INDEX(spi_index)) {
494 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
497 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
499 return (uint8_t) stm_spi->dr;
503 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
506 ao_spi_duplex(const void *out, void *in, uint16_t len, uint8_t spi_index);
511 #define ao_spi_init_cs(port, mask) do { \
513 for (__bit__ = 0; __bit__ < 32; __bit__++) { \
514 if (mask & (1 << __bit__)) \
515 ao_enable_output(port, __bit__, 1); \
519 #define ao_spi_set_cs(reg,mask) ((reg)->bsrr = ((uint32_t) (mask)) << 16)
520 #define ao_spi_clr_cs(reg,mask) ((reg)->bsrr = (mask))
522 #define ao_spi_get_mask(reg,mask,bus, speed) do { \
523 ao_spi_get(bus, speed); \
524 ao_spi_set_cs(reg,mask); \
527 static inline uint8_t
528 ao_spi_try_get_mask(struct stm_gpio *reg, uint16_t mask, uint8_t bus, uint32_t speed, uint8_t task_id)
530 if (!ao_spi_try_get(bus, speed, task_id))
532 ao_spi_set_cs(reg, mask);
536 #define ao_spi_put_mask(reg,mask,bus) do { \
537 ao_spi_clr_cs(reg,mask); \
541 #define ao_spi_get_bit(reg,bit,bus,speed) ao_spi_get_mask(reg,1<<(bit),bus,speed)
542 #define ao_spi_put_bit(reg,bit,bus) ao_spi_put_mask(reg,1<<(bit),bus)
545 ao_i2c_get(uint8_t i2c_index);
548 ao_i2c_start(uint8_t i2c_index, uint16_t address);
551 ao_i2c_put(uint8_t i2c_index);
554 ao_i2c_send(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
557 ao_i2c_recv(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
562 #endif /* _AO_ARCH_FUNCS_H_ */