2 * Copyright © 2023 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #ifndef _AO_ARCH_FUNCS_H_
20 #define _AO_ARCH_FUNCS_H_
22 #define AO_EXTI_MODE_RISING 1
23 #define AO_EXTI_MODE_FALLING 2
24 #define AO_EXTI_MODE_PULL_NONE 0
25 #define AO_EXTI_MODE_PULL_UP 4
26 #define AO_EXTI_MODE_PULL_DOWN 8
27 #define AO_EXTI_PRIORITY_LOW 16
28 #define AO_EXTI_PRIORITY_MED 0
29 #define AO_EXTI_PRIORITY_HIGH 32
30 #define AO_EXTI_PIN_NOCONFIGURE 64
33 ao_enable_port(struct stm_gpio *port)
35 if ((port) == &stm_gpioa)
36 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_IOPAEN);
37 else if ((port) == &stm_gpiob)
38 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_IOPBEN);
39 else if ((port) == &stm_gpioc)
40 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_IOPCEN);
41 else if ((port) == &stm_gpiod)
42 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_IOPDEN);
43 else if ((port) == &stm_gpioe)
44 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_IOPEEN);
48 ao_disable_port(struct stm_gpio *port)
50 if ((port) == &stm_gpioa)
51 stm_rcc.apb2enr &= ~(1UL << STM_RCC_APB2ENR_IOPAEN);
52 else if ((port) == &stm_gpiob)
53 stm_rcc.apb2enr &= ~(1UL << STM_RCC_APB2ENR_IOPBEN);
54 else if ((port) == &stm_gpioc)
55 stm_rcc.apb2enr &= ~(1UL << STM_RCC_APB2ENR_IOPCEN);
56 else if ((port) == &stm_gpiod)
57 stm_rcc.apb2enr &= ~(1UL << STM_RCC_APB2ENR_IOPDEN);
58 else if ((port) == &stm_gpioe)
59 stm_rcc.apb2enr &= ~(1UL << STM_RCC_APB2ENR_IOPEEN);
62 #define ao_gpio_set(port, bit, v) stm_gpio_set(port, bit, v)
64 #define ao_gpio_get(port, bit) stm_gpio_get(port, bit)
66 #define ao_gpio_set_bits(port, bits) stm_gpio_set_bits(port, bits)
68 #define ao_gpio_set_mask(port, bits, mask) stm_gpio_set_mask(port, bits, mask)
70 #define ao_gpio_clr_bits(port, bits) stm_gpio_clr_bits(port, bits);
72 #define ao_gpio_get_all(port) stm_gpio_get_all(port)
75 ao_enable_output(struct stm_gpio *port, int bit, uint8_t v)
78 ao_gpio_set(port, bit, v);
79 stm_gpio_conf(port, bit,
80 STM_GPIO_CR_MODE_OUTPUT_10MHZ,
81 STM_GPIO_CR_CNF_OUTPUT_PUSH_PULL);
85 ao_gpio_set_mode(struct stm_gpio *port, int bit, int mode)
89 if (mode == AO_EXTI_MODE_PULL_NONE)
90 cnf = STM_GPIO_CR_CNF_INPUT_FLOATING;
92 cnf = STM_GPIO_CR_CNF_INPUT_PULL;
93 ao_gpio_set(port, bit, mode == AO_EXTI_MODE_PULL_UP);
95 stm_gpio_conf(port, bit,
96 STM_GPIO_CR_MODE_INPUT,
101 ao_enable_input(struct stm_gpio *port, int bit, int mode)
103 ao_enable_port(port);
104 ao_gpio_set_mode(port, bit, mode);
107 #if USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_SW_FLOW || USE_SERIAL_3_SW_FLOW
108 #define HAS_SERIAL_SW_FLOW 1
110 #define HAS_SERIAL_SW_FLOW 0
113 #if USE_SERIAL_1_FLOW && !USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_FLOW && !USE_SERIAL_2_SW_FLOW || USE_SERIAL_3_FLOW && !USE_SERIAL_3_SW_FLOW
114 #define HAS_SERIAL_HW_FLOW 1
116 #define HAS_SERIAL_HW_FLOW 0
119 /* ao_serial_stm.c */
120 struct ao_stm_usart {
121 struct ao_fifo rx_fifo;
122 struct ao_fifo tx_fifo;
123 struct stm_usart *reg;
126 #if HAS_SERIAL_SW_FLOW
127 /* RTS - 0 if we have FIFO space, 1 if not
128 * CTS - 0 if we can send, 0 if not
130 struct stm_gpio *gpio_rts;
131 struct stm_gpio *gpio_cts;
139 ao_debug_out(char c);
142 extern struct ao_stm_usart ao_stm_usart1;
146 extern struct ao_stm_usart ao_stm_usart2;
150 extern struct ao_stm_usart ao_stm_usart3;
153 #define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
155 typedef uint32_t ao_arch_irq_t;
158 ao_arch_block_interrupts(void) {
159 #ifdef AO_NONMASK_INTERRUPTS
160 asm("msr basepri,%0" : : "r" (AO_STM_NVIC_BASEPRI_MASK));
167 ao_arch_release_interrupts(void) {
168 #ifdef AO_NONMASK_INTERRUPTS
169 asm("msr basepri,%0" : : "r" (0x0));
175 static inline uint32_t
176 ao_arch_irqsave(void) {
178 #ifdef AO_NONMASK_INTERRUPTS
179 asm("mrs %0,basepri" : "=r" (val));
181 asm("mrs %0,primask" : "=r" (val));
183 ao_arch_block_interrupts();
188 ao_arch_irqrestore(uint32_t basepri) {
189 #ifdef AO_NONMASK_INTERRUPTS
190 asm("msr basepri,%0" : : "r" (basepri));
192 asm("msr primask,%0" : : "r" (basepri));
197 ao_arch_memory_barrier(void) {
198 asm volatile("" ::: "memory");
202 ao_arch_irq_check(void) {
203 #ifdef AO_NONMASK_INTERRUPTS
205 asm("mrs %0,basepri" : "=r" (basepri));
207 ao_panic(AO_PANIC_IRQ);
210 asm("mrs %0,primask" : "=r" (primask));
211 if ((primask & 1) == 0)
212 ao_panic(AO_PANIC_IRQ);
218 ao_arch_init_stack(struct ao_task *task, uint32_t *sp, void *start)
220 uint32_t a = (uint32_t) start;
223 /* Return address (goes into LR) */
226 /* Clear register values r0-r12 */
234 /* BASEPRI with interrupts enabled */
240 static inline void ao_arch_save_regs(void) {
241 /* Save general registers */
242 asm("push {r0-r12,lr}\n");
248 #ifdef AO_NONMASK_INTERRUPTS
250 asm("mrs r0,basepri");
253 asm("mrs r0,primask");
258 static inline void ao_arch_save_stack(void) {
260 asm("mov %0,sp" : "=&r" (sp) );
261 ao_cur_task->sp32 = (sp);
264 static inline void ao_arch_restore_stack(void) {
266 asm("mov sp, %0" : : "r" (ao_cur_task->sp32) );
268 #ifdef AO_NONMASK_INTERRUPTS
269 /* Restore BASEPRI */
271 asm("msr basepri,r0");
273 /* Restore PRIMASK */
275 asm("msr primask,r0");
280 asm("msr apsr_nczvq,r0");
282 /* Restore general registers */
283 asm("pop {r0-r12,lr}\n");
285 /* Return to calling function */
288 #define HAS_ARCH_START_SCHEDULER 1
290 static inline void ao_arch_start_scheduler(void) {
294 asm("mrs %0,msp" : "=&r" (sp));
295 asm("msr psp,%0" : : "r" (sp));
296 asm("mrs %0,control" : "=r" (control));
298 asm("msr control,%0" : : "r" (control));
302 #define ao_arch_isr_stack()
304 #endif /* HAS_TASK */
307 ao_arch_wait_interrupt(void) {
308 #ifdef AO_NONMASK_INTERRUPTS
310 "dsb\n" /* Serialize data */
311 "isb\n" /* Serialize instructions */
312 "cpsid i\n" /* Block all interrupts */
313 "msr basepri,%0\n" /* Allow all interrupts through basepri */
314 "wfi\n" /* Wait for an interrupt */
315 "cpsie i\n" /* Allow all interrupts */
316 "msr basepri,%1\n" /* Block interrupts through basepri */
317 : : "r" (0), "r" (AO_STM_NVIC_BASEPRI_MASK));
320 ao_arch_release_interrupts();
321 ao_arch_block_interrupts();
325 #define ao_arch_critical(b) do { \
326 uint32_t __mask = ao_arch_irqsave(); \
327 do { b } while (0); \
328 ao_arch_irqrestore(__mask); \
331 #define ao_arch_reboot() \
332 (stm_scb.aircr = ((STM_SCB_AIRCR_VECTKEY_KEY << STM_SCB_AIRCR_VECTKEY) | \
333 (1 << STM_SCB_AIRCR_SYSRESETREQ)))
335 #endif /* _AO_ARCH_FUNCS_H_ */