2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
22 static uint8_t ao_adc_ready;
24 #define AO_ADC_CR2_VAL ((HAS_ADC_TEMP << STM_ADC_CR2_TSVREF) | \
25 (0 << STM_ADC_CR2_SWSTART) | \
26 (0 << STM_ADC_CR2_JWSTART) | \
27 (0 << STM_ADC_CR2_EXTTRIG) | \
28 (0 << STM_ADC_CR2_EXTSEL) | \
29 (0 << STM_ADC_CR2_JEXTTRIG) | \
30 (0 << STM_ADC_CR2_JEXTSEL) | \
31 (0 << STM_ADC_CR2_ALIGN) | \
32 (1 << STM_ADC_CR2_DMA) | \
33 (0 << STM_ADC_CR2_CONT) | \
34 (1 << STM_ADC_CR2_ADON))
37 * Callback from DMA ISR
39 * Mark time in ring, shut down DMA engine
41 static void ao_adc_done(int index)
44 AO_DATA_PRESENT(AO_DATA_ADC);
45 ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
46 ao_data_fill(ao_data_head);
51 * Start the ADC sequence using the DMA engine
60 ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
62 (void *) (&ao_data_ring[ao_data_head].adc),
64 (0 << STM_DMA_CCR_MEM2MEM) |
65 (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
66 (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
67 (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
68 (1 << STM_DMA_CCR_MINC) |
69 (0 << STM_DMA_CCR_PINC) |
70 (0 << STM_DMA_CCR_CIRC) |
71 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
72 ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
73 ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
75 stm_adc.cr2 = AO_ADC_CR2_VAL | (1 << STM_ADC_CR2_SWSTART);
78 #ifdef AO_ADC_SQ1_NAME
79 static const char *ao_adc_name[AO_NUM_ADC] = {
81 #ifdef AO_ADC_SQ2_NAME
84 #ifdef AO_ADC_SQ3_NAME
87 #ifdef AO_ADC_SQ4_NAME
90 #ifdef AO_ADC_SQ5_NAME
93 #ifdef AO_ADC_SQ6_NAME
96 #ifdef AO_ADC_SQ7_NAME
99 #ifdef AO_ADC_SQ8_NAME
102 #ifdef AO_ADC_SQ9_NAME
105 #ifdef AO_ADC_SQ10_NAME
108 #ifdef AO_ADC_SQ11_NAME
111 #ifdef AO_ADC_SQ12_NAME
114 #ifdef AO_ADC_SQ13_NAME
117 #ifdef AO_ADC_SQ14_NAME
120 #ifdef AO_ADC_SQ15_NAME
123 #ifdef AO_ADC_SQ16_NAME
126 #ifdef AO_ADC_SQ17_NAME
129 #ifdef AO_ADC_SQ18_NAME
132 #ifdef AO_ADC_SQ19_NAME
135 #ifdef AO_ADC_SQ20_NAME
138 #ifdef AO_ADC_SQ21_NAME
139 #error "too many ADC names"
147 struct ao_data packet;
153 ao_data_get(&packet);
155 AO_ADC_DUMP(&packet);
157 printf("tick: %5u", packet.tick);
158 d = (int16_t *) (&packet.adc);
159 for (i = 0; i < AO_NUM_ADC; i++) {
160 #ifdef AO_ADC_SQ1_NAME
162 printf (" %s: %5d", ao_adc_name[i], d[i]);
165 printf (" %2d: %5d", i, d[i]);
171 const struct ao_cmds ao_adc_cmds[] = {
172 { ao_adc_dump, "a\0Display current ADC values" },
177 adc_pin_set(struct stm_gpio *gpio, int pin)
179 ao_enable_port(gpio);
180 stm_gpio_conf(gpio, pin,
181 STM_GPIO_CR_MODE_INPUT,
182 STM_GPIO_CR_CNF_INPUT_ANALOG);
188 #ifdef AO_ADC_PIN0_PORT
189 adc_pin_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN);
191 #ifdef AO_ADC_PIN1_PORT
192 adc_pin_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN);
194 #ifdef AO_ADC_PIN2_PORT
195 adc_pin_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN);
197 #ifdef AO_ADC_PIN3_PORT
198 adc_pin_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN);
200 #ifdef AO_ADC_PIN4_PORT
201 adc_pin_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN);
203 #ifdef AO_ADC_PIN5_PORT
204 adc_pin_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN);
206 #ifdef AO_ADC_PIN6_PORT
207 adc_pin_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN);
209 #ifdef AO_ADC_PIN7_PORT
210 adc_pin_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN);
212 #ifdef AO_ADC_PIN8_PORT
213 adc_pin_set(AO_ADC_PIN8_PORT, AO_ADC_PIN8_PIN);
215 #ifdef AO_ADC_PIN9_PORT
216 adc_pin_set(AO_ADC_PIN9_PORT, AO_ADC_PIN9_PIN);
218 #ifdef AO_ADC_PIN10_PORT
219 adc_pin_set(AO_ADC_PIN10_PORT, AO_ADC_PIN10_PIN);
221 #ifdef AO_ADC_PIN11_PORT
222 adc_pin_set(AO_ADC_PIN11_PORT, AO_ADC_PIN11_PIN);
224 #ifdef AO_ADC_PIN12_PORT
225 adc_pin_set(AO_ADC_PIN12_PORT, AO_ADC_PIN12_PIN);
227 #ifdef AO_ADC_PIN13_PORT
228 adc_pin_set(AO_ADC_PIN13_PORT, AO_ADC_PIN13_PIN);
230 #ifdef AO_ADC_PIN14_PORT
231 adc_pin_set(AO_ADC_PIN14_PORT, AO_ADC_PIN14_PIN);
233 #ifdef AO_ADC_PIN15_PORT
234 adc_pin_set(AO_ADC_PIN15_PORT, AO_ADC_PIN15_PIN);
236 #ifdef AO_ADC_PIN16_PORT
237 adc_pin_set(AO_ADC_PIN16_PORT, AO_ADC_PIN16_PIN);
239 #ifdef AO_ADC_PIN17_PORT
240 adc_pin_set(AO_ADC_PIN17_PORT, AO_ADC_PIN17_PIN);
242 #ifdef AO_ADC_PIN18_PORT
243 adc_pin_set(AO_ADC_PIN18_PORT, AO_ADC_PIN18_PIN);
245 #ifdef AO_ADC_PIN19_PORT
246 adc_pin_set(AO_ADC_PIN19_PORT, AO_ADC_PIN19_PIN);
248 #ifdef AO_ADC_PIN20_PORT
249 adc_pin_set(AO_ADC_PIN20_PORT, AO_ADC_PIN20_PIN);
251 #ifdef AO_ADC_PIN21_PORT
252 adc_pin_set(AO_ADC_PIN21_PORT, AO_ADC_PIN21_PIN);
254 #ifdef AO_ADC_PIN22_PORT
255 adc_pin_set(AO_ADC_PIN22_PORT, AO_ADC_PIN22_PIN);
257 #ifdef AO_ADC_PIN23_PORT
258 adc_pin_set(AO_ADC_PIN23_PORT, AO_ADC_PIN23_PIN);
260 #ifdef AO_ADC_PIN24_PORT
261 #error "Too many ADC ports"
264 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
266 /* Turn off ADC during configuration */
269 stm_adc.cr1 = ((0 << STM_ADC_CR1_AWDEN ) |
270 (0 << STM_ADC_CR1_JAWDEN ) |
271 (STM_ADC_CR1_DUALMOD_INDEPENDENT << STM_ADC_CR1_DUALMOD ) |
272 (0 << STM_ADC_CR1_DISCNUM ) |
273 (0 << STM_ADC_CR1_JDISCEN ) |
274 (0 << STM_ADC_CR1_DISCEN ) |
275 (0 << STM_ADC_CR1_JAUTO ) |
276 (0 << STM_ADC_CR1_AWDSGL ) |
277 (1 << STM_ADC_CR1_SCAN ) |
278 (0 << STM_ADC_CR1_JEOCIE ) |
279 (0 << STM_ADC_CR1_AWDIE ) |
280 (0 << STM_ADC_CR1_EOCIE ) |
281 (0 << STM_ADC_CR1_AWDCH ));
283 /* 384 cycle sample time for everyone */
284 stm_adc.smpr1 = 0x3ffff;
285 stm_adc.smpr2 = 0x3fffffff;
287 stm_adc.sqr1 = ((AO_NUM_ADC - 1) << 20);
289 stm_adc.sqr3 |= (AO_ADC_SQ1 << 0);
292 stm_adc.sqr3 |= (AO_ADC_SQ2 << 5);
295 stm_adc.sqr3 |= (AO_ADC_SQ3 << 10);
298 stm_adc.sqr3 |= (AO_ADC_SQ4 << 15);
301 stm_adc.sqr3 |= (AO_ADC_SQ5 << 20);
304 stm_adc.sqr3 |= (AO_ADC_SQ6 << 25);
307 stm_adc.sqr2 |= (AO_ADC_SQ7 << 0);
310 stm_adc.sqr2 |= (AO_ADC_SQ8 << 5);
313 stm_adc.sqr2 |= (AO_ADC_SQ9 << 10);
316 stm_adc.sqr2 |= (AO_ADC_SQ10 << 15);
319 stm_adc.sqr2 |= (AO_ADC_SQ11 << 20);
322 stm_adc.sqr2 |= (AO_ADC_SQ12 << 25);
325 stm_adc.sqr1 |= (AO_ADC_SQ13 << 0);
328 stm_adc.sqr1 |= (AO_ADC_SQ14 << 5);
331 stm_adc.sqr1 |= (AO_ADC_SQ15 << 10);
334 stm_adc.sqr1 |= (AO_ADC_SQ16 << 15);
337 #error "too many ADC channels"
341 #error Please define HAS_ADC_TEMP
344 stm_adc.cr2 |= ((1 << STM_ADC_CR2_TSVREFE));
347 /* Clear any stale status bits */
350 ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
352 ao_cmd_register(&ao_adc_cmds[0]);