2 * Copyright © 2024 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 #include <ao_adc_single.h>
23 static uint8_t ao_adc_ready;
25 #define AO_ADC_CR2_VAL(start) ((HAS_ADC_TEMP << STM_ADC_CR2_TSVREF) | \
26 ((start) << STM_ADC_CR2_SWSTART) | \
27 (0 << STM_ADC_CR2_JWSTART) | \
28 (0 << STM_ADC_CR2_EXTTRIG) | \
29 (STM_ADC_CR2_EXTSEL_SWSTART << STM_ADC_CR2_EXTSEL) | \
30 (0 << STM_ADC_CR2_JEXTTRIG) | \
31 (0 << STM_ADC_CR2_JEXTSEL) | \
32 (0 << STM_ADC_CR2_ALIGN) | \
33 (1 << STM_ADC_CR2_DMA) | \
34 (0 << STM_ADC_CR2_CONT) | \
35 (1 << STM_ADC_CR2_ADON))
38 * Callback from DMA ISR
40 * Shut down DMA engine, signal anyone waiting
42 static void ao_adc_done(int index)
45 ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
47 /* Turn the ADC back off */
49 ao_wakeup((void *) &ao_adc_ready);
53 * Start the ADC sequence using the DMA engine
56 ao_adc_poll(struct ao_adc *packet)
60 ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
64 (0 << STM_DMA_CCR_MEM2MEM) |
65 (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
66 (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
67 (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
68 (1 << STM_DMA_CCR_MINC) |
69 (0 << STM_DMA_CCR_PINC) |
70 (0 << STM_DMA_CCR_CIRC) |
71 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
72 ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
73 ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
75 stm_adc1.cr2 = AO_ADC_CR2_VAL(0);
76 ao_delay(AO_MS_TO_TICKS(10));
77 stm_adc1.cr2 = AO_ADC_CR2_VAL(0);
78 ao_delay(AO_MS_TO_TICKS(10));
79 stm_adc1.cr2 = AO_ADC_CR2_VAL(1);
83 * Fetch a copy of the most recent ADC data
86 ao_adc_single_get(struct ao_adc *packet)
89 ao_arch_block_interrupts();
91 ao_sleep(&ao_adc_ready);
92 ao_arch_release_interrupts();
99 ao_adc_single_get(&packet);
100 AO_ADC_DUMP(&packet);
103 const struct ao_cmds ao_adc_cmds[] = {
104 { ao_adc_dump, "a\0Display current ADC values" },
109 adc_pin_set(struct stm_gpio *gpio, int pin)
111 ao_enable_port(gpio);
112 stm_gpio_conf(gpio, pin,
113 STM_GPIO_CR_MODE_INPUT,
114 STM_GPIO_CR_CNF_INPUT_ANALOG);
118 ao_adc_single_init(void)
120 #ifdef AO_ADC_PIN0_PORT
121 adc_pin_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN);
123 #ifdef AO_ADC_PIN1_PORT
124 adc_pin_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN);
126 #ifdef AO_ADC_PIN2_PORT
127 adc_pin_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN);
129 #ifdef AO_ADC_PIN3_PORT
130 adc_pin_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN);
132 #ifdef AO_ADC_PIN4_PORT
133 adc_pin_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN);
135 #ifdef AO_ADC_PIN5_PORT
136 adc_pin_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN);
138 #ifdef AO_ADC_PIN6_PORT
139 adc_pin_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN);
141 #ifdef AO_ADC_PIN7_PORT
142 adc_pin_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN);
144 #ifdef AO_ADC_PIN8_PORT
145 adc_pin_set(AO_ADC_PIN8_PORT, AO_ADC_PIN8_PIN);
147 #ifdef AO_ADC_PIN9_PORT
148 adc_pin_set(AO_ADC_PIN9_PORT, AO_ADC_PIN9_PIN);
150 #ifdef AO_ADC_PIN10_PORT
151 adc_pin_set(AO_ADC_PIN10_PORT, AO_ADC_PIN10_PIN);
153 #ifdef AO_ADC_PIN11_PORT
154 adc_pin_set(AO_ADC_PIN11_PORT, AO_ADC_PIN11_PIN);
156 #ifdef AO_ADC_PIN12_PORT
157 adc_pin_set(AO_ADC_PIN12_PORT, AO_ADC_PIN12_PIN);
159 #ifdef AO_ADC_PIN13_PORT
160 adc_pin_set(AO_ADC_PIN13_PORT, AO_ADC_PIN13_PIN);
162 #ifdef AO_ADC_PIN14_PORT
163 adc_pin_set(AO_ADC_PIN14_PORT, AO_ADC_PIN14_PIN);
165 #ifdef AO_ADC_PIN15_PORT
166 adc_pin_set(AO_ADC_PIN15_PORT, AO_ADC_PIN15_PIN);
168 #ifdef AO_ADC_PIN16_PORT
169 adc_pin_set(AO_ADC_PIN16_PORT, AO_ADC_PIN16_PIN);
171 #ifdef AO_ADC_PIN17_PORT
172 adc_pin_set(AO_ADC_PIN17_PORT, AO_ADC_PIN17_PIN);
174 #ifdef AO_ADC_PIN18_PORT
175 adc_pin_set(AO_ADC_PIN18_PORT, AO_ADC_PIN18_PIN);
177 #ifdef AO_ADC_PIN19_PORT
178 adc_pin_set(AO_ADC_PIN19_PORT, AO_ADC_PIN19_PIN);
180 #ifdef AO_ADC_PIN20_PORT
181 adc_pin_set(AO_ADC_PIN20_PORT, AO_ADC_PIN20_PIN);
183 #ifdef AO_ADC_PIN21_PORT
184 adc_pin_set(AO_ADC_PIN21_PORT, AO_ADC_PIN21_PIN);
186 #ifdef AO_ADC_PIN22_PORT
187 adc_pin_set(AO_ADC_PIN22_PORT, AO_ADC_PIN22_PIN);
189 #ifdef AO_ADC_PIN23_PORT
190 adc_pin_set(AO_ADC_PIN23_PORT, AO_ADC_PIN23_PIN);
192 #ifdef AO_ADC_PIN24_PORT
193 #error "Too many ADC ports"
196 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
198 /* Turn off ADC during configuration */
201 stm_adc1.cr1 = ((0 << STM_ADC_CR1_AWDEN ) |
202 (0 << STM_ADC_CR1_JAWDEN ) |
203 (STM_ADC_CR1_DUALMOD_INDEPENDENT << STM_ADC_CR1_DUALMOD ) |
204 (0 << STM_ADC_CR1_DISCNUM ) |
205 (0 << STM_ADC_CR1_JDISCEN ) |
206 (0 << STM_ADC_CR1_DISCEN ) |
207 (0 << STM_ADC_CR1_JAUTO ) |
208 (0 << STM_ADC_CR1_AWDSGL ) |
209 (1 << STM_ADC_CR1_SCAN ) |
210 (0 << STM_ADC_CR1_JEOCIE ) |
211 (0 << STM_ADC_CR1_AWDIE ) |
212 (0 << STM_ADC_CR1_EOCIE ) |
213 (0 << STM_ADC_CR1_AWDCH ));
215 /* 384 cycle sample time for everyone */
216 stm_adc1.smpr1 = 0x00ffffff;
217 stm_adc1.smpr2 = 0x3fffffff;
219 stm_adc1.sqr1 = ((AO_NUM_ADC - 1) << 20);
221 stm_adc1.sqr3 |= (AO_ADC_SQ1 << 0);
224 stm_adc1.sqr3 |= (AO_ADC_SQ2 << 5);
227 stm_adc1.sqr3 |= (AO_ADC_SQ3 << 10);
230 stm_adc1.sqr3 |= (AO_ADC_SQ4 << 15);
233 stm_adc1.sqr3 |= (AO_ADC_SQ5 << 20);
236 stm_adc1.sqr3 |= (AO_ADC_SQ6 << 25);
239 stm_adc1.sqr2 |= (AO_ADC_SQ7 << 0);
242 stm_adc1.sqr2 |= (AO_ADC_SQ8 << 5);
245 stm_adc1.sqr2 |= (AO_ADC_SQ9 << 10);
248 stm_adc1.sqr2 |= (AO_ADC_SQ10 << 15);
251 stm_adc1.sqr2 |= (AO_ADC_SQ11 << 20);
254 stm_adc1.sqr2 |= (AO_ADC_SQ12 << 25);
257 stm_adc1.sqr1 |= (AO_ADC_SQ13 << 0);
260 stm_adc1.sqr1 |= (AO_ADC_SQ14 << 5);
263 stm_adc1.sqr1 |= (AO_ADC_SQ15 << 10);
266 stm_adc1.sqr1 |= (AO_ADC_SQ16 << 15);
269 #error "too many ADC channels"
272 /* Clear any stale status bits */
275 ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
277 ao_cmd_register(&ao_adc_cmds[0]);