2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
23 typedef volatile uint32_t vuint32_t;
24 typedef volatile void * vvoid_t;
41 #define STM_MODER_SHIFT(pin) ((pin) << 1)
42 #define STM_MODER_MASK 3
43 #define STM_MODER_INPUT 0
44 #define STM_MODER_OUTPUT 1
45 #define STM_MODER_ALTERNATE 2
46 #define STM_MODER_ANALOG 3
49 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
50 gpio->moder = ((gpio->moder &
51 ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
52 value << STM_MODER_SHIFT(pin));
55 static inline vuint32_t
56 stm_moder_get(struct stm_gpio *gpio, int pin) {
57 return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
60 #define STM_OTYPER_SHIFT(pin) (pin)
61 #define STM_OTYPER_MASK 1
62 #define STM_OTYPER_PUSH_PULL 0
63 #define STM_OTYPER_OPEN_DRAIN 1
66 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
67 gpio->otyper = ((gpio->otyper &
68 ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
69 value << STM_OTYPER_SHIFT(pin));
72 static inline vuint32_t
73 stm_otyper_get(struct stm_gpio *gpio, int pin) {
74 return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
77 #define STM_OSPEEDR_SHIFT(pin) ((pin) << 1)
78 #define STM_OSPEEDR_MASK 3
79 #define STM_OSPEEDR_400kHz 0
80 #define STM_OSPEEDR_2MHz 1
81 #define STM_OSPEEDR_10MHz 2
82 #define STM_OSPEEDR_40MHz 3
85 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
86 gpio->ospeedr = ((gpio->ospeedr &
87 ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
88 value << STM_OSPEEDR_SHIFT(pin));
91 static inline vuint32_t
92 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
93 return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
96 #define STM_PUPDR_SHIFT(pin) ((pin) << 1)
97 #define STM_PUPDR_MASK 3
98 #define STM_PUPDR_NONE 0
99 #define STM_PUPDR_PULL_UP 1
100 #define STM_PUPDR_PULL_DOWN 2
101 #define STM_PUPDR_RESERVED 3
104 stm_pupdr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
105 gpio->pupdr = ((gpio->pupdr &
106 ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
107 value << STM_PUPDR_SHIFT(pin));
110 static inline vuint32_t
111 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
112 return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
115 #define STM_AFR_SHIFT(pin) ((pin) << 2)
116 #define STM_AFR_MASK 0xf
117 #define STM_AFR_NONE 0
118 #define STM_AFR_AF0 0x0
119 #define STM_AFR_AF1 0x1
120 #define STM_AFR_AF2 0x2
121 #define STM_AFR_AF3 0x3
122 #define STM_AFR_AF4 0x4
123 #define STM_AFR_AF5 0x5
124 #define STM_AFR_AF6 0x6
125 #define STM_AFR_AF7 0x7
126 #define STM_AFR_AF8 0x8
127 #define STM_AFR_AF9 0x9
128 #define STM_AFR_AF10 0xa
129 #define STM_AFR_AF11 0xb
130 #define STM_AFR_AF12 0xc
131 #define STM_AFR_AF13 0xd
132 #define STM_AFR_AF14 0xe
133 #define STM_AFR_AF15 0xf
136 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
138 * Set alternate pin mode too
140 stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
142 gpio->afrl = ((gpio->afrl &
143 ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
144 value << STM_AFR_SHIFT(pin));
147 gpio->afrh = ((gpio->afrh &
148 ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
149 value << STM_AFR_SHIFT(pin));
153 static inline uint32_t
154 stm_afr_get(struct stm_gpio *gpio, int pin) {
156 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
159 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
164 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
165 /* Use the bit set/reset register to do this atomically */
166 gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
169 static inline uint8_t
170 stm_gpio_isset(struct stm_gpio *gpio, int pin) {
171 return (gpio->idr >> pin) & 1;
174 extern struct stm_gpio stm_gpioa;
175 extern struct stm_gpio stm_gpiob;
176 extern struct stm_gpio stm_gpioc;
177 extern struct stm_gpio stm_gpiod;
178 extern struct stm_gpio stm_gpioe;
179 extern struct stm_gpio stm_gpioh;
182 vuint32_t sr; /* status register */
183 vuint32_t dr; /* data register */
184 vuint32_t brr; /* baud rate register */
185 vuint32_t cr1; /* control register 1 */
187 vuint32_t cr2; /* control register 2 */
188 vuint32_t cr3; /* control register 3 */
189 vuint32_t gtpr; /* guard time and prescaler */
192 extern struct stm_usart stm_usart1;
193 extern struct stm_usart stm_usart2;
194 extern struct stm_usart stm_usart3;
196 #define STM_USART_SR_CTS (9) /* CTS flag */
197 #define STM_USART_SR_LBD (8) /* LIN break detection flag */
198 #define STM_USART_SR_TXE (7) /* Transmit data register empty */
199 #define STM_USART_SR_TC (6) /* Transmission complete */
200 #define STM_USART_SR_RXNE (5) /* Read data register not empty */
201 #define STM_USART_SR_IDLE (4) /* IDLE line detected */
202 #define STM_USART_SR_ORE (3) /* Overrun error */
203 #define STM_USART_SR_NF (2) /* Noise detected flag */
204 #define STM_USART_SR_FE (1) /* Framing error */
205 #define STM_USART_SR_PE (0) /* Parity error */
207 #define STM_USART_CR1_OVER8 (15) /* Oversampling mode */
208 #define STM_USART_CR1_UE (13) /* USART enable */
209 #define STM_USART_CR1_M (12) /* Word length */
210 #define STM_USART_CR1_WAKE (11) /* Wakeup method */
211 #define STM_USART_CR1_PCE (10) /* Parity control enable */
212 #define STM_USART_CR1_PS (9) /* Parity selection */
213 #define STM_USART_CR1_PEIE (8) /* PE interrupt enable */
214 #define STM_USART_CR1_TXEIE (7) /* TXE interrupt enable */
215 #define STM_USART_CR1_TCIE (6) /* Transmission complete interrupt enable */
216 #define STM_USART_CR1_RXNEIE (5) /* RXNE interrupt enable */
217 #define STM_USART_CR1_IDLEIE (4) /* IDLE interrupt enable */
218 #define STM_USART_CR1_TE (3) /* Transmitter enable */
219 #define STM_USART_CR1_RE (2) /* Receiver enable */
220 #define STM_USART_CR1_RWU (1) /* Receiver wakeup */
221 #define STM_USART_CR1_SBK (0) /* Send break */
223 #define STM_USART_CR2_LINEN (14) /* LIN mode enable */
224 #define STM_USART_CR2_STOP (12) /* STOP bits */
225 #define STM_USART_CR2_STOP_MASK 3
226 #define STM_USART_CR2_STOP_1 0
227 #define STM_USART_CR2_STOP_0_5 1
228 #define STM_USART_CR2_STOP_2 2
229 #define STM_USART_CR2_STOP_1_5 3
231 #define STM_USART_CR2_CLKEN (11) /* Clock enable */
232 #define STM_USART_CR2_CPOL (10) /* Clock polarity */
233 #define STM_USART_CR2_CPHA (9) /* Clock phase */
234 #define STM_USART_CR2_LBCL (8) /* Last bit clock pulse */
235 #define STM_USART_CR2_LBDIE (6) /* LIN break detection interrupt enable */
236 #define STM_USART_CR2_LBDL (5) /* lin break detection length */
237 #define STM_USART_CR2_ADD (0)
238 #define STM_USART_CR2_ADD_MASK 0xf
240 #define STM_USART_CR3_ONEBITE (11) /* One sample bit method enable */
241 #define STM_USART_CR3_CTSIE (10) /* CTS interrupt enable */
242 #define STM_USART_CR3_CTSE (9) /* CTS enable */
243 #define STM_USART_CR3_RTSE (8) /* RTS enable */
244 #define STM_USART_CR3_DMAT (7) /* DMA enable transmitter */
245 #define STM_USART_CR3_DMAR (6) /* DMA enable receiver */
246 #define STM_USART_CR3_SCEN (5) /* Smartcard mode enable */
247 #define STM_USART_CR3_NACK (4) /* Smartcard NACK enable */
248 #define STM_USART_CR3_HDSEL (3) /* Half-duplex selection */
249 #define STM_USART_CR3_IRLP (2) /* IrDA low-power */
250 #define STM_USART_CR3_IREN (1) /* IrDA mode enable */
251 #define STM_USART_CR3_EIE (0) /* Error interrupt enable */
256 extern struct stm_tim stm_tim9;
257 extern struct stm_tim stm_tim10;
258 extern struct stm_tim stm_tim11;
260 /* Flash interface */
276 extern struct stm_flash stm_flash;
278 #define STM_FLASH_ACR_RUN_PD (4)
279 #define STM_FLASH_ACR_SLEEP_PD (3)
280 #define STM_FLASH_ACR_ACC64 (2)
281 #define STM_FLASH_ACR_PRFEN (1)
282 #define STM_FLASH_ACR_LATENCY (0)
304 extern struct stm_rcc stm_rcc;
306 #define STM_RCC_CR_RTCPRE (29)
307 #define STM_RCC_CR_RTCPRE_HSE_DIV_2 0
308 #define STM_RCC_CR_RTCPRE_HSE_DIV_4 1
309 #define STM_RCC_CR_RTCPRE_HSE_DIV_8 2
310 #define STM_RCC_CR_RTCPRE_HSE_DIV_16 3
311 #define STM_RCC_CR_RTCPRE_HSE_MASK 3
313 #define STM_RCC_CR_CSSON (28)
314 #define STM_RCC_CR_PLLRDY (25)
315 #define STM_RCC_CR_PLLON (24)
316 #define STM_RCC_CR_HSEBYP (18)
317 #define STM_RCC_CR_HSERDY (17)
318 #define STM_RCC_CR_HSEON (16)
319 #define STM_RCC_CR_MSIRDY (9)
320 #define STM_RCC_CR_MSION (8)
321 #define STM_RCC_CR_HSIRDY (1)
322 #define STM_RCC_CR_HSION (0)
324 #define STM_RCC_CFGR_MCOPRE (28)
325 #define STM_RCC_CFGR_MCOPRE_DIV_1 0
326 #define STM_RCC_CFGR_MCOPRE_DIV_2 1
327 #define STM_RCC_CFGR_MCOPRE_DIV_4 2
328 #define STM_RCC_CFGR_MCOPRE_DIV_8 3
329 #define STM_RCC_CFGR_MCOPRE_DIV_16 4
330 #define STM_RCC_CFGR_MCOPRE_DIV_MASK 7
332 #define STM_RCC_CFGR_MCOSEL (24)
333 #define STM_RCC_CFGR_MCOSEL_DISABLE 0
334 #define STM_RCC_CFGR_MCOSEL_SYSCLK 1
335 #define STM_RCC_CFGR_MCOSEL_HSI 2
336 #define STM_RCC_CFGR_MCOSEL_MSI 3
337 #define STM_RCC_CFGR_MCOSEL_HSE 4
338 #define STM_RCC_CFGR_MCOSEL_PLL 5
339 #define STM_RCC_CFGR_MCOSEL_LSI 6
340 #define STM_RCC_CFGR_MCOSEL_LSE 7
341 #define STM_RCC_CFGR_MCOSEL_MASK 7
343 #define STM_RCC_CFGR_PLLDIV (22)
344 #define STM_RCC_CFGR_PLLDIV_2 1
345 #define STM_RCC_CFGR_PLLDIV_3 2
346 #define STM_RCC_CFGR_PLLDIV_4 3
347 #define STM_RCC_CFGR_PLLDIV_MASK 3
349 #define STM_RCC_CFGR_PLLMUL (18)
350 #define STM_RCC_CFGR_PLLMUL_3 0
351 #define STM_RCC_CFGR_PLLMUL_4 1
352 #define STM_RCC_CFGR_PLLMUL_6 2
353 #define STM_RCC_CFGR_PLLMUL_8 3
354 #define STM_RCC_CFGR_PLLMUL_12 4
355 #define STM_RCC_CFGR_PLLMUL_16 5
356 #define STM_RCC_CFGR_PLLMUL_24 6
357 #define STM_RCC_CFGR_PLLMUL_32 7
358 #define STM_RCC_CFGR_PLLMUL_48 8
359 #define STM_RCC_CFGR_PLLMUL_MASK 0xf
361 #define STM_RCC_CFGR_PLLSRC (16)
363 #define STM_RCC_CFGR_PPRE2 (11)
364 #define STM_RCC_CFGR_PPRE2_DIV_1 0
365 #define STM_RCC_CFGR_PPRE2_DIV_2 4
366 #define STM_RCC_CFGR_PPRE2_DIV_4 5
367 #define STM_RCC_CFGR_PPRE2_DIV_8 6
368 #define STM_RCC_CFGR_PPRE2_DIV_16 7
369 #define STM_RCC_CFGR_PPRE2_MASK 7
371 #define STM_RCC_CFGR_PPRE1 (8)
372 #define STM_RCC_CFGR_PPRE1_DIV_1 0
373 #define STM_RCC_CFGR_PPRE1_DIV_2 4
374 #define STM_RCC_CFGR_PPRE1_DIV_4 5
375 #define STM_RCC_CFGR_PPRE1_DIV_8 6
376 #define STM_RCC_CFGR_PPRE1_DIV_16 7
377 #define STM_RCC_CFGR_PPRE1_MASK 7
379 #define STM_RCC_CFGR_HPRE (4)
380 #define STM_RCC_CFGR_HPRE_DIV_1 0
381 #define STM_RCC_CFGR_HPRE_DIV_2 8
382 #define STM_RCC_CFGR_HPRE_DIV_4 9
383 #define STM_RCC_CFGR_HPRE_DIV_8 0xa
384 #define STM_RCC_CFGR_HPRE_DIV_16 0xb
385 #define STM_RCC_CFGR_HPRE_DIV_64 0xc
386 #define STM_RCC_CFGR_HPRE_DIV_128 0xd
387 #define STM_RCC_CFGR_HPRE_DIV_256 0xe
388 #define STM_RCC_CFGR_HPRE_DIV_512 0xf
389 #define STM_RCC_CFGR_HPRE_MASK 0xf
391 #define STM_RCC_CFGR_SWS (2)
392 #define STM_RCC_CFGR_SWS_MSI 0
393 #define STM_RCC_CFGR_SWS_HSI 1
394 #define STM_RCC_CFGR_SWS_HSE 2
395 #define STM_RCC_CFGR_SWS_PLL 3
396 #define STM_RCC_CFGR_SWS_MASK 3
398 #define STM_RCC_CFGR_SW (0)
399 #define STM_RCC_CFGR_SW_MSI 0
400 #define STM_RCC_CFGR_SW_HSI 1
401 #define STM_RCC_CFGR_SW_HSE 2
402 #define STM_RCC_CFGR_SW_PLL 3
403 #define STM_RCC_CFGR_SW_MASK 3
405 #define STM_RCC_AHBENR_DMA1EN (24)
406 #define STM_RCC_AHBENR_FLITFEN (15)
407 #define STM_RCC_AHBENR_CRCEN (12)
408 #define STM_RCC_AHBENR_GPIOHEN (5)
409 #define STM_RCC_AHBENR_GPIOEEN (4)
410 #define STM_RCC_AHBENR_GPIODEN (3)
411 #define STM_RCC_AHBENR_GPIOCEN (2)
412 #define STM_RCC_AHBENR_GPIOBEN (1)
413 #define STM_RCC_AHBENR_GPIOAEN (0)
415 #define STM_RCC_APB2ENR_USART1EN (14)
416 #define STM_RCC_APB2ENR_SPI1EN (12)
417 #define STM_RCC_APB2ENR_ADC1EN (9)
418 #define STM_RCC_APB2ENR_TIM11EN (4)
419 #define STM_RCC_APB2ENR_TIM10EN (3)
420 #define STM_RCC_APB2ENR_TIM9EN (2)
421 #define STM_RCC_APB2ENR_SYSCFGEN (0)
423 #define STM_RCC_APB1ENR_COMPEN (31)
424 #define STM_RCC_APB1ENR_DACEN (29)
425 #define STM_RCC_APB1ENR_PWREN (28)
426 #define STM_RCC_APB1ENR_USBEN (23)
427 #define STM_RCC_APB1ENR_I2C2EN (22)
428 #define STM_RCC_APB1ENR_I2C1EN (21)
429 #define STM_RCC_APB1ENR_USART3EN (18)
430 #define STM_RCC_APB1ENR_USART2EN (17)
431 #define STM_RCC_APB1ENR_SPI2EN (14)
432 #define STM_RCC_APB1ENR_WWDGEN (11)
433 #define STM_RCC_APB1ENR_LCDEN (9)
434 #define STM_RCC_APB1ENR_TIM7EN (5)
435 #define STM_RCC_APB1ENR_TIM6EN (4)
436 #define STM_RCC_APB1ENR_TIM4EN (2)
437 #define STM_RCC_APB1ENR_TIM3EN (1)
438 #define STM_RCC_APB1ENR_TIM2EN (0)
440 #define STM_RCC_CSR_LPWRRSTF (31)
441 #define STM_RCC_CSR_WWDGRSTF (30)
442 #define STM_RCC_CSR_IWDGRSTF (29)
443 #define STM_RCC_CSR_SFTRSTF (28)
444 #define STM_RCC_CSR_PORRSTF (27)
445 #define STM_RCC_CSR_PINRSTF (26)
446 #define STM_RCC_CSR_OBLRSTF (25)
447 #define STM_RCC_CSR_RMVF (24)
448 #define STM_RCC_CSR_RTFRST (23)
449 #define STM_RCC_CSR_RTCEN (22)
450 #define STM_RCC_CSR_RTCSEL (16)
452 #define STM_RCC_CSR_RTCSEL_NONE 0
453 #define STM_RCC_CSR_RTCSEL_LSE 1
454 #define STM_RCC_CSR_RTCSEL_LSI 2
455 #define STM_RCC_CSR_RTCSEL_HSE 3
456 #define STM_RCC_CSR_RTCSEL_MASK 3
458 #define STM_RCC_CSR_LSEBYP (10)
459 #define STM_RCC_CSR_LSERDY (9)
460 #define STM_RCC_CSR_LSEON (8)
461 #define STM_RCC_CSR_LSIRDY (1)
462 #define STM_RCC_CSR_LSION (0)
469 extern struct stm_pwr stm_pwr;
471 #define STM_PWR_CR_LPRUN (14)
473 #define STM_PWR_CR_VOS (11)
474 #define STM_PWR_CR_VOS_1_8 1
475 #define STM_PWR_CR_VOS_1_5 2
476 #define STM_PWR_CR_VOS_1_2 3
477 #define STM_PWR_CR_VOS_MASK 3
479 #define STM_PWR_CR_FWU (10)
480 #define STM_PWR_CR_ULP (9)
481 #define STM_PWR_CR_DBP (8)
483 #define STM_PWR_CR_PLS (5)
484 #define STM_PWR_CR_PLS_1_9 0
485 #define STM_PWR_CR_PLS_2_1 1
486 #define STM_PWR_CR_PLS_2_3 2
487 #define STM_PWR_CR_PLS_2_5 3
488 #define STM_PWR_CR_PLS_2_7 4
489 #define STM_PWR_CR_PLS_2_9 5
490 #define STM_PWR_CR_PLS_3_1 6
491 #define STM_PWR_CR_PLS_EXT 7
492 #define STM_PWR_CR_PLS_MASK 7
494 #define STM_PWR_CR_PVDE (4)
495 #define STM_PWR_CR_CSBF (3)
496 #define STM_PWR_CR_CWUF (2)
497 #define STM_PWR_CR_PDDS (1)
498 #define STM_PWR_CR_LPSDSR (0)
500 #define STM_PWR_CSR_EWUP3 (10)
501 #define STM_PWR_CSR_EWUP2 (9)
502 #define STM_PWR_CSR_EWUP1 (8)
503 #define STM_PWR_CSR_REGLPF (5)
504 #define STM_PWR_CSR_VOSF (4)
505 #define STM_PWR_CSR_VREFINTRDYF (3)
506 #define STM_PWR_CSR_PVDO (2)
507 #define STM_PWR_CSR_SBF (1)
508 #define STM_PWR_CSR_WUF (0)
527 extern struct stm_tim67 stm_tim6;
529 #define STM_TIM67_CR1_ARPE (7)
530 #define STM_TIM67_CR1_OPM (3)
531 #define STM_TIM67_CR1_URS (2)
532 #define STM_TIM67_CR1_UDIS (1)
533 #define STM_TIM67_CR1_CEN (0)
535 #define STM_TIM67_CR2_MMS (4)
536 #define STM_TIM67_CR2_MMS_RESET 0
537 #define STM_TIM67_CR2_MMS_ENABLE 1
538 #define STM_TIM67_CR2_MMS_UPDATE 2
539 #define STM_TIM67_CR2_MMS_MASK 7
541 #define STM_TIM67_DIER_UDE (8)
542 #define STM_TIM67_DIER_UIE (0)
544 #define STM_TIM67_SR_UIF (0)
546 #define STM_TIM67_EGR_UG (0)
553 uint32_t unused_0x10;
557 extern struct stm_lcd stm_lcd;
559 #define STM_LCD_CR_MUX_SEG (7)
561 #define STM_LCD_CR_BIAS (5)
562 #define STM_LCD_CR_BIAS_1_4 0
563 #define STM_LCD_CR_BIAS_1_2 1
564 #define STM_LCD_CR_BIAS_1_3 2
565 #define STM_LCD_CR_BIAS_MASK 3
567 #define STM_LCD_CR_DUTY (2)
568 #define STM_LCD_CR_DUTY_STATIC 0
569 #define STM_LCD_CR_DUTY_1_2 1
570 #define STM_LCD_CR_DUTY_1_3 2
571 #define STM_LCD_CR_DUTY_1_4 3
572 #define STM_LCD_CR_DUTY_1_8 4
573 #define STM_LCD_CR_DUTY_MASK 7
575 #define STM_LCD_CR_VSEL (1)
576 #define STM_LCD_CR_LCDEN (0)
578 #define STM_LCD_FCR_PS (22)
579 #define STM_LCD_FCR_PS_1 0x0
580 #define STM_LCD_FCR_PS_2 0x1
581 #define STM_LCD_FCR_PS_4 0x2
582 #define STM_LCD_FCR_PS_8 0x3
583 #define STM_LCD_FCR_PS_16 0x4
584 #define STM_LCD_FCR_PS_32 0x5
585 #define STM_LCD_FCR_PS_64 0x6
586 #define STM_LCD_FCR_PS_128 0x7
587 #define STM_LCD_FCR_PS_256 0x8
588 #define STM_LCD_FCR_PS_512 0x9
589 #define STM_LCD_FCR_PS_1024 0xa
590 #define STM_LCD_FCR_PS_2048 0xb
591 #define STM_LCD_FCR_PS_4096 0xc
592 #define STM_LCD_FCR_PS_8192 0xd
593 #define STM_LCD_FCR_PS_16384 0xe
594 #define STM_LCD_FCR_PS_32768 0xf
595 #define STM_LCD_FCR_PS_MASK 0xf
597 #define STM_LCD_FCR_DIV (18)
598 #define STM_LCD_FCR_DIV_16 0x0
599 #define STM_LCD_FCR_DIV_17 0x1
600 #define STM_LCD_FCR_DIV_18 0x2
601 #define STM_LCD_FCR_DIV_19 0x3
602 #define STM_LCD_FCR_DIV_20 0x4
603 #define STM_LCD_FCR_DIV_21 0x5
604 #define STM_LCD_FCR_DIV_22 0x6
605 #define STM_LCD_FCR_DIV_23 0x7
606 #define STM_LCD_FCR_DIV_24 0x8
607 #define STM_LCD_FCR_DIV_25 0x9
608 #define STM_LCD_FCR_DIV_26 0xa
609 #define STM_LCD_FCR_DIV_27 0xb
610 #define STM_LCD_FCR_DIV_28 0xc
611 #define STM_LCD_FCR_DIV_29 0xd
612 #define STM_LCD_FCR_DIV_30 0xe
613 #define STM_LCD_FCR_DIV_31 0xf
614 #define STM_LCD_FCR_DIV_MASK 0xf
616 #define STM_LCD_FCR_BLINK (16)
617 #define STM_LCD_FCR_BLINK_DISABLE 0
618 #define STM_LCD_FCR_BLINK_SEG0_COM0 1
619 #define STM_LCD_FCR_BLINK_SEG0_COMALL 2
620 #define STM_LCD_FCR_BLINK_SEGALL_COMALL 3
621 #define STM_LCD_FCR_BLINK_MASK 3
623 #define STM_LCD_FCR_BLINKF (13)
624 #define STM_LCD_FCR_BLINKF_8 0
625 #define STM_LCD_FCR_BLINKF_16 1
626 #define STM_LCD_FCR_BLINKF_32 2
627 #define STM_LCD_FCR_BLINKF_64 3
628 #define STM_LCD_FCR_BLINKF_128 4
629 #define STM_LCD_FCR_BLINKF_256 5
630 #define STM_LCD_FCR_BLINKF_512 6
631 #define STM_LCD_FCR_BLINKF_1024 7
632 #define STM_LCD_FCR_BLINKF_MASK 7
634 #define STM_LCD_FCR_CC (10)
635 #define STM_LCD_FCR_CC_MASK 7
637 #define STM_LCD_FCR_DEAD (7)
638 #define STM_LCD_FCR_DEAD_MASK 7
640 #define STM_LCD_FCR_PON (4)
641 #define STM_LCD_FCR_PON_MASK 7
643 #define STM_LCD_FCR_UDDIE (3)
644 #define STM_LCD_FCR_SOFIE (1)
645 #define STM_LCD_FCR_HD (0)
647 #define STM_LCD_SR_FCRSF (5)
648 #define STM_LCD_SR_RDY (4)
649 #define STM_LCD_SR_UDD (3)
650 #define STM_LCD_SR_UDR (2)
651 #define STM_LCD_SR_SOF (1)
652 #define STM_LCD_SR_ENS (0)
654 #define STM_LCD_CLR_UDDC (3)
655 #define STM_LCD_CLR_SOFC (1)
658 vuint32_t iser[3]; /* 0x000 */
660 uint8_t _unused00c[0x080 - 0x00c];
662 vuint32_t icer[3]; /* 0x080 */
664 uint8_t _unused08c[0x100 - 0x08c];
666 vuint32_t ispr[3]; /* 0x100 */
668 uint8_t _unused10c[0x180 - 0x10c];
670 vuint32_t icpr[3]; /* 0x180 */
672 uint8_t _unused18c[0x200 - 0x18c];
674 vuint32_t iabr[3]; /* 0x200 */
676 uint8_t _unused20c[0x300 - 0x20c];
678 vuint32_t ipr[21]; /* 0x300 */
680 uint8_t _unused324[0xe00 - 0x324];
682 vuint32_t stir; /* 0xe00 */
685 extern struct stm_nvic stm_nvic;
687 #define IRQ_REG(irq) ((irq) >> 5)
688 #define IRQ_BIT(irq) ((irq) & 0x1f)
689 #define IRQ_MASK(irq) (1 << IRQ_BIT(irq))
690 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
693 stm_nvic_set_enable(int irq) {
694 stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
698 stm_nvic_clear_enable(int irq) {
699 stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
703 stm_nvic_enabled(int irq) {
704 return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
708 stm_nvic_set_pending(int irq) {
709 stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
713 stm_nvic_clear_pending(int irq) {
714 stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
718 stm_nvic_pending(int irq) {
719 return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
723 stm_nvic_active(int irq) {
724 return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
727 #define IRQ_PRIO_REG(irq) ((irq) >> 2)
728 #define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3)
729 #define IRQ_PRIO_MASK(irq) (0xff << IRQ_PRIO_BIT(irq))
732 stm_nvic_set_priority(int irq, uint8_t prio) {
733 int n = IRQ_PRIO_REG(irq);
737 v &= ~IRQ_PRIO_MASK(irq);
738 v |= (prio) << IRQ_PRIO_BIT(irq);
742 static inline uint8_t
743 stm_nvic_get_priority(int irq) {
744 return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
747 #define isr(name) void stm_ ## name ## _isr(void);
806 #define STM_ISR_WWDG_POS 0
807 #define STM_ISR_PVD_POS 1
808 #define STM_ISR_TAMPER_STAMP_POS 2
809 #define STM_ISR_RTC_WKUP_POS 3
810 #define STM_ISR_FLASH_POS 4
811 #define STM_ISR_RCC_POS 5
812 #define STM_ISR_EXTI0_POS 6
813 #define STM_ISR_EXTI1_POS 7
814 #define STM_ISR_EXTI2_POS 8
815 #define STM_ISR_EXTI3_POS 9
816 #define STM_ISR_EXTI4_POS 10
817 #define STM_ISR_DMA1_CHANNEL1_POS 11
818 #define STM_ISR_DMA2_CHANNEL1_POS 12
819 #define STM_ISR_DMA3_CHANNEL1_POS 13
820 #define STM_ISR_DMA4_CHANNEL1_POS 14
821 #define STM_ISR_DMA5_CHANNEL1_POS 15
822 #define STM_ISR_DMA6_CHANNEL1_POS 16
823 #define STM_ISR_DMA7_CHANNEL1_POS 17
824 #define STM_ISR_ADC1_POS 18
825 #define STM_ISR_USB_HP_POS 19
826 #define STM_ISR_USB_LP_POS 20
827 #define STM_ISR_DAC_POS 21
828 #define STM_ISR_COMP_POS 22
829 #define STM_ISR_EXTI9_5_POS 23
830 #define STM_ISR_LCD_POS 24
831 #define STM_ISR_TIM9_POS 25
832 #define STM_ISR_TIM10_POS 26
833 #define STM_ISR_TIM11_POS 27
834 #define STM_ISR_TIM2_POS 28
835 #define STM_ISR_TIM3_POS 29
836 #define STM_ISR_TIM4_POS 30
837 #define STM_ISR_I2C1_EV_POS 31
838 #define STM_ISR_I2C1_ER_POS 32
839 #define STM_ISR_I2C2_EV_POS 33
840 #define STM_ISR_I2C2_ER_POS 34
841 #define STM_ISR_SPI1_POS 35
842 #define STM_ISR_SPI2_POS 36
843 #define STM_ISR_USART1_POS 37
844 #define STM_ISR_USART2_POS 38
845 #define STM_ISR_USART3_POS 39
846 #define STM_ISR_EXTI15_10_POS 40
847 #define STM_ISR_RTC_ALARM_POS 41
848 #define STM_ISR_USB_FS_WKUP_POS 42
849 #define STM_ISR_TIM6_POS 43
850 #define STM_ISR_TIM7_POS 44
852 struct stm_dma_channel {
860 #define STM_NUM_DMA 7
865 struct stm_dma_channel channel[STM_NUM_DMA];
868 extern struct stm_dma stm_dma;
870 /* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
873 #define STM_DMA_INDEX(channel) ((channel) - 1)
875 #define STM_DMA_ISR(index) ((index) << 2)
876 #define STM_DMA_ISR_MASK 0xf
877 #define STM_DMA_ISR_TEIF 3
878 #define STM_DMA_ISR_HTIF 2
879 #define STM_DMA_ISR_TCIF 1
880 #define STM_DMA_ISR_GIF 0
882 #define STM_DMA_IFCR(index) ((index) << 2)
883 #define STM_DMA_IFCR_MASK 0xf
884 #define STM_DMA_IFCR_CTEIF 3
885 #define STM_DMA_IFCR_CHTIF 2
886 #define STM_DMA_IFCR_CTCIF 1
887 #define STM_DMA_IFCR_CGIF 0
889 #define STM_DMA_CCR_MEM2MEM (14)
891 #define STM_DMA_CCR_PL (12)
892 #define STM_DMA_CCR_PL_LOW (0)
893 #define STM_DMA_CCR_PL_MEDIUM (1)
894 #define STM_DMA_CCR_PL_HIGH (2)
895 #define STM_DMA_CCR_PL_VERY_HIGH (3)
896 #define STM_DMA_CCR_PL_MASK (3)
898 #define STM_DMA_CCR_MSIZE (10)
899 #define STM_DMA_CCR_MSIZE_8 (0)
900 #define STM_DMA_CCR_MSIZE_16 (1)
901 #define STM_DMA_CCR_MSIZE_32 (2)
902 #define STM_DMA_CCR_MSIZE_MASK (3)
904 #define STM_DMA_CCR_PSIZE (8)
905 #define STM_DMA_CCR_PSIZE_8 (0)
906 #define STM_DMA_CCR_PSIZE_16 (1)
907 #define STM_DMA_CCR_PSIZE_32 (2)
908 #define STM_DMA_CCR_PSIZE_MASK (3)
910 #define STM_DMA_CCR_MINC (7)
911 #define STM_DMA_CCR_PINC (6)
912 #define STM_DMA_CCR_CIRC (5)
913 #define STM_DMA_CCR_DIR (4)
914 #define STM_DMA_CCR_DIR_PER_TO_MEM 0
915 #define STM_DMA_CCR_DIR_MEM_TO_PER 1
916 #define STM_DMA_CCR_TEIE (3)
917 #define STM_DMA_CCR_HTIE (2)
918 #define STM_DMA_CCR_TCIE (1)
919 #define STM_DMA_CCR_EN (0)
921 #define STM_DMA_CHANNEL_ADC1 1
922 #define STM_DMA_CHANNEL_SPI1_RX 2
923 #define STM_DMA_CHANNEL_SPI1_TX 3
924 #define STM_DMA_CHANNEL_SPI2_RX 4
925 #define STM_DMA_CHANNEL_SPI2_TX 5
926 #define STM_DMA_CHANNEL_USART3_TX 2
927 #define STM_DMA_CHANNEL_USART3_RX 3
928 #define STM_DMA_CHANNEL_USART1_TX 4
929 #define STM_DMA_CHANNEL_USART1_RX 5
930 #define STM_DMA_CHANNEL_USART2_RX 6
931 #define STM_DMA_CHANNEL_USART2_TX 7
932 #define STM_DMA_CHANNEL_I2C2_TX 4
933 #define STM_DMA_CHANNEL_I2C2_RX 5
934 #define STM_DMA_CHANNEL_I2C1_RX 6
935 #define STM_DMA_CHANNEL_I2C1_TX 7
936 #define STM_DMA_CHANNEL_TIM2_CH3 1
937 #define STM_DMA_CHANNEL_TIM2_UP 2
938 #define STM_DMA_CHANNEL_TIM2_CH1 5
939 #define STM_DMA_CHANNEL_TIM2_CH2 7
940 #define STM_DMA_CHANNEL_TIM2_CH4 7
941 #define STM_DMA_CHANNEL_TIM3_CH3 2
942 #define STM_DMA_CHANNEL_TIM3_CH4 3
943 #define STM_DMA_CHANNEL_TIM3_UP 3
944 #define STM_DMA_CHANNEL_TIM3_CH1 6
945 #define STM_DMA_CHANNEL_TIM3_TRIG 6
946 #define STM_DMA_CHANNEL_TIM4_CH1 1
947 #define STM_DMA_CHANNEL_TIM4_CH2 4
948 #define STM_DMA_CHANNEL_TIM4_CH3 5
949 #define STM_DMA_CHANNEL_TIM4_UP 7
950 #define STM_DMA_CHANNEL_TIM6_UP_DA 2
951 #define STM_DMA_CHANNEL_C_CHANNEL1 2
952 #define STM_DMA_CHANNEL_TIM7_UP_DA 3
953 #define STM_DMA_CHANNEL_C_CHANNEL2 3
956 * Only spi channel 1 and 2 can use DMA
958 #define STM_NUM_SPI 2
970 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
972 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
975 #define STM_SPI_INDEX(channel) ((channel) - 1)
977 #define STM_SPI_CR1_BIDIMODE 15
978 #define STM_SPI_CR1_BIDIOE 14
979 #define STM_SPI_CR1_CRCEN 13
980 #define STM_SPI_CR1_CRCNEXT 12
981 #define STM_SPI_CR1_DFF 11
982 #define STM_SPI_CR1_RXONLY 10
983 #define STM_SPI_CR1_SSM 9
984 #define STM_SPI_CR1_SSI 8
985 #define STM_SPI_CR1_LSBFIRST 7
986 #define STM_SPI_CR1_SPE 6
987 #define STM_SPI_CR1_BR 3
988 #define STM_SPI_CR1_BR_PCLK_2 0
989 #define STM_SPI_CR1_BR_PCLK_4 1
990 #define STM_SPI_CR1_BR_PCLK_8 2
991 #define STM_SPI_CR1_BR_PCLK_16 3
992 #define STM_SPI_CR1_BR_PCLK_32 4
993 #define STM_SPI_CR1_BR_PCLK_64 5
994 #define STM_SPI_CR1_BR_PCLK_128 6
995 #define STM_SPI_CR1_BR_PCLK_256 7
996 #define STM_SPI_CR1_BR_MASK 7
998 #define STM_SPI_CR1_MSTR 2
999 #define STM_SPI_CR1_CPOL 1
1000 #define STM_SPI_CR1_CPHA 0
1002 #define STM_SPI_CR2_TXEIE 7
1003 #define STM_SPI_CR2_RXNEIE 6
1004 #define STM_SPI_CR2_ERRIE 5
1005 #define STM_SPI_CR2_SSOE 2
1006 #define STM_SPI_CR2_TXDMAEN 1
1007 #define STM_SPI_CR2_RXDMAEN 0
1009 #define STM_SPI_SR_BSY 7
1010 #define STM_SPI_SR_OVR 6
1011 #define STM_SPI_SR_MODF 5
1012 #define STM_SPI_SR_CRCERR 4
1013 #define STM_SPI_SR_TXE 1
1014 #define STM_SPI_SR_RXNE 0
1016 #endif /* _STM32L_H_ */