2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
24 typedef volatile uint32_t vuint32_t;
25 typedef volatile void * vvoid_t;
42 #define STM_MODER_SHIFT(pin) ((pin) << 1)
43 #define STM_MODER_MASK 3UL
44 #define STM_MODER_INPUT 0
45 #define STM_MODER_OUTPUT 1
46 #define STM_MODER_ALTERNATE 2
47 #define STM_MODER_ANALOG 3
50 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
51 gpio->moder = ((gpio->moder &
52 (uint32_t) ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
53 value << STM_MODER_SHIFT(pin));
56 static inline uint32_t
57 stm_spread_mask(uint16_t mask) {
60 /* 0000000000000000mmmmmmmmmmmmmmmm */
61 m = (m & 0xff) | ((m & 0xff00) << 8);
62 /* 00000000mmmmmmmm00000000mmmmmmmm */
63 m = (m & 0x000f000f) | ((m & 0x00f000f0) << 4);
64 /* 0000mmmm0000mmmm0000mmmm0000mmmm */
65 m = (m & 0x03030303) | ((m & 0x0c0c0c0c) << 2);
66 /* 00mm00mm00mm00mm00mm00mm00mm00mm */
67 m = (m & 0x11111111) | ((m & 0x22222222) << 2);
68 /* 0m0m0m0m0m0m0m0m0m0m0m0m0m0m0m0m */
73 stm_moder_set_mask(struct stm_gpio *gpio, uint16_t mask, uint32_t value) {
74 uint32_t bits32 = stm_spread_mask(mask);
75 uint32_t mask32 = 3 * bits32;
76 uint32_t value32 = (value & 3) * bits32;
78 gpio->moder = ((gpio->moder & ~mask32) | value32);
81 static inline uint32_t
82 stm_moder_get(struct stm_gpio *gpio, int pin) {
83 return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
86 #define STM_OTYPER_SHIFT(pin) (pin)
87 #define STM_OTYPER_MASK 1UL
88 #define STM_OTYPER_PUSH_PULL 0
89 #define STM_OTYPER_OPEN_DRAIN 1
92 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
93 gpio->otyper = ((gpio->otyper &
94 (uint32_t) ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
95 value << STM_OTYPER_SHIFT(pin));
98 static inline uint32_t
99 stm_otyper_get(struct stm_gpio *gpio, int pin) {
100 return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
103 #define STM_OSPEEDR_SHIFT(pin) ((pin) << 1)
104 #define STM_OSPEEDR_MASK 3UL
105 #define STM_OSPEEDR_400kHz 0
106 #define STM_OSPEEDR_2MHz 1
107 #define STM_OSPEEDR_10MHz 2
108 #define STM_OSPEEDR_40MHz 3
111 stm_ospeedr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
112 gpio->ospeedr = ((gpio->ospeedr &
113 (uint32_t) ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
114 value << STM_OSPEEDR_SHIFT(pin));
118 stm_ospeedr_set_mask(struct stm_gpio *gpio, uint16_t mask, uint32_t value) {
119 uint32_t bits32 = stm_spread_mask(mask);
120 uint32_t mask32 = 3 * bits32;
121 uint32_t value32 = (value & 3) * bits32;
123 gpio->ospeedr = ((gpio->ospeedr & ~mask32) | value32);
126 static inline uint32_t
127 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
128 return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
131 #define STM_PUPDR_SHIFT(pin) ((pin) << 1)
132 #define STM_PUPDR_MASK 3UL
133 #define STM_PUPDR_NONE 0
134 #define STM_PUPDR_PULL_UP 1
135 #define STM_PUPDR_PULL_DOWN 2
136 #define STM_PUPDR_RESERVED 3
139 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
140 gpio->pupdr = ((gpio->pupdr &
141 (uint32_t) ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
142 value << STM_PUPDR_SHIFT(pin));
146 stm_pupdr_set_mask(struct stm_gpio *gpio, uint16_t mask, uint32_t value) {
147 uint32_t bits32 = stm_spread_mask(mask);
148 uint32_t mask32 = 3 * bits32;
149 uint32_t value32 = (value & 3) * bits32;
151 gpio->pupdr = (gpio->pupdr & ~mask32) | value32;
154 static inline uint32_t
155 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
156 return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
159 #define STM_AFR_SHIFT(pin) ((pin) << 2)
160 #define STM_AFR_MASK 0xfUL
161 #define STM_AFR_NONE 0
162 #define STM_AFR_AF0 0x0
163 #define STM_AFR_AF1 0x1
164 #define STM_AFR_AF2 0x2
165 #define STM_AFR_AF3 0x3
166 #define STM_AFR_AF4 0x4
167 #define STM_AFR_AF5 0x5
168 #define STM_AFR_AF6 0x6
169 #define STM_AFR_AF7 0x7
170 #define STM_AFR_AF8 0x8
171 #define STM_AFR_AF9 0x9
172 #define STM_AFR_AF10 0xa
173 #define STM_AFR_AF11 0xb
174 #define STM_AFR_AF12 0xc
175 #define STM_AFR_AF13 0xd
176 #define STM_AFR_AF14 0xe
177 #define STM_AFR_AF15 0xf
180 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
182 * Set alternate pin mode too
184 stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
186 gpio->afrl = ((gpio->afrl &
187 (uint32_t) ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
188 value << STM_AFR_SHIFT(pin));
191 gpio->afrh = ((gpio->afrh &
192 (uint32_t) ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
193 value << STM_AFR_SHIFT(pin));
197 static inline uint32_t
198 stm_afr_get(struct stm_gpio *gpio, int pin) {
200 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
203 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
208 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
209 /* Use the bit set/reset register to do this atomically */
210 gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
214 stm_gpio_set_mask(struct stm_gpio *gpio, uint16_t bits, uint16_t mask) {
215 /* Use the bit set/reset register to do this atomically */
216 gpio->bsrr = ((uint32_t) (~bits & mask) << 16) | ((uint32_t) (bits & mask));
220 stm_gpio_set_bits(struct stm_gpio *gpio, uint16_t bits) {
225 stm_gpio_clr_bits(struct stm_gpio *gpio, uint16_t bits) {
226 gpio->bsrr = ((uint32_t) bits) << 16;
229 static inline uint8_t
230 stm_gpio_get(struct stm_gpio *gpio, int pin) {
231 return (gpio->idr >> pin) & 1;
234 static inline uint16_t
235 stm_gpio_get_all(struct stm_gpio *gpio) {
236 return (uint16_t) gpio->idr;
240 * We can't define these in registers.ld or our fancy
241 * ao_enable_gpio macro will expand into a huge pile of code
242 * as the compiler won't do correct constant folding and
243 * dead-code elimination
246 extern struct stm_gpio stm_gpioa;
247 extern struct stm_gpio stm_gpiob;
248 extern struct stm_gpio stm_gpioc;
249 extern struct stm_gpio stm_gpiod;
250 extern struct stm_gpio stm_gpioe;
251 extern struct stm_gpio stm_gpioh;
253 #define stm_gpioh (*((struct stm_gpio *) 0x40021400))
254 #define stm_gpioe (*((struct stm_gpio *) 0x40021000))
255 #define stm_gpiod (*((struct stm_gpio *) 0x40020c00))
256 #define stm_gpioc (*((struct stm_gpio *) 0x40020800))
257 #define stm_gpiob (*((struct stm_gpio *) 0x40020400))
258 #define stm_gpioa (*((struct stm_gpio *) 0x40020000))
261 vuint32_t sr; /* status register */
262 vuint32_t dr; /* data register */
263 vuint32_t brr; /* baud rate register */
264 vuint32_t cr1; /* control register 1 */
266 vuint32_t cr2; /* control register 2 */
267 vuint32_t cr3; /* control register 3 */
268 vuint32_t gtpr; /* guard time and prescaler */
271 extern struct stm_usart stm_usart1;
272 extern struct stm_usart stm_usart2;
273 extern struct stm_usart stm_usart3;
275 #define STM_USART_SR_CTS (9) /* CTS flag */
276 #define STM_USART_SR_LBD (8) /* LIN break detection flag */
277 #define STM_USART_SR_TXE (7) /* Transmit data register empty */
278 #define STM_USART_SR_TC (6) /* Transmission complete */
279 #define STM_USART_SR_RXNE (5) /* Read data register not empty */
280 #define STM_USART_SR_IDLE (4) /* IDLE line detected */
281 #define STM_USART_SR_ORE (3) /* Overrun error */
282 #define STM_USART_SR_NF (2) /* Noise detected flag */
283 #define STM_USART_SR_FE (1) /* Framing error */
284 #define STM_USART_SR_PE (0) /* Parity error */
286 #define STM_USART_CR1_OVER8 (15) /* Oversampling mode */
287 #define STM_USART_CR1_UE (13) /* USART enable */
288 #define STM_USART_CR1_M (12) /* Word length */
289 #define STM_USART_CR1_WAKE (11) /* Wakeup method */
290 #define STM_USART_CR1_PCE (10) /* Parity control enable */
291 #define STM_USART_CR1_PS (9) /* Parity selection */
292 #define STM_USART_CR1_PEIE (8) /* PE interrupt enable */
293 #define STM_USART_CR1_TXEIE (7) /* TXE interrupt enable */
294 #define STM_USART_CR1_TCIE (6) /* Transmission complete interrupt enable */
295 #define STM_USART_CR1_RXNEIE (5) /* RXNE interrupt enable */
296 #define STM_USART_CR1_IDLEIE (4) /* IDLE interrupt enable */
297 #define STM_USART_CR1_TE (3) /* Transmitter enable */
298 #define STM_USART_CR1_RE (2) /* Receiver enable */
299 #define STM_USART_CR1_RWU (1) /* Receiver wakeup */
300 #define STM_USART_CR1_SBK (0) /* Send break */
302 #define STM_USART_CR2_LINEN (14) /* LIN mode enable */
303 #define STM_USART_CR2_STOP (12) /* STOP bits */
304 #define STM_USART_CR2_STOP_MASK 3UL
305 #define STM_USART_CR2_STOP_1 0
306 #define STM_USART_CR2_STOP_0_5 1
307 #define STM_USART_CR2_STOP_2 2
308 #define STM_USART_CR2_STOP_1_5 3
310 #define STM_USART_CR2_CLKEN (11) /* Clock enable */
311 #define STM_USART_CR2_CPOL (10) /* Clock polarity */
312 #define STM_USART_CR2_CPHA (9) /* Clock phase */
313 #define STM_USART_CR2_LBCL (8) /* Last bit clock pulse */
314 #define STM_USART_CR2_LBDIE (6) /* LIN break detection interrupt enable */
315 #define STM_USART_CR2_LBDL (5) /* lin break detection length */
316 #define STM_USART_CR2_ADD (0)
317 #define STM_USART_CR2_ADD_MASK 0xfUL
319 #define STM_USART_CR3_ONEBITE (11) /* One sample bit method enable */
320 #define STM_USART_CR3_CTSIE (10) /* CTS interrupt enable */
321 #define STM_USART_CR3_CTSE (9) /* CTS enable */
322 #define STM_USART_CR3_RTSE (8) /* RTS enable */
323 #define STM_USART_CR3_DMAT (7) /* DMA enable transmitter */
324 #define STM_USART_CR3_DMAR (6) /* DMA enable receiver */
325 #define STM_USART_CR3_SCEN (5) /* Smartcard mode enable */
326 #define STM_USART_CR3_NACK (4) /* Smartcard NACK enable */
327 #define STM_USART_CR3_HDSEL (3) /* Half-duplex selection */
328 #define STM_USART_CR3_IRLP (2) /* IrDA low-power */
329 #define STM_USART_CR3_IREN (1) /* IrDA mode enable */
330 #define STM_USART_CR3_EIE (0) /* Error interrupt enable */
335 extern struct stm_tim stm_tim9;
361 extern struct stm_tim1011 stm_tim10;
362 extern struct stm_tim1011 stm_tim11;
364 #define STM_TIM1011_CR1_CKD 8
365 #define STM_TIM1011_CR1_CKD_1 0
366 #define STM_TIM1011_CR1_CKD_2 1
367 #define STM_TIM1011_CR1_CKD_4 2
368 #define STM_TIM1011_CR1_CKD_MASK 3UL
369 #define STM_TIM1011_CR1_ARPE 7
370 #define STM_TIM1011_CR1_URS 2
371 #define STM_TIM1011_CR1_UDIS 1
372 #define STM_TIM1011_CR1_CEN 0
374 #define STM_TIM1011_SMCR_ETP 15
375 #define STM_TIM1011_SMCR_ECE 14
376 #define STM_TIM1011_SMCR_ETPS 12
377 #define STM_TIM1011_SMCR_ETPS_OFF 0
378 #define STM_TIM1011_SMCR_ETPS_2 1
379 #define STM_TIM1011_SMCR_ETPS_4 2
380 #define STM_TIM1011_SMCR_ETPS_8 3
381 #define STM_TIM1011_SMCR_ETPS_MASK 3UL
382 #define STM_TIM1011_SMCR_ETF 8
383 #define STM_TIM1011_SMCR_ETF_NONE 0
384 #define STM_TIM1011_SMCR_ETF_CK_INT_2 1
385 #define STM_TIM1011_SMCR_ETF_CK_INT_4 2
386 #define STM_TIM1011_SMCR_ETF_CK_INT_8 3
387 #define STM_TIM1011_SMCR_ETF_DTS_2_6 4
388 #define STM_TIM1011_SMCR_ETF_DTS_2_8 5
389 #define STM_TIM1011_SMCR_ETF_DTS_4_6 6
390 #define STM_TIM1011_SMCR_ETF_DTS_4_8 7
391 #define STM_TIM1011_SMCR_ETF_DTS_8_6 8
392 #define STM_TIM1011_SMCR_ETF_DTS_8_8 9
393 #define STM_TIM1011_SMCR_ETF_DTS_16_5 10
394 #define STM_TIM1011_SMCR_ETF_DTS_16_6 11
395 #define STM_TIM1011_SMCR_ETF_DTS_16_8 12
396 #define STM_TIM1011_SMCR_ETF_DTS_32_5 13
397 #define STM_TIM1011_SMCR_ETF_DTS_32_6 14
398 #define STM_TIM1011_SMCR_ETF_DTS_32_8 15
399 #define STM_TIM1011_SMCR_ETF_MASK 15UL
401 #define STM_TIM1011_DIER_CC1E 1
402 #define STM_TIM1011_DIER_UIE 0
404 #define STM_TIM1011_SR_CC1OF 9
405 #define STM_TIM1011_SR_CC1IF 1
406 #define STM_TIM1011_SR_UIF 0
408 #define STM_TIM1011_EGR_CC1G 1
409 #define STM_TIM1011_EGR_UG 0
411 #define STM_TIM1011_CCMR1_OC1CE 7
412 #define STM_TIM1011_CCMR1_OC1M 4
413 #define STM_TIM1011_CCMR1_OC1M_FROZEN 0
414 #define STM_TIM1011_CCMR1_OC1M_SET_1_ACTIVE_ON_MATCH 1
415 #define STM_TIM1011_CCMR1_OC1M_SET_1_INACTIVE_ON_MATCH 2
416 #define STM_TIM1011_CCMR1_OC1M_TOGGLE 3
417 #define STM_TIM1011_CCMR1_OC1M_FORCE_INACTIVE 4
418 #define STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE 5
419 #define STM_TIM1011_CCMR1_OC1M_PWM_MODE_1 6
420 #define STM_TIM1011_CCMR1_OC1M_PWM_MODE_2 7
421 #define STM_TIM1011_CCMR1_OC1M_MASK 7UL
422 #define STM_TIM1011_CCMR1_OC1PE 3
423 #define STM_TIM1011_CCMR1_OC1FE 2
424 #define STM_TIM1011_CCMR1_CC1S 0
425 #define STM_TIM1011_CCMR1_CC1S_OUTPUT 0
426 #define STM_TIM1011_CCMR1_CC1S_INPUT_TI1 1
427 #define STM_TIM1011_CCMR1_CC1S_INPUT_TI2 2
428 #define STM_TIM1011_CCMR1_CC1S_INPUT_TRC 3
429 #define STM_TIM1011_CCMR1_CC1S_MASK 3UL
431 #define STM_TIM1011_CCMR1_IC1F_NONE 0
432 #define STM_TIM1011_CCMR1_IC1F_CK_INT_2 1
433 #define STM_TIM1011_CCMR1_IC1F_CK_INT_4 2
434 #define STM_TIM1011_CCMR1_IC1F_CK_INT_8 3
435 #define STM_TIM1011_CCMR1_IC1F_DTS_2_6 4
436 #define STM_TIM1011_CCMR1_IC1F_DTS_2_8 5
437 #define STM_TIM1011_CCMR1_IC1F_DTS_4_6 6
438 #define STM_TIM1011_CCMR1_IC1F_DTS_4_8 7
439 #define STM_TIM1011_CCMR1_IC1F_DTS_8_6 8
440 #define STM_TIM1011_CCMR1_IC1F_DTS_8_8 9
441 #define STM_TIM1011_CCMR1_IC1F_DTS_16_5 10
442 #define STM_TIM1011_CCMR1_IC1F_DTS_16_6 11
443 #define STM_TIM1011_CCMR1_IC1F_DTS_16_8 12
444 #define STM_TIM1011_CCMR1_IC1F_DTS_32_5 13
445 #define STM_TIM1011_CCMR1_IC1F_DTS_32_6 14
446 #define STM_TIM1011_CCMR1_IC1F_DTS_32_8 15
447 #define STM_TIM1011_CCMR1_IC1F_MASK 15UL
448 #define STM_TIM1011_CCMR1_IC1PSC 2
449 #define STM_TIM1011_CCMR1_IC1PSC_1 0
450 #define STM_TIM1011_CCMR1_IC1PSC_2 1
451 #define STM_TIM1011_CCMR1_IC1PSC_4 2
452 #define STM_TIM1011_CCMR1_IC1PSC_8 3
453 #define STM_TIM1011_CCMR1_IC1PSC_MASK 3UL
454 #define STM_TIM1011_CCMR1_CC1S 0
456 #define STM_TIM1011_CCER_CC1NP 3
457 #define STM_TIM1011_CCER_CC1P 1
458 #define STM_TIM1011_CCER_CC1E 0
460 #define STM_TIM1011_OR_TI1_RMP_RI 3
461 #define STM_TIM1011_ETR_RMP 2
462 #define STM_TIM1011_TI1_RMP 0
463 #define STM_TIM1011_TI1_RMP_GPIO 0
464 #define STM_TIM1011_TI1_RMP_LSI 1
465 #define STM_TIM1011_TI1_RMP_LSE 2
466 #define STM_TIM1011_TI1_RMP_RTC 3
467 #define STM_TIM1011_TI1_RMP_MASK 3UL
469 /* Flash interface */
485 extern struct stm_flash stm_flash;
487 #define STM_FLASH_ACR_RUN_PD (4)
488 #define STM_FLASH_ACR_SLEEP_PD (3)
489 #define STM_FLASH_ACR_ACC64 (2)
490 #define STM_FLASH_ACR_PRFEN (1)
491 #define STM_FLASH_ACR_LATENCY (0)
493 #define STM_FLASH_PECR_OBL_LAUNCH 18
494 #define STM_FLASH_PECR_ERRIE 17
495 #define STM_FLASH_PECR_EOPIE 16
496 #define STM_FLASH_PECR_FPRG 10
497 #define STM_FLASH_PECR_ERASE 9
498 #define STM_FLASH_PECR_FTDW 8
499 #define STM_FLASH_PECR_DATA 4
500 #define STM_FLASH_PECR_PROG 3
501 #define STM_FLASH_PECR_OPTLOCK 2
502 #define STM_FLASH_PECR_PRGLOCK 1
503 #define STM_FLASH_PECR_PELOCK 0
505 #define STM_FLASH_SR_OPTVERR 11
506 #define STM_FLASH_SR_SIZERR 10
507 #define STM_FLASH_SR_PGAERR 9
508 #define STM_FLASH_SR_WRPERR 8
509 #define STM_FLASH_SR_READY 3
510 #define STM_FLASH_SR_ENDHV 2
511 #define STM_FLASH_SR_EOP 1
512 #define STM_FLASH_SR_BSY 0
514 #define STM_FLASH_PEKEYR_PEKEY1 0x89ABCDEF
515 #define STM_FLASH_PEKEYR_PEKEY2 0x02030405
517 #define STM_FLASH_PRGKEYR_PRGKEY1 0x8C9DAEBF
518 #define STM_FLASH_PRGKEYR_PRGKEY2 0x13141516
540 extern struct stm_rcc stm_rcc;
542 /* Nominal high speed internal oscillator frequency is 16MHz */
543 #define STM_HSI_FREQ 16000000
545 #define STM_RCC_CR_RTCPRE (29)
546 #define STM_RCC_CR_RTCPRE_HSE_DIV_2 0
547 #define STM_RCC_CR_RTCPRE_HSE_DIV_4 1
548 #define STM_RCC_CR_RTCPRE_HSE_DIV_8 2
549 #define STM_RCC_CR_RTCPRE_HSE_DIV_16 3
550 #define STM_RCC_CR_RTCPRE_HSE_MASK 3UL
552 #define STM_RCC_CR_CSSON (28)
553 #define STM_RCC_CR_PLLRDY (25)
554 #define STM_RCC_CR_PLLON (24)
555 #define STM_RCC_CR_HSEBYP (18)
556 #define STM_RCC_CR_HSERDY (17)
557 #define STM_RCC_CR_HSEON (16)
558 #define STM_RCC_CR_MSIRDY (9)
559 #define STM_RCC_CR_MSION (8)
560 #define STM_RCC_CR_HSIRDY (1)
561 #define STM_RCC_CR_HSION (0)
563 #define STM_RCC_CFGR_MCOPRE (28)
564 #define STM_RCC_CFGR_MCOPRE_DIV_1 0
565 #define STM_RCC_CFGR_MCOPRE_DIV_2 1
566 #define STM_RCC_CFGR_MCOPRE_DIV_4 2
567 #define STM_RCC_CFGR_MCOPRE_DIV_8 3
568 #define STM_RCC_CFGR_MCOPRE_DIV_16 4
569 #define STM_RCC_CFGR_MCOPRE_MASK 7UL
571 #define STM_RCC_CFGR_MCOSEL (24)
572 #define STM_RCC_CFGR_MCOSEL_DISABLE 0
573 #define STM_RCC_CFGR_MCOSEL_SYSCLK 1
574 #define STM_RCC_CFGR_MCOSEL_HSI 2
575 #define STM_RCC_CFGR_MCOSEL_MSI 3
576 #define STM_RCC_CFGR_MCOSEL_HSE 4
577 #define STM_RCC_CFGR_MCOSEL_PLL 5
578 #define STM_RCC_CFGR_MCOSEL_LSI 6
579 #define STM_RCC_CFGR_MCOSEL_LSE 7
580 #define STM_RCC_CFGR_MCOSEL_MASK 7UL
582 #define STM_RCC_CFGR_PLLDIV (22)
583 #define STM_RCC_CFGR_PLLDIV_2 1
584 #define STM_RCC_CFGR_PLLDIV_3 2
585 #define STM_RCC_CFGR_PLLDIV_4 3
586 #define STM_RCC_CFGR_PLLDIV_MASK 3UL
588 #define STM_RCC_CFGR_PLLMUL (18)
589 #define STM_RCC_CFGR_PLLMUL_3 0
590 #define STM_RCC_CFGR_PLLMUL_4 1
591 #define STM_RCC_CFGR_PLLMUL_6 2
592 #define STM_RCC_CFGR_PLLMUL_8 3
593 #define STM_RCC_CFGR_PLLMUL_12 4
594 #define STM_RCC_CFGR_PLLMUL_16 5
595 #define STM_RCC_CFGR_PLLMUL_24 6
596 #define STM_RCC_CFGR_PLLMUL_32 7
597 #define STM_RCC_CFGR_PLLMUL_48 8
598 #define STM_RCC_CFGR_PLLMUL_MASK 0xfUL
600 #define STM_RCC_CFGR_PLLSRC (16)
602 #define STM_RCC_CFGR_PPRE2 (11)
603 #define STM_RCC_CFGR_PPRE2_DIV_1 0
604 #define STM_RCC_CFGR_PPRE2_DIV_2 4
605 #define STM_RCC_CFGR_PPRE2_DIV_4 5
606 #define STM_RCC_CFGR_PPRE2_DIV_8 6
607 #define STM_RCC_CFGR_PPRE2_DIV_16 7
608 #define STM_RCC_CFGR_PPRE2_MASK 7UL
610 #define STM_RCC_CFGR_PPRE1 (8)
611 #define STM_RCC_CFGR_PPRE1_DIV_1 0
612 #define STM_RCC_CFGR_PPRE1_DIV_2 4
613 #define STM_RCC_CFGR_PPRE1_DIV_4 5
614 #define STM_RCC_CFGR_PPRE1_DIV_8 6
615 #define STM_RCC_CFGR_PPRE1_DIV_16 7
616 #define STM_RCC_CFGR_PPRE1_MASK 7UL
618 #define STM_RCC_CFGR_HPRE (4)
619 #define STM_RCC_CFGR_HPRE_DIV_1 0
620 #define STM_RCC_CFGR_HPRE_DIV_2 8
621 #define STM_RCC_CFGR_HPRE_DIV_4 9
622 #define STM_RCC_CFGR_HPRE_DIV_8 0xa
623 #define STM_RCC_CFGR_HPRE_DIV_16 0xb
624 #define STM_RCC_CFGR_HPRE_DIV_64 0xc
625 #define STM_RCC_CFGR_HPRE_DIV_128 0xd
626 #define STM_RCC_CFGR_HPRE_DIV_256 0xe
627 #define STM_RCC_CFGR_HPRE_DIV_512 0xf
628 #define STM_RCC_CFGR_HPRE_MASK 0xfUL
630 #define STM_RCC_CFGR_SWS (2)
631 #define STM_RCC_CFGR_SWS_MSI 0
632 #define STM_RCC_CFGR_SWS_HSI 1
633 #define STM_RCC_CFGR_SWS_HSE 2
634 #define STM_RCC_CFGR_SWS_PLL 3
635 #define STM_RCC_CFGR_SWS_MASK 3UL
637 #define STM_RCC_CFGR_SW (0)
638 #define STM_RCC_CFGR_SW_MSI 0
639 #define STM_RCC_CFGR_SW_HSI 1
640 #define STM_RCC_CFGR_SW_HSE 2
641 #define STM_RCC_CFGR_SW_PLL 3
642 #define STM_RCC_CFGR_SW_MASK 3UL
644 #define STM_RCC_AHBENR_DMA1EN (24)
645 #define STM_RCC_AHBENR_FLITFEN (15)
646 #define STM_RCC_AHBENR_CRCEN (12)
647 #define STM_RCC_AHBENR_GPIOHEN (5)
648 #define STM_RCC_AHBENR_GPIOEEN (4)
649 #define STM_RCC_AHBENR_GPIODEN (3)
650 #define STM_RCC_AHBENR_GPIOCEN (2)
651 #define STM_RCC_AHBENR_GPIOBEN (1)
652 #define STM_RCC_AHBENR_GPIOAEN (0)
654 #define STM_RCC_APB2ENR_USART1EN (14)
655 #define STM_RCC_APB2ENR_SPI1EN (12)
656 #define STM_RCC_APB2ENR_ADC1EN (9)
657 #define STM_RCC_APB2ENR_TIM11EN (4)
658 #define STM_RCC_APB2ENR_TIM10EN (3)
659 #define STM_RCC_APB2ENR_TIM9EN (2)
660 #define STM_RCC_APB2ENR_SYSCFGEN (0)
662 #define STM_RCC_APB1ENR_COMPEN (31)
663 #define STM_RCC_APB1ENR_DACEN (29)
664 #define STM_RCC_APB1ENR_PWREN (28)
665 #define STM_RCC_APB1ENR_USBEN (23)
666 #define STM_RCC_APB1ENR_I2C2EN (22)
667 #define STM_RCC_APB1ENR_I2C1EN (21)
668 #define STM_RCC_APB1ENR_USART3EN (18)
669 #define STM_RCC_APB1ENR_USART2EN (17)
670 #define STM_RCC_APB1ENR_SPI2EN (14)
671 #define STM_RCC_APB1ENR_WWDGEN (11)
672 #define STM_RCC_APB1ENR_LCDEN (9)
673 #define STM_RCC_APB1ENR_TIM7EN (5)
674 #define STM_RCC_APB1ENR_TIM6EN (4)
675 #define STM_RCC_APB1ENR_TIM4EN (2)
676 #define STM_RCC_APB1ENR_TIM3EN (1)
677 #define STM_RCC_APB1ENR_TIM2EN (0)
679 #define STM_RCC_CSR_LPWRRSTF (31)
680 #define STM_RCC_CSR_WWDGRSTF (30)
681 #define STM_RCC_CSR_IWDGRSTF (29)
682 #define STM_RCC_CSR_SFTRSTF (28)
683 #define STM_RCC_CSR_PORRSTF (27)
684 #define STM_RCC_CSR_PINRSTF (26)
685 #define STM_RCC_CSR_OBLRSTF (25)
686 #define STM_RCC_CSR_RMVF (24)
687 #define STM_RCC_CSR_RTFRST (23)
688 #define STM_RCC_CSR_RTCEN (22)
689 #define STM_RCC_CSR_RTCSEL (16)
691 #define STM_RCC_CSR_RTCSEL_NONE 0
692 #define STM_RCC_CSR_RTCSEL_LSE 1
693 #define STM_RCC_CSR_RTCSEL_LSI 2
694 #define STM_RCC_CSR_RTCSEL_HSE 3
695 #define STM_RCC_CSR_RTCSEL_MASK 3UL
697 #define STM_RCC_CSR_LSEBYP (10)
698 #define STM_RCC_CSR_LSERDY (9)
699 #define STM_RCC_CSR_LSEON (8)
700 #define STM_RCC_CSR_LSIRDY (1)
701 #define STM_RCC_CSR_LSION (0)
708 extern struct stm_pwr stm_pwr;
710 #define STM_PWR_CR_LPRUN (14)
712 #define STM_PWR_CR_VOS (11)
713 #define STM_PWR_CR_VOS_1_8 1UL
714 #define STM_PWR_CR_VOS_1_5 2UL
715 #define STM_PWR_CR_VOS_1_2 3UL
716 #define STM_PWR_CR_VOS_MASK 3UL
718 #define STM_PWR_CR_FWU (10)
719 #define STM_PWR_CR_ULP (9)
720 #define STM_PWR_CR_DBP (8)
722 #define STM_PWR_CR_PLS (5)
723 #define STM_PWR_CR_PLS_1_9 0
724 #define STM_PWR_CR_PLS_2_1 1
725 #define STM_PWR_CR_PLS_2_3 2
726 #define STM_PWR_CR_PLS_2_5 3
727 #define STM_PWR_CR_PLS_2_7 4
728 #define STM_PWR_CR_PLS_2_9 5
729 #define STM_PWR_CR_PLS_3_1 6
730 #define STM_PWR_CR_PLS_EXT 7
731 #define STM_PWR_CR_PLS_MASK 7UL
733 #define STM_PWR_CR_PVDE (4)
734 #define STM_PWR_CR_CSBF (3)
735 #define STM_PWR_CR_CWUF (2)
736 #define STM_PWR_CR_PDDS (1)
737 #define STM_PWR_CR_LPSDSR (0)
739 #define STM_PWR_CSR_EWUP3 (10)
740 #define STM_PWR_CSR_EWUP2 (9)
741 #define STM_PWR_CSR_EWUP1 (8)
742 #define STM_PWR_CSR_REGLPF (5)
743 #define STM_PWR_CSR_VOSF (4)
744 #define STM_PWR_CSR_VREFINTRDYF (3)
745 #define STM_PWR_CSR_PVDO (2)
746 #define STM_PWR_CSR_SBF (1)
747 #define STM_PWR_CSR_WUF (0)
766 extern struct stm_tim67 stm_tim6;
768 #define STM_TIM67_CR1_ARPE (7)
769 #define STM_TIM67_CR1_OPM (3)
770 #define STM_TIM67_CR1_URS (2)
771 #define STM_TIM67_CR1_UDIS (1)
772 #define STM_TIM67_CR1_CEN (0)
774 #define STM_TIM67_CR2_MMS (4)
775 #define STM_TIM67_CR2_MMS_RESET 0
776 #define STM_TIM67_CR2_MMS_ENABLE 1
777 #define STM_TIM67_CR2_MMS_UPDATE 2
778 #define STM_TIM67_CR2_MMS_MASK 7UL
780 #define STM_TIM67_DIER_UDE (8)
781 #define STM_TIM67_DIER_UIE (0)
783 #define STM_TIM67_SR_UIF (0)
785 #define STM_TIM67_EGR_UG (0)
792 uint32_t unused_0x10;
796 extern struct stm_lcd stm_lcd;
798 #define STM_LCD_CR_MUX_SEG (7)
800 #define STM_LCD_CR_BIAS (5)
801 #define STM_LCD_CR_BIAS_1_4 0
802 #define STM_LCD_CR_BIAS_1_2 1
803 #define STM_LCD_CR_BIAS_1_3 2
804 #define STM_LCD_CR_BIAS_MASK 3UL
806 #define STM_LCD_CR_DUTY (2)
807 #define STM_LCD_CR_DUTY_STATIC 0
808 #define STM_LCD_CR_DUTY_1_2 1
809 #define STM_LCD_CR_DUTY_1_3 2
810 #define STM_LCD_CR_DUTY_1_4 3
811 #define STM_LCD_CR_DUTY_1_8 4
812 #define STM_LCD_CR_DUTY_MASK 7UL
814 #define STM_LCD_CR_VSEL (1)
815 #define STM_LCD_CR_LCDEN (0)
817 #define STM_LCD_FCR_PS (22)
818 #define STM_LCD_FCR_PS_1 0x0
819 #define STM_LCD_FCR_PS_2 0x1
820 #define STM_LCD_FCR_PS_4 0x2
821 #define STM_LCD_FCR_PS_8 0x3
822 #define STM_LCD_FCR_PS_16 0x4
823 #define STM_LCD_FCR_PS_32 0x5
824 #define STM_LCD_FCR_PS_64 0x6
825 #define STM_LCD_FCR_PS_128 0x7
826 #define STM_LCD_FCR_PS_256 0x8
827 #define STM_LCD_FCR_PS_512 0x9
828 #define STM_LCD_FCR_PS_1024 0xa
829 #define STM_LCD_FCR_PS_2048 0xb
830 #define STM_LCD_FCR_PS_4096 0xc
831 #define STM_LCD_FCR_PS_8192 0xd
832 #define STM_LCD_FCR_PS_16384 0xe
833 #define STM_LCD_FCR_PS_32768 0xf
834 #define STM_LCD_FCR_PS_MASK 0xfUL
836 #define STM_LCD_FCR_DIV (18)
837 #define STM_LCD_FCR_DIV_16 0x0
838 #define STM_LCD_FCR_DIV_17 0x1
839 #define STM_LCD_FCR_DIV_18 0x2
840 #define STM_LCD_FCR_DIV_19 0x3
841 #define STM_LCD_FCR_DIV_20 0x4
842 #define STM_LCD_FCR_DIV_21 0x5
843 #define STM_LCD_FCR_DIV_22 0x6
844 #define STM_LCD_FCR_DIV_23 0x7
845 #define STM_LCD_FCR_DIV_24 0x8
846 #define STM_LCD_FCR_DIV_25 0x9
847 #define STM_LCD_FCR_DIV_26 0xa
848 #define STM_LCD_FCR_DIV_27 0xb
849 #define STM_LCD_FCR_DIV_28 0xc
850 #define STM_LCD_FCR_DIV_29 0xd
851 #define STM_LCD_FCR_DIV_30 0xe
852 #define STM_LCD_FCR_DIV_31 0xf
853 #define STM_LCD_FCR_DIV_MASK 0xfUL
855 #define STM_LCD_FCR_BLINK (16)
856 #define STM_LCD_FCR_BLINK_DISABLE 0
857 #define STM_LCD_FCR_BLINK_SEG0_COM0 1
858 #define STM_LCD_FCR_BLINK_SEG0_COMALL 2
859 #define STM_LCD_FCR_BLINK_SEGALL_COMALL 3
860 #define STM_LCD_FCR_BLINK_MASK 3UL
862 #define STM_LCD_FCR_BLINKF (13)
863 #define STM_LCD_FCR_BLINKF_8 0
864 #define STM_LCD_FCR_BLINKF_16 1
865 #define STM_LCD_FCR_BLINKF_32 2
866 #define STM_LCD_FCR_BLINKF_64 3
867 #define STM_LCD_FCR_BLINKF_128 4
868 #define STM_LCD_FCR_BLINKF_256 5
869 #define STM_LCD_FCR_BLINKF_512 6
870 #define STM_LCD_FCR_BLINKF_1024 7
871 #define STM_LCD_FCR_BLINKF_MASK 7UL
873 #define STM_LCD_FCR_CC (10)
874 #define STM_LCD_FCR_CC_MASK 7UL
876 #define STM_LCD_FCR_DEAD (7)
877 #define STM_LCD_FCR_DEAD_MASK 7UL
879 #define STM_LCD_FCR_PON (4)
880 #define STM_LCD_FCR_PON_MASK 7UL
882 #define STM_LCD_FCR_UDDIE (3)
883 #define STM_LCD_FCR_SOFIE (1)
884 #define STM_LCD_FCR_HD (0)
886 #define STM_LCD_SR_FCRSF (5)
887 #define STM_LCD_SR_RDY (4)
888 #define STM_LCD_SR_UDD (3)
889 #define STM_LCD_SR_UDR (2)
890 #define STM_LCD_SR_SOF (1)
891 #define STM_LCD_SR_ENS (0)
893 #define STM_LCD_CLR_UDDC (3)
894 #define STM_LCD_CLR_SOFC (1)
896 /* The SYSTICK starts at 0xe000e010 */
905 extern struct stm_systick stm_systick;
907 #define STM_SYSTICK_CSR_ENABLE 0
908 #define STM_SYSTICK_CSR_TICKINT 1
909 #define STM_SYSTICK_CSR_CLKSOURCE 2
910 #define STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 0
911 #define STM_SYSTICK_CSR_CLKSOURCE_HCLK 1
912 #define STM_SYSTICK_CSR_COUNTFLAG 16
914 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
917 vuint32_t iser[8]; /* 0x000 0xe000e100 Set Enable Register */
919 uint8_t _unused020[0x080 - 0x020];
921 vuint32_t icer[8]; /* 0x080 0xe000e180 Clear Enable Register */
923 uint8_t _unused0a0[0x100 - 0x0a0];
925 vuint32_t ispr[8]; /* 0x100 0xe000e200 Set Pending Register */
927 uint8_t _unused120[0x180 - 0x120];
929 vuint32_t icpr[8]; /* 0x180 0xe000e280 Clear Pending Register */
931 uint8_t _unused1a0[0x200 - 0x1a0];
933 vuint32_t iabr[8]; /* 0x200 0xe000e300 Active Bit Register */
935 uint8_t _unused220[0x300 - 0x220];
937 vuint32_t ipr[60]; /* 0x300 0xe000e400 Priority Register */
939 uint8_t _unused3f0[0xc00 - 0x3f0];
941 vuint32_t cpuid_base; /* 0xc00 0xe000ed00 CPUID Base Register */
942 vuint32_t ics; /* 0xc04 0xe000ed04 Interrupt Control State Register */
943 vuint32_t vto; /* 0xc08 0xe000ed08 Vector Table Offset Register */
944 vuint32_t ai_rc; /* 0xc0c 0xe000ed0c Application Interrupt/Reset Control Register */
945 vuint32_t sc; /* 0xc10 0xe000ed10 System Control Register */
946 vuint32_t cc; /* 0xc14 0xe000ed14 Configuration Control Register */
948 vuint32_t shpr7_4; /* 0xc18 0xe000ed18 System Hander Priority Registers */
949 vuint32_t shpr11_8; /* 0xc1c */
950 vuint32_t shpr15_12; /* 0xc20 */
952 uint8_t _unusedc18[0xe00 - 0xc24];
954 vuint32_t stir; /* 0xe00 */
957 extern struct stm_nvic stm_nvic;
959 #define IRQ_REG(irq) ((irq) >> 5)
960 #define IRQ_BIT(irq) ((irq) & 0x1f)
961 #define IRQ_MASK(irq) (1 << IRQ_BIT(irq))
962 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
965 stm_nvic_set_enable(int irq) {
966 stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
970 stm_nvic_clear_enable(int irq) {
971 stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
975 stm_nvic_enabled(int irq) {
976 return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
980 stm_nvic_set_pending(int irq) {
981 stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
985 stm_nvic_clear_pending(int irq) {
986 stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
990 stm_nvic_pending(int irq) {
991 return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
995 stm_nvic_active(int irq) {
996 return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
999 #define IRQ_PRIO_REG(irq) ((irq) >> 2)
1000 #define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3)
1001 #define IRQ_PRIO_MASK(irq) (0xff << IRQ_PRIO_BIT(irq))
1004 stm_nvic_set_priority(int irq, uint8_t prio) {
1005 int n = IRQ_PRIO_REG(irq);
1008 v = stm_nvic.ipr[n];
1009 v &= (uint32_t) ~IRQ_PRIO_MASK(irq);
1010 v |= (prio) << IRQ_PRIO_BIT(irq);
1011 stm_nvic.ipr[n] = v;
1014 static inline uint8_t
1015 stm_nvic_get_priority(int irq) {
1016 return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
1040 extern struct stm_scb stm_scb;
1042 #define STM_SCB_AIRCR_VECTKEY 16
1043 #define STM_SCB_AIRCR_VECTKEY_KEY 0x05fa
1044 #define STM_SCB_AIRCR_PRIGROUP 8
1045 #define STM_SCB_AIRCR_SYSRESETREQ 2
1046 #define STM_SCB_AIRCR_VECTCLRACTIVE 1
1047 #define STM_SCB_AIRCR_VECTRESET 0
1064 extern struct stm_mpu stm_mpu;
1066 #define STM_MPU_TYPER_IREGION 16
1067 #define STM_MPU_TYPER_IREGION_MASK 0xffUL
1068 #define STM_MPU_TYPER_DREGION 8
1069 #define STM_MPU_TYPER_DREGION_MASK 0xffUL
1070 #define STM_MPU_TYPER_SEPARATE 0
1072 #define STM_MPU_CR_PRIVDEFENA 2
1073 #define STM_MPU_CR_HFNMIENA 1
1074 #define STM_MPU_CR_ENABLE 0
1076 #define STM_MPU_RNR_REGION 0
1077 #define STM_MPU_RNR_REGION_MASK 0xffUL
1079 #define STM_MPU_RBAR_ADDR 5
1080 #define STM_MPU_RBAR_ADDR_MASK 0x7ffffffUL
1082 #define STM_MPU_RBAR_VALID 4
1083 #define STM_MPU_RBAR_REGION 0
1084 #define STM_MPU_RBAR_REGION_MASK 0xfUL
1086 #define STM_MPU_RASR_XN 28
1087 #define STM_MPU_RASR_AP 24
1088 #define STM_MPU_RASR_AP_NONE_NONE 0
1089 #define STM_MPU_RASR_AP_RW_NONE 1
1090 #define STM_MPU_RASR_AP_RW_RO 2
1091 #define STM_MPU_RASR_AP_RW_RW 3
1092 #define STM_MPU_RASR_AP_RO_NONE 5
1093 #define STM_MPU_RASR_AP_RO_RO 6
1094 #define STM_MPU_RASR_AP_MASK 7UL
1095 #define STM_MPU_RASR_TEX 19
1096 #define STM_MPU_RASR_TEX_MASK 7UL
1097 #define STM_MPU_RASR_S 18
1098 #define STM_MPU_RASR_C 17
1099 #define STM_MPU_RASR_B 16
1100 #define STM_MPU_RASR_SRD 8
1101 #define STM_MPU_RASR_SRD_MASK 0xffUL
1102 #define STM_MPU_RASR_SIZE 1
1103 #define STM_MPU_RASR_SIZE_MASK 0x1fUL
1104 #define STM_MPU_RASR_ENABLE 0
1106 #define isr_decl(name) void stm_ ## name ## _isr(void)
1112 isr_decl(hardfault);
1113 isr_decl(memmanage);
1115 isr_decl(usagefault);
1122 isr_decl(tamper_stamp);
1131 isr_decl(dma1_channel1);
1132 isr_decl(dma1_channel2);
1133 isr_decl(dma1_channel3);
1134 isr_decl(dma1_channel4);
1135 isr_decl(dma1_channel5);
1136 isr_decl(dma1_channel6);
1137 isr_decl(dma1_channel7);
1160 isr_decl(exti15_10);
1161 isr_decl(rtc_alarm);
1162 isr_decl(usb_fs_wkup);
1168 #define STM_ISR_WWDG_POS 0
1169 #define STM_ISR_PVD_POS 1
1170 #define STM_ISR_TAMPER_STAMP_POS 2
1171 #define STM_ISR_RTC_WKUP_POS 3
1172 #define STM_ISR_FLASH_POS 4
1173 #define STM_ISR_RCC_POS 5
1174 #define STM_ISR_EXTI0_POS 6
1175 #define STM_ISR_EXTI1_POS 7
1176 #define STM_ISR_EXTI2_POS 8
1177 #define STM_ISR_EXTI3_POS 9
1178 #define STM_ISR_EXTI4_POS 10
1179 #define STM_ISR_DMA1_CHANNEL1_POS 11
1180 #define STM_ISR_DMA2_CHANNEL1_POS 12
1181 #define STM_ISR_DMA3_CHANNEL1_POS 13
1182 #define STM_ISR_DMA4_CHANNEL1_POS 14
1183 #define STM_ISR_DMA5_CHANNEL1_POS 15
1184 #define STM_ISR_DMA6_CHANNEL1_POS 16
1185 #define STM_ISR_DMA7_CHANNEL1_POS 17
1186 #define STM_ISR_ADC1_POS 18
1187 #define STM_ISR_USB_HP_POS 19
1188 #define STM_ISR_USB_LP_POS 20
1189 #define STM_ISR_DAC_POS 21
1190 #define STM_ISR_COMP_POS 22
1191 #define STM_ISR_EXTI9_5_POS 23
1192 #define STM_ISR_LCD_POS 24
1193 #define STM_ISR_TIM9_POS 25
1194 #define STM_ISR_TIM10_POS 26
1195 #define STM_ISR_TIM11_POS 27
1196 #define STM_ISR_TIM2_POS 28
1197 #define STM_ISR_TIM3_POS 29
1198 #define STM_ISR_TIM4_POS 30
1199 #define STM_ISR_I2C1_EV_POS 31
1200 #define STM_ISR_I2C1_ER_POS 32
1201 #define STM_ISR_I2C2_EV_POS 33
1202 #define STM_ISR_I2C2_ER_POS 34
1203 #define STM_ISR_SPI1_POS 35
1204 #define STM_ISR_SPI2_POS 36
1205 #define STM_ISR_USART1_POS 37
1206 #define STM_ISR_USART2_POS 38
1207 #define STM_ISR_USART3_POS 39
1208 #define STM_ISR_EXTI15_10_POS 40
1209 #define STM_ISR_RTC_ALARM_POS 41
1210 #define STM_ISR_USB_FS_WKUP_POS 42
1211 #define STM_ISR_TIM6_POS 43
1212 #define STM_ISR_TIM7_POS 44
1217 vuint32_t exticr[4];
1220 extern struct stm_syscfg stm_syscfg;
1222 #define STM_SYSCFG_MEMRMP_MEM_MODE 0
1223 #define STM_SYSCFG_MEMRMP_MEM_MODE_MAIN_FLASH 0
1224 #define STM_SYSCFG_MEMRMP_MEM_MODE_SYSTEM_FLASH 1
1225 #define STM_SYSCFG_MEMRMP_MEM_MODE_SRAM 3
1226 #define STM_SYSCFG_MEMRMP_MEM_MODE_MASK 3UL
1228 #define STM_SYSCFG_PMC_USB_PU 0
1230 #define STM_SYSCFG_EXTICR_PA 0
1231 #define STM_SYSCFG_EXTICR_PB 1
1232 #define STM_SYSCFG_EXTICR_PC 2
1233 #define STM_SYSCFG_EXTICR_PD 3
1234 #define STM_SYSCFG_EXTICR_PE 4
1235 #define STM_SYSCFG_EXTICR_PH 5
1238 stm_exticr_set(struct stm_gpio *gpio, int pin) {
1239 uint8_t reg = (uint8_t) (pin >> 2);
1240 uint8_t shift = (pin & 3) << 2;
1244 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN);
1246 if (gpio == &stm_gpioa)
1247 val = STM_SYSCFG_EXTICR_PA;
1248 else if (gpio == &stm_gpiob)
1249 val = STM_SYSCFG_EXTICR_PB;
1250 else if (gpio == &stm_gpioc)
1251 val = STM_SYSCFG_EXTICR_PC;
1252 else if (gpio == &stm_gpiod)
1253 val = STM_SYSCFG_EXTICR_PD;
1254 else if (gpio == &stm_gpioe)
1255 val = STM_SYSCFG_EXTICR_PE;
1257 stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & (uint32_t) ~(0xf << shift)) | val << shift;
1261 struct stm_dma_channel {
1269 #define STM_NUM_DMA 7
1274 struct stm_dma_channel channel[STM_NUM_DMA];
1277 extern struct stm_dma stm_dma;
1279 /* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
1282 #define STM_DMA_INDEX(channel) ((channel) - 1)
1284 #define STM_DMA_ISR(index) ((index) << 2)
1285 #define STM_DMA_ISR_MASK 0xfUL
1286 #define STM_DMA_ISR_TEIF 3
1287 #define STM_DMA_ISR_HTIF 2
1288 #define STM_DMA_ISR_TCIF 1
1289 #define STM_DMA_ISR_GIF 0
1291 #define STM_DMA_IFCR(index) ((index) << 2)
1292 #define STM_DMA_IFCR_MASK 0xfUL
1293 #define STM_DMA_IFCR_CTEIF 3
1294 #define STM_DMA_IFCR_CHTIF 2
1295 #define STM_DMA_IFCR_CTCIF 1
1296 #define STM_DMA_IFCR_CGIF 0
1298 #define STM_DMA_CCR_MEM2MEM (14)
1300 #define STM_DMA_CCR_PL (12)
1301 #define STM_DMA_CCR_PL_LOW (0)
1302 #define STM_DMA_CCR_PL_MEDIUM (1)
1303 #define STM_DMA_CCR_PL_HIGH (2)
1304 #define STM_DMA_CCR_PL_VERY_HIGH (3)
1305 #define STM_DMA_CCR_PL_MASK (3)
1307 #define STM_DMA_CCR_MSIZE (10)
1308 #define STM_DMA_CCR_MSIZE_8 (0)
1309 #define STM_DMA_CCR_MSIZE_16 (1)
1310 #define STM_DMA_CCR_MSIZE_32 (2)
1311 #define STM_DMA_CCR_MSIZE_MASK (3)
1313 #define STM_DMA_CCR_PSIZE (8)
1314 #define STM_DMA_CCR_PSIZE_8 (0)
1315 #define STM_DMA_CCR_PSIZE_16 (1)
1316 #define STM_DMA_CCR_PSIZE_32 (2)
1317 #define STM_DMA_CCR_PSIZE_MASK (3)
1319 #define STM_DMA_CCR_MINC (7)
1320 #define STM_DMA_CCR_PINC (6)
1321 #define STM_DMA_CCR_CIRC (5)
1322 #define STM_DMA_CCR_DIR (4)
1323 #define STM_DMA_CCR_DIR_PER_TO_MEM 0
1324 #define STM_DMA_CCR_DIR_MEM_TO_PER 1
1325 #define STM_DMA_CCR_TEIE (3)
1326 #define STM_DMA_CCR_HTIE (2)
1327 #define STM_DMA_CCR_TCIE (1)
1328 #define STM_DMA_CCR_EN (0)
1330 #define STM_DMA_CHANNEL_ADC1 1
1331 #define STM_DMA_CHANNEL_SPI1_RX 2
1332 #define STM_DMA_CHANNEL_SPI1_TX 3
1333 #define STM_DMA_CHANNEL_SPI2_RX 4
1334 #define STM_DMA_CHANNEL_SPI2_TX 5
1335 #define STM_DMA_CHANNEL_USART3_TX 2
1336 #define STM_DMA_CHANNEL_USART3_RX 3
1337 #define STM_DMA_CHANNEL_USART1_TX 4
1338 #define STM_DMA_CHANNEL_USART1_RX 5
1339 #define STM_DMA_CHANNEL_USART2_RX 6
1340 #define STM_DMA_CHANNEL_USART2_TX 7
1341 #define STM_DMA_CHANNEL_I2C2_TX 4
1342 #define STM_DMA_CHANNEL_I2C2_RX 5
1343 #define STM_DMA_CHANNEL_I2C1_TX 6
1344 #define STM_DMA_CHANNEL_I2C1_RX 7
1345 #define STM_DMA_CHANNEL_TIM2_CH3 1
1346 #define STM_DMA_CHANNEL_TIM2_UP 2
1347 #define STM_DMA_CHANNEL_TIM2_CH1 5
1348 #define STM_DMA_CHANNEL_TIM2_CH2 7
1349 #define STM_DMA_CHANNEL_TIM2_CH4 7
1350 #define STM_DMA_CHANNEL_TIM3_CH3 2
1351 #define STM_DMA_CHANNEL_TIM3_CH4 3
1352 #define STM_DMA_CHANNEL_TIM3_UP 3
1353 #define STM_DMA_CHANNEL_TIM3_CH1 6
1354 #define STM_DMA_CHANNEL_TIM3_TRIG 6
1355 #define STM_DMA_CHANNEL_TIM4_CH1 1
1356 #define STM_DMA_CHANNEL_TIM4_CH2 4
1357 #define STM_DMA_CHANNEL_TIM4_CH3 5
1358 #define STM_DMA_CHANNEL_TIM4_UP 7
1359 #define STM_DMA_CHANNEL_TIM6_UP_DA 2
1360 #define STM_DMA_CHANNEL_C_CHANNEL1 2
1361 #define STM_DMA_CHANNEL_TIM7_UP_DA 3
1362 #define STM_DMA_CHANNEL_C_CHANNEL2 3
1365 * Only spi channel 1 and 2 can use DMA
1367 #define STM_NUM_SPI 2
1379 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
1381 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1384 #define STM_SPI_INDEX(channel) ((channel) - 1)
1386 #define STM_SPI_CR1_BIDIMODE 15
1387 #define STM_SPI_CR1_BIDIOE 14
1388 #define STM_SPI_CR1_CRCEN 13
1389 #define STM_SPI_CR1_CRCNEXT 12
1390 #define STM_SPI_CR1_DFF 11
1391 #define STM_SPI_CR1_RXONLY 10
1392 #define STM_SPI_CR1_SSM 9
1393 #define STM_SPI_CR1_SSI 8
1394 #define STM_SPI_CR1_LSBFIRST 7
1395 #define STM_SPI_CR1_SPE 6
1396 #define STM_SPI_CR1_BR 3
1397 #define STM_SPI_CR1_BR_PCLK_2 0
1398 #define STM_SPI_CR1_BR_PCLK_4 1
1399 #define STM_SPI_CR1_BR_PCLK_8 2
1400 #define STM_SPI_CR1_BR_PCLK_16 3
1401 #define STM_SPI_CR1_BR_PCLK_32 4
1402 #define STM_SPI_CR1_BR_PCLK_64 5
1403 #define STM_SPI_CR1_BR_PCLK_128 6
1404 #define STM_SPI_CR1_BR_PCLK_256 7
1405 #define STM_SPI_CR1_BR_MASK 7UL
1407 #define STM_SPI_CR1_MSTR 2
1408 #define STM_SPI_CR1_CPOL 1
1409 #define STM_SPI_CR1_CPHA 0
1411 #define STM_SPI_CR2_TXEIE 7
1412 #define STM_SPI_CR2_RXNEIE 6
1413 #define STM_SPI_CR2_ERRIE 5
1414 #define STM_SPI_CR2_SSOE 2
1415 #define STM_SPI_CR2_TXDMAEN 1
1416 #define STM_SPI_CR2_RXDMAEN 0
1418 #define STM_SPI_SR_FRE 8
1419 #define STM_SPI_SR_BSY 7
1420 #define STM_SPI_SR_OVR 6
1421 #define STM_SPI_SR_MODF 5
1422 #define STM_SPI_SR_CRCERR 4
1423 #define STM_SPI_SR_UDR 3
1424 #define STM_SPI_SR_CHSIDE 2
1425 #define STM_SPI_SR_TXE 1
1426 #define STM_SPI_SR_RXNE 0
1452 uint8_t reserved[0x300 - 0x5c];
1457 extern struct stm_adc stm_adc;
1459 #define STM_ADC_SQ_TEMP 16
1460 #define STM_ADC_SQ_V_REF 17
1462 #define STM_ADC_SR_JCNR 9
1463 #define STM_ADC_SR_RCNR 8
1464 #define STM_ADC_SR_ADONS 6
1465 #define STM_ADC_SR_OVR 5
1466 #define STM_ADC_SR_STRT 4
1467 #define STM_ADC_SR_JSTRT 3
1468 #define STM_ADC_SR_JEOC 2
1469 #define STM_ADC_SR_EOC 1
1470 #define STM_ADC_SR_AWD 0
1472 #define STM_ADC_CR1_OVRIE 26
1473 #define STM_ADC_CR1_RES 24
1474 #define STM_ADC_CR1_RES_12 0
1475 #define STM_ADC_CR1_RES_10 1
1476 #define STM_ADC_CR1_RES_8 2
1477 #define STM_ADC_CR1_RES_6 3
1478 #define STM_ADC_CR1_RES_MASK 3UL
1479 #define STM_ADC_CR1_AWDEN 23
1480 #define STM_ADC_CR1_JAWDEN 22
1481 #define STM_ADC_CR1_PDI 17
1482 #define STM_ADC_CR1_PDD 16
1483 #define STM_ADC_CR1_DISCNUM 13
1484 #define STM_ADC_CR1_DISCNUM_1 0
1485 #define STM_ADC_CR1_DISCNUM_2 1
1486 #define STM_ADC_CR1_DISCNUM_3 2
1487 #define STM_ADC_CR1_DISCNUM_4 3
1488 #define STM_ADC_CR1_DISCNUM_5 4
1489 #define STM_ADC_CR1_DISCNUM_6 5
1490 #define STM_ADC_CR1_DISCNUM_7 6
1491 #define STM_ADC_CR1_DISCNUM_8 7
1492 #define STM_ADC_CR1_DISCNUM_MASK 7UL
1493 #define STM_ADC_CR1_JDISCEN 12
1494 #define STM_ADC_CR1_DISCEN 11
1495 #define STM_ADC_CR1_JAUTO 10
1496 #define STM_ADC_CR1_AWDSGL 9
1497 #define STM_ADC_CR1_SCAN 8
1498 #define STM_ADC_CR1_JEOCIE 7
1499 #define STM_ADC_CR1_AWDIE 6
1500 #define STM_ADC_CR1_EOCIE 5
1501 #define STM_ADC_CR1_AWDCH 0
1502 #define STM_ADC_CR1_AWDCH_MASK 0x1fUL
1504 #define STM_ADC_CR2_SWSTART 30
1505 #define STM_ADC_CR2_EXTEN 28
1506 #define STM_ADC_CR2_EXTEN_DISABLE 0
1507 #define STM_ADC_CR2_EXTEN_RISING 1
1508 #define STM_ADC_CR2_EXTEN_FALLING 2
1509 #define STM_ADC_CR2_EXTEN_BOTH 3
1510 #define STM_ADC_CR2_EXTEN_MASK 3UL
1511 #define STM_ADC_CR2_EXTSEL 24
1512 #define STM_ADC_CR2_EXTSEL_TIM9_CC2 0
1513 #define STM_ADC_CR2_EXTSEL_TIM9_TRGO 1
1514 #define STM_ADC_CR2_EXTSEL_TIM2_CC3 2
1515 #define STM_ADC_CR2_EXTSEL_TIM2_CC2 3
1516 #define STM_ADC_CR2_EXTSEL_TIM3_TRGO 4
1517 #define STM_ADC_CR2_EXTSEL_TIM4_CC4 5
1518 #define STM_ADC_CR2_EXTSEL_TIM2_TRGO 6
1519 #define STM_ADC_CR2_EXTSEL_TIM3_CC1 7
1520 #define STM_ADC_CR2_EXTSEL_TIM3_CC3 8
1521 #define STM_ADC_CR2_EXTSEL_TIM4_TRGO 9
1522 #define STM_ADC_CR2_EXTSEL_TIM6_TRGO 10
1523 #define STM_ADC_CR2_EXTSEL_EXTI_11 15
1524 #define STM_ADC_CR2_EXTSEL_MASK 15UL
1525 #define STM_ADC_CR2_JWSTART 22
1526 #define STM_ADC_CR2_JEXTEN 20
1527 #define STM_ADC_CR2_JEXTEN_DISABLE 0
1528 #define STM_ADC_CR2_JEXTEN_RISING 1
1529 #define STM_ADC_CR2_JEXTEN_FALLING 2
1530 #define STM_ADC_CR2_JEXTEN_BOTH 3
1531 #define STM_ADC_CR2_JEXTEN_MASK 3UL
1532 #define STM_ADC_CR2_JEXTSEL 16
1533 #define STM_ADC_CR2_JEXTSEL_TIM9_CC1 0
1534 #define STM_ADC_CR2_JEXTSEL_TIM9_TRGO 1
1535 #define STM_ADC_CR2_JEXTSEL_TIM2_TRGO 2
1536 #define STM_ADC_CR2_JEXTSEL_TIM2_CC1 3
1537 #define STM_ADC_CR2_JEXTSEL_TIM3_CC4 4
1538 #define STM_ADC_CR2_JEXTSEL_TIM4_TRGO 5
1539 #define STM_ADC_CR2_JEXTSEL_TIM4_CC1 6
1540 #define STM_ADC_CR2_JEXTSEL_TIM4_CC2 7
1541 #define STM_ADC_CR2_JEXTSEL_TIM4_CC3 8
1542 #define STM_ADC_CR2_JEXTSEL_TIM10_CC1 9
1543 #define STM_ADC_CR2_JEXTSEL_TIM7_TRGO 10
1544 #define STM_ADC_CR2_JEXTSEL_EXTI_15 15
1545 #define STM_ADC_CR2_JEXTSEL_MASK 15UL
1546 #define STM_ADC_CR2_ALIGN 11
1547 #define STM_ADC_CR2_EOCS 10
1548 #define STM_ADC_CR2_DDS 9
1549 #define STM_ADC_CR2_DMA 8
1550 #define STM_ADC_CR2_DELS 4
1551 #define STM_ADC_CR2_DELS_NONE 0
1552 #define STM_ADC_CR2_DELS_UNTIL_READ 1
1553 #define STM_ADC_CR2_DELS_7 2
1554 #define STM_ADC_CR2_DELS_15 3
1555 #define STM_ADC_CR2_DELS_31 4
1556 #define STM_ADC_CR2_DELS_63 5
1557 #define STM_ADC_CR2_DELS_127 6
1558 #define STM_ADC_CR2_DELS_255 7
1559 #define STM_ADC_CR2_DELS_MASK 7UL
1560 #define STM_ADC_CR2_CONT 1
1561 #define STM_ADC_CR2_ADON 0
1563 #define STM_ADC_CCR_TSVREFE 23
1564 #define STM_ADC_CCR_ADCPRE 16
1565 #define STM_ADC_CCR_ADCPRE_HSI_1 0
1566 #define STM_ADC_CCR_ADCPRE_HSI_2 1
1567 #define STM_ADC_CCR_ADCPRE_HSI_4 2
1568 #define STM_ADC_CCR_ADCPRE_MASK 3UL
1570 struct stm_temp_cal {
1572 uint16_t ts_cal_cold;
1574 uint16_t ts_cal_hot;
1577 extern struct stm_temp_cal stm_temp_cal;
1579 #define stm_temp_cal_cold 25
1580 #define stm_temp_cal_hot 110
1582 struct stm_dbg_mcu {
1586 extern struct stm_dbg_mcu stm_dbg_mcu;
1588 static inline uint16_t
1590 return stm_dbg_mcu.idcode & 0xfff;
1593 struct stm_flash_size {
1597 extern struct stm_flash_size stm_flash_size_medium;
1598 extern struct stm_flash_size stm_flash_size_large;
1600 /* Returns flash size in bytes */
1602 stm_flash_size(void);
1604 struct stm_device_id {
1610 extern struct stm_device_id stm_device_id;
1612 #define STM_NUM_I2C 2
1614 #define STM_I2C_INDEX(channel) ((channel) - 1)
1628 extern struct stm_i2c stm_i2c1, stm_i2c2;
1630 #define STM_I2C_CR1_SWRST 15
1631 #define STM_I2C_CR1_ALERT 13
1632 #define STM_I2C_CR1_PEC 12
1633 #define STM_I2C_CR1_POS 11
1634 #define STM_I2C_CR1_ACK 10
1635 #define STM_I2C_CR1_STOP 9
1636 #define STM_I2C_CR1_START 8
1637 #define STM_I2C_CR1_NOSTRETCH 7
1638 #define STM_I2C_CR1_ENGC 6
1639 #define STM_I2C_CR1_ENPEC 5
1640 #define STM_I2C_CR1_ENARP 4
1641 #define STM_I2C_CR1_SMBTYPE 3
1642 #define STM_I2C_CR1_SMBUS 1
1643 #define STM_I2C_CR1_PE 0
1645 #define STM_I2C_CR2_LAST 12
1646 #define STM_I2C_CR2_DMAEN 11
1647 #define STM_I2C_CR2_ITBUFEN 10
1648 #define STM_I2C_CR2_ITEVTEN 9
1649 #define STM_I2C_CR2_ITERREN 8
1650 #define STM_I2C_CR2_FREQ 0
1651 #define STM_I2C_CR2_FREQ_2_MHZ 2
1652 #define STM_I2C_CR2_FREQ_4_MHZ 4
1653 #define STM_I2C_CR2_FREQ_8_MHZ 8
1654 #define STM_I2C_CR2_FREQ_16_MHZ 16
1655 #define STM_I2C_CR2_FREQ_24_MHZ 24
1656 #define STM_I2C_CR2_FREQ_32_MHZ 32
1657 #define STM_I2C_CR2_FREQ_MASK 0x3fUL
1659 #define STM_I2C_SR1_SMBALERT 15
1660 #define STM_I2C_SR1_TIMEOUT 14
1661 #define STM_I2C_SR1_PECERR 12
1662 #define STM_I2C_SR1_OVR 11
1663 #define STM_I2C_SR1_AF 10
1664 #define STM_I2C_SR1_ARLO 9
1665 #define STM_I2C_SR1_BERR 8
1666 #define STM_I2C_SR1_TXE 7
1667 #define STM_I2C_SR1_RXNE 6
1668 #define STM_I2C_SR1_STOPF 4
1669 #define STM_I2C_SR1_ADD10 3
1670 #define STM_I2C_SR1_BTF 2
1671 #define STM_I2C_SR1_ADDR 1
1672 #define STM_I2C_SR1_SB 0
1674 #define STM_I2C_SR2_PEC 8
1675 #define STM_I2C_SR2_PEC_MASK 0xff00UL
1676 #define STM_I2C_SR2_DUALF 7
1677 #define STM_I2C_SR2_SMBHOST 6
1678 #define STM_I2C_SR2_SMBDEFAULT 5
1679 #define STM_I2C_SR2_GENCALL 4
1680 #define STM_I2C_SR2_TRA 2
1681 #define STM_I2C_SR2_BUSY 1
1682 #define STM_I2C_SR2_MSL 0
1684 #define STM_I2C_CCR_FS 15
1685 #define STM_I2C_CCR_DUTY 14
1686 #define STM_I2C_CCR_CCR 0
1687 #define STM_I2C_CCR_MASK 0x7ffUL
1705 uint32_t reserved_30;
1711 uint32_t reserved_44;
1715 uint32_t reserved_50;
1718 extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
1720 #define STM_TIM234_CR1_CKD 8
1721 #define STM_TIM234_CR1_CKD_1 0
1722 #define STM_TIM234_CR1_CKD_2 1
1723 #define STM_TIM234_CR1_CKD_4 2
1724 #define STM_TIM234_CR1_CKD_MASK 3UL
1725 #define STM_TIM234_CR1_ARPE 7
1726 #define STM_TIM234_CR1_CMS 5
1727 #define STM_TIM234_CR1_CMS_EDGE 0
1728 #define STM_TIM234_CR1_CMS_CENTER_1 1
1729 #define STM_TIM234_CR1_CMS_CENTER_2 2
1730 #define STM_TIM234_CR1_CMS_CENTER_3 3
1731 #define STM_TIM234_CR1_CMS_MASK 3UL
1732 #define STM_TIM234_CR1_DIR 4
1733 #define STM_TIM234_CR1_DIR_UP 0
1734 #define STM_TIM234_CR1_DIR_DOWN 1
1735 #define STM_TIM234_CR1_OPM 3
1736 #define STM_TIM234_CR1_URS 2
1737 #define STM_TIM234_CR1_UDIS 1
1738 #define STM_TIM234_CR1_CEN 0
1740 #define STM_TIM234_CR2_TI1S 7
1741 #define STM_TIM234_CR2_MMS 4
1742 #define STM_TIM234_CR2_MMS_RESET 0
1743 #define STM_TIM234_CR2_MMS_ENABLE 1
1744 #define STM_TIM234_CR2_MMS_UPDATE 2
1745 #define STM_TIM234_CR2_MMS_COMPARE_PULSE 3
1746 #define STM_TIM234_CR2_MMS_COMPARE_OC1REF 4
1747 #define STM_TIM234_CR2_MMS_COMPARE_OC2REF 5
1748 #define STM_TIM234_CR2_MMS_COMPARE_OC3REF 6
1749 #define STM_TIM234_CR2_MMS_COMPARE_OC4REF 7
1750 #define STM_TIM234_CR2_MMS_MASK 7UL
1751 #define STM_TIM234_CR2_CCDS 3
1753 #define STM_TIM234_SMCR_ETP 15
1754 #define STM_TIM234_SMCR_ECE 14
1755 #define STM_TIM234_SMCR_ETPS 12
1756 #define STM_TIM234_SMCR_ETPS_OFF 0
1757 #define STM_TIM234_SMCR_ETPS_DIV_2 1
1758 #define STM_TIM234_SMCR_ETPS_DIV_4 2
1759 #define STM_TIM234_SMCR_ETPS_DIV_8 3
1760 #define STM_TIM234_SMCR_ETPS_MASK 3UL
1761 #define STM_TIM234_SMCR_ETF 8
1762 #define STM_TIM234_SMCR_ETF_NONE 0
1763 #define STM_TIM234_SMCR_ETF_INT_N_2 1
1764 #define STM_TIM234_SMCR_ETF_INT_N_4 2
1765 #define STM_TIM234_SMCR_ETF_INT_N_8 3
1766 #define STM_TIM234_SMCR_ETF_DTS_2_N_6 4
1767 #define STM_TIM234_SMCR_ETF_DTS_2_N_8 5
1768 #define STM_TIM234_SMCR_ETF_DTS_4_N_6 6
1769 #define STM_TIM234_SMCR_ETF_DTS_4_N_8 7
1770 #define STM_TIM234_SMCR_ETF_DTS_8_N_6 8
1771 #define STM_TIM234_SMCR_ETF_DTS_8_N_8 9
1772 #define STM_TIM234_SMCR_ETF_DTS_16_N_5 10
1773 #define STM_TIM234_SMCR_ETF_DTS_16_N_6 11
1774 #define STM_TIM234_SMCR_ETF_DTS_16_N_8 12
1775 #define STM_TIM234_SMCR_ETF_DTS_32_N_5 13
1776 #define STM_TIM234_SMCR_ETF_DTS_32_N_6 14
1777 #define STM_TIM234_SMCR_ETF_DTS_32_N_8 15
1778 #define STM_TIM234_SMCR_ETF_MASK 15UL
1779 #define STM_TIM234_SMCR_MSM 7
1780 #define STM_TIM234_SMCR_TS 4
1781 #define STM_TIM234_SMCR_TS_ITR0 0
1782 #define STM_TIM234_SMCR_TS_ITR1 1
1783 #define STM_TIM234_SMCR_TS_ITR2 2
1784 #define STM_TIM234_SMCR_TS_ITR3 3
1785 #define STM_TIM234_SMCR_TS_TI1F_ED 4
1786 #define STM_TIM234_SMCR_TS_TI1FP1 5
1787 #define STM_TIM234_SMCR_TS_TI2FP2 6
1788 #define STM_TIM234_SMCR_TS_ETRF 7
1789 #define STM_TIM234_SMCR_TS_MASK 7UL
1790 #define STM_TIM234_SMCR_OCCS 3
1791 #define STM_TIM234_SMCR_SMS 0
1792 #define STM_TIM234_SMCR_SMS_DISABLE 0
1793 #define STM_TIM234_SMCR_SMS_ENCODER_MODE_1 1
1794 #define STM_TIM234_SMCR_SMS_ENCODER_MODE_2 2
1795 #define STM_TIM234_SMCR_SMS_ENCODER_MODE_3 3
1796 #define STM_TIM234_SMCR_SMS_RESET_MODE 4
1797 #define STM_TIM234_SMCR_SMS_GATED_MODE 5
1798 #define STM_TIM234_SMCR_SMS_TRIGGER_MODE 6
1799 #define STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK 7
1800 #define STM_TIM234_SMCR_SMS_MASK 7UL
1802 #define STM_TIM234_DIER_TDE 14
1803 #define STM_TIM234_DIER_CC4DE 12
1804 #define STM_TIM234_DIER_CC3DE 11
1805 #define STM_TIM234_DIER_CC2DE 10
1806 #define STM_TIM234_DIER_CC1DE 9
1807 #define STM_TIM234_DIER_UDE 8
1809 #define STM_TIM234_DIER_TIE 6
1810 #define STM_TIM234_DIER_CC4IE 4
1811 #define STM_TIM234_DIER_CC3IE 3
1812 #define STM_TIM234_DIER_CC2IE 2
1813 #define STM_TIM234_DIER_CC1IE 1
1814 #define STM_TIM234_DIER_UIE 0
1816 #define STM_TIM234_SR_CC4OF 12
1817 #define STM_TIM234_SR_CC3OF 11
1818 #define STM_TIM234_SR_CC2OF 10
1819 #define STM_TIM234_SR_CC1OF 9
1820 #define STM_TIM234_SR_TIF 6
1821 #define STM_TIM234_SR_CC4IF 4
1822 #define STM_TIM234_SR_CC3IF 3
1823 #define STM_TIM234_SR_CC2IF 2
1824 #define STM_TIM234_SR_CC1IF 1
1825 #define STM_TIM234_SR_UIF 0
1827 #define STM_TIM234_EGR_TG 6
1828 #define STM_TIM234_EGR_CC4G 4
1829 #define STM_TIM234_EGR_CC3G 3
1830 #define STM_TIM234_EGR_CC2G 2
1831 #define STM_TIM234_EGR_CC1G 1
1832 #define STM_TIM234_EGR_UG 0
1834 #define STM_TIM234_CCMR1_OC2CE 15
1835 #define STM_TIM234_CCMR1_OC2M 12
1836 #define STM_TIM234_CCMR1_OC2M_FROZEN 0
1837 #define STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH 1
1838 #define STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH 2
1839 #define STM_TIM234_CCMR1_OC2M_TOGGLE 3
1840 #define STM_TIM234_CCMR1_OC2M_FORCE_LOW 4
1841 #define STM_TIM234_CCMR1_OC2M_FORCE_HIGH 5
1842 #define STM_TIM234_CCMR1_OC2M_PWM_MODE_1 6
1843 #define STM_TIM234_CCMR1_OC2M_PWM_MODE_2 7
1844 #define STM_TIM234_CCMR1_OC2M_MASK 7UL
1845 #define STM_TIM234_CCMR1_OC2PE 11
1846 #define STM_TIM234_CCMR1_OC2FE 10
1847 #define STM_TIM234_CCMR1_CC2S 8
1848 #define STM_TIM234_CCMR1_CC2S_OUTPUT 0
1849 #define STM_TIM234_CCMR1_CC2S_INPUT_TI2 1
1850 #define STM_TIM234_CCMR1_CC2S_INPUT_TI1 2
1851 #define STM_TIM234_CCMR1_CC2S_INPUT_TRC 3
1852 #define STM_TIM234_CCMR1_CC2S_MASK 3UL
1854 #define STM_TIM234_CCMR1_OC1CE 7
1855 #define STM_TIM234_CCMR1_OC1M 4
1856 #define STM_TIM234_CCMR1_OC1M_FROZEN 0
1857 #define STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH 1
1858 #define STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH 2
1859 #define STM_TIM234_CCMR1_OC1M_TOGGLE 3
1860 #define STM_TIM234_CCMR1_OC1M_FORCE_LOW 4
1861 #define STM_TIM234_CCMR1_OC1M_FORCE_HIGH 5
1862 #define STM_TIM234_CCMR1_OC1M_PWM_MODE_1 6
1863 #define STM_TIM234_CCMR1_OC1M_PWM_MODE_2 7
1864 #define STM_TIM234_CCMR1_OC1M_MASK 7UL
1865 #define STM_TIM234_CCMR1_OC1PE 3
1866 #define STM_TIM234_CCMR1_OC1FE 2
1867 #define STM_TIM234_CCMR1_CC1S 0
1868 #define STM_TIM234_CCMR1_CC1S_OUTPUT 0
1869 #define STM_TIM234_CCMR1_CC1S_INPUT_TI1 1
1870 #define STM_TIM234_CCMR1_CC1S_INPUT_TI2 2
1871 #define STM_TIM234_CCMR1_CC1S_INPUT_TRC 3
1872 #define STM_TIM234_CCMR1_CC1S_MASK 3UL
1874 #define STM_TIM234_CCMR1_IC2F 12
1875 #define STM_TIM234_CCMR1_IC2F_NONE 0
1876 #define STM_TIM234_CCMR1_IC2F_CK_INT_N_2 1
1877 #define STM_TIM234_CCMR1_IC2F_CK_INT_N_4 2
1878 #define STM_TIM234_CCMR1_IC2F_CK_INT_N_8 3
1879 #define STM_TIM234_CCMR1_IC2F_DTS_2_N_6 4
1880 #define STM_TIM234_CCMR1_IC2F_DTS_2_N_8 5
1881 #define STM_TIM234_CCMR1_IC2F_DTS_4_N_6 6
1882 #define STM_TIM234_CCMR1_IC2F_DTS_4_N_8 7
1883 #define STM_TIM234_CCMR1_IC2F_DTS_8_N_6 8
1884 #define STM_TIM234_CCMR1_IC2F_DTS_8_N_8 9
1885 #define STM_TIM234_CCMR1_IC2F_DTS_16_N_5 10
1886 #define STM_TIM234_CCMR1_IC2F_DTS_16_N_6 11
1887 #define STM_TIM234_CCMR1_IC2F_DTS_16_N_8 12
1888 #define STM_TIM234_CCMR1_IC2F_DTS_32_N_5 13
1889 #define STM_TIM234_CCMR1_IC2F_DTS_32_N_6 14
1890 #define STM_TIM234_CCMR1_IC2F_DTS_32_N_8 15
1891 #define STM_TIM234_CCMR1_IC2PSC 10
1892 #define STM_TIM234_CCMR1_IC2PSC_NONE 0
1893 #define STM_TIM234_CCMR1_IC2PSC_2 1
1894 #define STM_TIM234_CCMR1_IC2PSC_4 2
1895 #define STM_TIM234_CCMR1_IC2PSC_8 3
1896 #define STM_TIM234_CCMR1_IC1F 4
1897 #define STM_TIM234_CCMR1_IC1F_NONE 0
1898 #define STM_TIM234_CCMR1_IC1F_CK_INT_N_2 1
1899 #define STM_TIM234_CCMR1_IC1F_CK_INT_N_4 2
1900 #define STM_TIM234_CCMR1_IC1F_CK_INT_N_8 3
1901 #define STM_TIM234_CCMR1_IC1F_DTS_2_N_6 4
1902 #define STM_TIM234_CCMR1_IC1F_DTS_2_N_8 5
1903 #define STM_TIM234_CCMR1_IC1F_DTS_4_N_6 6
1904 #define STM_TIM234_CCMR1_IC1F_DTS_4_N_8 7
1905 #define STM_TIM234_CCMR1_IC1F_DTS_8_N_6 8
1906 #define STM_TIM234_CCMR1_IC1F_DTS_8_N_8 9
1907 #define STM_TIM234_CCMR1_IC1F_DTS_16_N_5 10
1908 #define STM_TIM234_CCMR1_IC1F_DTS_16_N_6 11
1909 #define STM_TIM234_CCMR1_IC1F_DTS_16_N_8 12
1910 #define STM_TIM234_CCMR1_IC1F_DTS_32_N_5 13
1911 #define STM_TIM234_CCMR1_IC1F_DTS_32_N_6 14
1912 #define STM_TIM234_CCMR1_IC1F_DTS_32_N_8 15
1913 #define STM_TIM234_CCMR1_IC1PSC 2
1914 #define STM_TIM234_CCMR1_IC1PSC_NONE 0
1915 #define STM_TIM234_CCMR1_IC1PSC_2 1
1916 #define STM_TIM234_CCMR1_IC1PSC_4 2
1917 #define STM_TIM234_CCMR1_IC1PSC_8 3
1919 #define STM_TIM234_CCMR2_OC4CE 15
1920 #define STM_TIM234_CCMR2_OC4M 12
1921 #define STM_TIM234_CCMR2_OC4M_FROZEN 0
1922 #define STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH 1
1923 #define STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH 2
1924 #define STM_TIM234_CCMR2_OC4M_TOGGLE 3
1925 #define STM_TIM234_CCMR2_OC4M_FORCE_LOW 4
1926 #define STM_TIM234_CCMR2_OC4M_FORCE_HIGH 5
1927 #define STM_TIM234_CCMR2_OC4M_PWM_MODE_1 6
1928 #define STM_TIM234_CCMR2_OC4M_PWM_MODE_2 7
1929 #define STM_TIM234_CCMR2_OC4M_MASK 7UL
1930 #define STM_TIM234_CCMR2_OC4PE 11
1931 #define STM_TIM234_CCMR2_OC4FE 10
1932 #define STM_TIM234_CCMR2_CC4S 8
1933 #define STM_TIM234_CCMR2_CC4S_OUTPUT 0
1934 #define STM_TIM234_CCMR2_CC4S_INPUT_TI4 1
1935 #define STM_TIM234_CCMR2_CC4S_INPUT_TI3 2
1936 #define STM_TIM234_CCMR2_CC4S_INPUT_TRC 3
1937 #define STM_TIM234_CCMR2_CC4S_MASK 3UL
1939 #define STM_TIM234_CCMR2_OC3CE 7
1940 #define STM_TIM234_CCMR2_OC3M 4
1941 #define STM_TIM234_CCMR2_OC3M_FROZEN 0
1942 #define STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH 1
1943 #define STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH 2
1944 #define STM_TIM234_CCMR2_OC3M_TOGGLE 3
1945 #define STM_TIM234_CCMR2_OC3M_FORCE_LOW 4
1946 #define STM_TIM234_CCMR2_OC3M_FORCE_HIGH 5
1947 #define STM_TIM234_CCMR2_OC3M_PWM_MODE_1 6
1948 #define STM_TIM234_CCMR2_OC3M_PWM_MODE_2 7
1949 #define STM_TIM234_CCMR2_OC3M_MASK 7UL
1950 #define STM_TIM234_CCMR2_OC3PE 3
1951 #define STM_TIM234_CCMR2_OC3FE 2
1952 #define STM_TIM234_CCMR2_CC3S 0
1953 #define STM_TIM234_CCMR2_CC3S_OUTPUT 0
1954 #define STM_TIM234_CCMR2_CC3S_INPUT_TI3 1
1955 #define STM_TIM234_CCMR2_CC3S_INPUT_TI4 2
1956 #define STM_TIM234_CCMR2_CC3S_INPUT_TRC 3
1957 #define STM_TIM234_CCMR2_CC3S_MASK 3UL
1959 #define STM_TIM234_CCER_CC4NP 15
1960 #define STM_TIM234_CCER_CC4P 13
1961 #define STM_TIM234_CCER_CC4P_ACTIVE_HIGH 0
1962 #define STM_TIM234_CCER_CC4P_ACTIVE_LOW 1
1963 #define STM_TIM234_CCER_CC4E 12
1964 #define STM_TIM234_CCER_CC3NP 11
1965 #define STM_TIM234_CCER_CC3P 9
1966 #define STM_TIM234_CCER_CC3P_ACTIVE_HIGH 0
1967 #define STM_TIM234_CCER_CC3P_ACTIVE_LOW 1
1968 #define STM_TIM234_CCER_CC3E 8
1969 #define STM_TIM234_CCER_CC2NP 7
1970 #define STM_TIM234_CCER_CC2P 5
1971 #define STM_TIM234_CCER_CC2P_ACTIVE_HIGH 0
1972 #define STM_TIM234_CCER_CC2P_ACTIVE_LOW 1
1973 #define STM_TIM234_CCER_CC2E 4
1974 #define STM_TIM234_CCER_CC1NP 3
1975 #define STM_TIM234_CCER_CC1P 1
1976 #define STM_TIM234_CCER_CC1P_ACTIVE_HIGH 0
1977 #define STM_TIM234_CCER_CC1P_ACTIVE_LOW 1
1978 #define STM_TIM234_CCER_CC1E 0
1982 uint8_t reserved_20[0x40 - 0x20];
1990 #define STM_USB_EPR_CTR_RX 15
1991 #define STM_USB_EPR_CTR_RX_WRITE_INVARIANT 1
1992 #define STM_USB_EPR_DTOG_RX 14
1993 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT 0
1994 #define STM_USB_EPR_STAT_RX 12
1995 #define STM_USB_EPR_STAT_RX_DISABLED 0
1996 #define STM_USB_EPR_STAT_RX_STALL 1
1997 #define STM_USB_EPR_STAT_RX_NAK 2
1998 #define STM_USB_EPR_STAT_RX_VALID 3
1999 #define STM_USB_EPR_STAT_RX_MASK 3UL
2000 #define STM_USB_EPR_STAT_RX_WRITE_INVARIANT 0
2001 #define STM_USB_EPR_SETUP 11
2002 #define STM_USB_EPR_EP_TYPE 9
2003 #define STM_USB_EPR_EP_TYPE_BULK 0
2004 #define STM_USB_EPR_EP_TYPE_CONTROL 1
2005 #define STM_USB_EPR_EP_TYPE_ISO 2
2006 #define STM_USB_EPR_EP_TYPE_INTERRUPT 3
2007 #define STM_USB_EPR_EP_TYPE_MASK 3UL
2008 #define STM_USB_EPR_EP_KIND 8
2009 #define STM_USB_EPR_EP_KIND_DBL_BUF 1 /* Bulk */
2010 #define STM_USB_EPR_EP_KIND_STATUS_OUT 1 /* Control */
2011 #define STM_USB_EPR_CTR_TX 7
2012 #define STM_USB_CTR_TX_WRITE_INVARIANT 1
2013 #define STM_USB_EPR_DTOG_TX 6
2014 #define STM_USB_EPR_DTOG_TX_WRITE_INVARIANT 0
2015 #define STM_USB_EPR_STAT_TX 4
2016 #define STM_USB_EPR_STAT_TX_DISABLED 0
2017 #define STM_USB_EPR_STAT_TX_STALL 1
2018 #define STM_USB_EPR_STAT_TX_NAK 2
2019 #define STM_USB_EPR_STAT_TX_VALID 3
2020 #define STM_USB_EPR_STAT_TX_WRITE_INVARIANT 0
2021 #define STM_USB_EPR_STAT_TX_MASK 3UL
2022 #define STM_USB_EPR_EA 0
2023 #define STM_USB_EPR_EA_MASK 0xfUL
2025 #define STM_USB_CNTR_CTRM 15
2026 #define STM_USB_CNTR_PMAOVRM 14
2027 #define STM_USB_CNTR_ERRM 13
2028 #define STM_USB_CNTR_WKUPM 12
2029 #define STM_USB_CNTR_SUSPM 11
2030 #define STM_USB_CNTR_RESETM 10
2031 #define STM_USB_CNTR_SOFM 9
2032 #define STM_USB_CNTR_ESOFM 8
2033 #define STM_USB_CNTR_RESUME 4
2034 #define STM_USB_CNTR_FSUSP 3
2035 #define STM_USB_CNTR_LP_MODE 2
2036 #define STM_USB_CNTR_PDWN 1
2037 #define STM_USB_CNTR_FRES 0
2039 #define STM_USB_ISTR_CTR 15
2040 #define STM_USB_ISTR_PMAOVR 14
2041 #define STM_USB_ISTR_ERR 13
2042 #define STM_USB_ISTR_WKUP 12
2043 #define STM_USB_ISTR_SUSP 11
2044 #define STM_USB_ISTR_RESET 10
2045 #define STM_USB_ISTR_SOF 9
2046 #define STM_USB_ISTR_ESOF 8
2047 #define STM_USB_ISTR_DIR 4
2048 #define STM_USB_ISTR_EP_ID 0
2049 #define STM_USB_ISTR_EP_ID_MASK 0xfUL
2051 #define STM_USB_FNR_RXDP 15
2052 #define STM_USB_FNR_RXDM 14
2053 #define STM_USB_FNR_LCK 13
2054 #define STM_USB_FNR_LSOF 11
2055 #define STM_USB_FNR_LSOF_MASK 0x3UL
2056 #define STM_USB_FNR_FN 0
2057 #define STM_USB_FNR_FN_MASK 0x7ffUL
2059 #define STM_USB_DADDR_EF 7
2060 #define STM_USB_DADDR_ADD 0
2061 #define STM_USB_DADDR_ADD_MASK 0x7fUL
2063 extern struct stm_usb stm_usb;
2082 #define STM_USB_BDT_COUNT_RX_BL_SIZE 15
2083 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK 10
2084 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK 0x1fUL
2085 #define STM_USB_BDT_COUNT_RX_COUNT_RX 0
2086 #define STM_USB_BDT_COUNT_RX_COUNT_RX_MASK 0x1ffUL
2088 #define STM_USB_BDT_SIZE 8
2090 extern uint8_t stm_usb_sram[] __attribute__ ((aligned(4)));
2102 extern struct stm_exti stm_exti;
2104 #endif /* _STM32L_H_ */