2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
23 typedef volatile uint32_t vuint32_t;
40 #define STM_MODER_SHIFT(pin) ((pin) << 1)
41 #define STM_MODER_MASK 3
42 #define STM_MODER_INPUT 0
43 #define STM_MODER_OUTPUT 1
44 #define STM_MODER_ALTERNATE 2
45 #define STM_MODER_ANALOG 3
48 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
49 gpio->moder = ((gpio->moder &
50 ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
51 value << STM_MODER_SHIFT(pin));
54 static inline vuint32_t
55 stm_moder_get(struct stm_gpio *gpio, int pin) {
56 return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
59 #define STM_OTYPER_SHIFT(pin) (pin)
60 #define STM_OTYPER_MASK 1
61 #define STM_OTYPER_PUSH_PULL 0
62 #define STM_OTYPER_OPEN_DRAIN 1
65 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
66 gpio->otyper = ((gpio->otyper &
67 ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
68 value << STM_OTYPER_SHIFT(pin));
71 static inline vuint32_t
72 stm_otyper_get(struct stm_gpio *gpio, int pin) {
73 return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
76 #define STM_OSPEEDR_SHIFT(pin) ((pin) << 1)
77 #define STM_OSPEEDR_MASK 3
78 #define STM_OSPEEDR_400kHz 0
79 #define STM_OSPEEDR_2MHz 1
80 #define STM_OSPEEDR_10MHz 2
81 #define STM_OSPEEDR_40MHz 3
84 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
85 gpio->ospeedr = ((gpio->ospeedr &
86 ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
87 value << STM_OSPEEDR_SHIFT(pin));
90 static inline vuint32_t
91 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
92 return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
95 #define STM_PUPDR_SHIFT(pin) ((pin) << 1)
96 #define STM_PUPDR_MASK 3
97 #define STM_PUPDR_NONE 0
98 #define STM_PUPDR_PULL_UP 1
99 #define STM_PUPDR_PULL_DOWN 2
100 #define STM_PUPDR_RESERVED 3
103 stm_pupdr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
104 gpio->pupdr = ((gpio->pupdr &
105 ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
106 value << STM_PUPDR_SHIFT(pin));
109 static inline vuint32_t
110 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
111 return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
114 #define STM_AFR_SHIFT(pin) ((pin) << 2)
115 #define STM_AFR_MASK 0xf
116 #define STM_AFR_NONE 0
117 #define STM_AFR_AF0 0x0
118 #define STM_AFR_AF1 0x1
119 #define STM_AFR_AF2 0x2
120 #define STM_AFR_AF3 0x3
121 #define STM_AFR_AF4 0x4
122 #define STM_AFR_AF5 0x5
123 #define STM_AFR_AF6 0x6
124 #define STM_AFR_AF7 0x7
125 #define STM_AFR_AF8 0x8
126 #define STM_AFR_AF9 0x9
127 #define STM_AFR_AF10 0xa
128 #define STM_AFR_AF11 0xb
129 #define STM_AFR_AF12 0xc
130 #define STM_AFR_AF13 0xd
131 #define STM_AFR_AF14 0xe
132 #define STM_AFR_AF15 0xf
135 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
137 gpio->afrl = ((gpio->afrl &
138 ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
139 value << STM_AFR_SHIFT(pin));
142 gpio->afrh = ((gpio->afrh &
143 ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
144 value << STM_AFR_SHIFT(pin));
148 static inline uint32_t
149 stm_afr_get(struct stm_gpio *gpio, int pin) {
151 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
154 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
158 extern struct stm_gpio stm_gpioa;
159 extern struct stm_gpio stm_gpiob;
160 extern struct stm_gpio stm_gpioc;
161 extern struct stm_gpio stm_gpiod;
162 extern struct stm_gpio stm_gpioe;
163 extern struct stm_gpio stm_gpioh;
166 vuint32_t sr; /* status register */
167 vuint32_t dr; /* data register */
168 vuint32_t brr; /* baud rate register */
169 vuint32_t cr1; /* control register 1 */
171 vuint32_t cr2; /* control register 2 */
172 vuint32_t cr3; /* control register 3 */
173 vuint32_t gtpr; /* guard time and prescaler */
176 extern struct stm_usart stm_usart1;
178 #define STM_USART_SR_CTS (9) /* CTS flag */
179 #define STM_USART_SR_LBD (8) /* LIN break detection flag */
180 #define STM_USART_SR_TXE (7) /* Transmit data register empty */
181 #define STM_USART_SR_TC (6) /* Transmission complete */
182 #define STM_USART_SR_RXNE (5) /* Read data register not empty */
183 #define STM_USART_SR_IDLE (4) /* IDLE line detected */
184 #define STM_USART_SR_ORE (3) /* Overrun error */
185 #define STM_USART_SR_NF (2) /* Noise detected flag */
186 #define STM_USART_SR_FE (1) /* Framing error */
187 #define STM_USART_SR_PE (0) /* Parity error */
189 #define STM_USART_CR1_OVER8 (15) /* Oversampling mode */
190 #define STM_USART_CR1_UE (13) /* USART enable */
191 #define STM_USART_CR1_M (12) /* Word length */
192 #define STM_USART_CR1_WAKE (11) /* Wakeup method */
193 #define STM_USART_CR1_PCE (10) /* Parity control enable */
194 #define STM_USART_CR1_PS (9) /* Parity selection */
195 #define STM_USART_CR1_PEIE (8) /* PE interrupt enable */
196 #define STM_USART_CR1_TXEIE (7) /* TXE interrupt enable */
197 #define STM_USART_CR1_TCIE (6) /* Transmission complete interrupt enable */
198 #define STM_USART_CR1_RXNEIE (5) /* RXNE interrupt enable */
199 #define STM_USART_CR1_IDLEIE (4) /* IDLE interrupt enable */
200 #define STM_USART_CR1_TE (3) /* Transmitter enable */
201 #define STM_USART_CR1_RE (2) /* Receiver enable */
202 #define STM_USART_CR1_RWU (1) /* Receiver wakeup */
203 #define STM_USART_CR1_SBK (0) /* Send break */
205 #define STM_USART_CR2_LINEN (14) /* LIN mode enable */
206 #define STM_USART_CR2_STOP (12) /* STOP bits */
207 #define STM_USART_CR2_STOP_MASK 3
208 #define STM_USART_CR2_STOP_1 0
209 #define STM_USART_CR2_STOP_0_5 1
210 #define STM_USART_CR2_STOP_2 2
211 #define STM_USART_CR2_STOP_1_5 3
213 #define STM_USART_CR2_CLKEN (11) /* Clock enable */
214 #define STM_USART_CR2_CPOL (10) /* Clock polarity */
215 #define STM_USART_CR2_CPHA (9) /* Clock phase */
216 #define STM_USART_CR2_LBCL (8) /* Last bit clock pulse */
217 #define STM_USART_CR2_LBDIE (6) /* LIN break detection interrupt enable */
218 #define STM_USART_CR2_LBDL (5) /* lin break detection length */
219 #define STM_USART_CR2_ADD (0)
220 #define STM_USART_CR2_ADD_MASK 0xf
222 #define STM_USART_CR3_ONEBITE (11) /* One sample bit method enable */
223 #define STM_USART_CR3_CTSIE (10) /* CTS interrupt enable */
224 #define STM_USART_CR3_CTSE (9) /* CTS enable */
225 #define STM_USART_CR3_RTSE (8) /* RTS enable */
226 #define STM_USART_CR3_DMAT (7) /* DMA enable transmitter */
227 #define STM_USART_CR3_DMAR (6) /* DMA enable receiver */
228 #define STM_USART_CR3_SCEN (5) /* Smartcard mode enable */
229 #define STM_USART_CR3_NACK (4) /* Smartcard NACK enable */
230 #define STM_USART_CR3_HDSEL (3) /* Half-duplex selection */
231 #define STM_USART_CR3_IRLP (2) /* IrDA low-power */
232 #define STM_USART_CR3_IREN (1) /* IrDA mode enable */
233 #define STM_USART_CR3_EIE (0) /* Error interrupt enable */
238 extern struct stm_spi stm_spi1;
243 extern struct stm_tim stm_tim9;
244 extern struct stm_tim stm_tim10;
245 extern struct stm_tim stm_tim11;
247 /* Flash interface */
263 extern struct stm_flash stm_flash;
265 #define STM_FLASH_ACR_RUN_PD (4)
266 #define STM_FLASH_ACR_SLEEP_PD (3)
267 #define STM_FLASH_ACR_ACC64 (2)
268 #define STM_FLASH_ACR_PRFEN (1)
269 #define STM_FLASH_ACR_LATENCY (0)
291 extern struct stm_rcc stm_rcc;
293 #define STM_RCC_CR_RTCPRE (29)
294 #define STM_RCC_CR_RTCPRE_HSE_DIV_2 0
295 #define STM_RCC_CR_RTCPRE_HSE_DIV_4 1
296 #define STM_RCC_CR_RTCPRE_HSE_DIV_8 2
297 #define STM_RCC_CR_RTCPRE_HSE_DIV_16 3
298 #define STM_RCC_CR_RTCPRE_HSE_MASK 3
300 #define STM_RCC_CR_CSSON (28)
301 #define STM_RCC_CR_PLLRDY (25)
302 #define STM_RCC_CR_PLLON (24)
303 #define STM_RCC_CR_HSEBYP (18)
304 #define STM_RCC_CR_HSERDY (17)
305 #define STM_RCC_CR_HSEON (16)
306 #define STM_RCC_CR_MSIRDY (9)
307 #define STM_RCC_CR_MSION (8)
308 #define STM_RCC_CR_HSIRDY (1)
309 #define STM_RCC_CR_HSION (0)
311 #define STM_RCC_CFGR_MCOPRE (28)
312 #define STM_RCC_CFGR_MCOPRE_DIV_1 0
313 #define STM_RCC_CFGR_MCOPRE_DIV_2 1
314 #define STM_RCC_CFGR_MCOPRE_DIV_4 2
315 #define STM_RCC_CFGR_MCOPRE_DIV_8 3
316 #define STM_RCC_CFGR_MCOPRE_DIV_16 4
317 #define STM_RCC_CFGR_MCOPRE_DIV_MASK 7
319 #define STM_RCC_CFGR_MCOSEL (24)
320 #define STM_RCC_CFGR_MCOSEL_DISABLE 0
321 #define STM_RCC_CFGR_MCOSEL_SYSCLK 1
322 #define STM_RCC_CFGR_MCOSEL_HSI 2
323 #define STM_RCC_CFGR_MCOSEL_MSI 3
324 #define STM_RCC_CFGR_MCOSEL_HSE 4
325 #define STM_RCC_CFGR_MCOSEL_PLL 5
326 #define STM_RCC_CFGR_MCOSEL_LSI 6
327 #define STM_RCC_CFGR_MCOSEL_LSE 7
328 #define STM_RCC_CFGR_MCOSEL_MASK 7
330 #define STM_RCC_CFGR_PLLDIV (22)
331 #define STM_RCC_CFGR_PLLDIV_2 1
332 #define STM_RCC_CFGR_PLLDIV_3 2
333 #define STM_RCC_CFGR_PLLDIV_4 3
334 #define STM_RCC_CFGR_PLLDIV_MASK 3
336 #define STM_RCC_CFGR_PLLMUL (18)
337 #define STM_RCC_CFGR_PLLMUL_3 0
338 #define STM_RCC_CFGR_PLLMUL_4 1
339 #define STM_RCC_CFGR_PLLMUL_6 2
340 #define STM_RCC_CFGR_PLLMUL_8 3
341 #define STM_RCC_CFGR_PLLMUL_12 4
342 #define STM_RCC_CFGR_PLLMUL_16 5
343 #define STM_RCC_CFGR_PLLMUL_24 6
344 #define STM_RCC_CFGR_PLLMUL_32 7
345 #define STM_RCC_CFGR_PLLMUL_48 8
346 #define STM_RCC_CFGR_PLLMUL_MASK 0xf
348 #define STM_RCC_CFGR_PLLSRC (16)
350 #define STM_RCC_CFGR_PPRE2 (11)
351 #define STM_RCC_CFGR_PPRE2_DIV_1 0
352 #define STM_RCC_CFGR_PPRE2_DIV_2 4
353 #define STM_RCC_CFGR_PPRE2_DIV_4 5
354 #define STM_RCC_CFGR_PPRE2_DIV_8 6
355 #define STM_RCC_CFGR_PPRE2_DIV_16 7
356 #define STM_RCC_CFGR_PPRE2_MASK 7
358 #define STM_RCC_CFGR_PPRE1 (8)
359 #define STM_RCC_CFGR_PPRE1_DIV_1 0
360 #define STM_RCC_CFGR_PPRE1_DIV_2 4
361 #define STM_RCC_CFGR_PPRE1_DIV_4 5
362 #define STM_RCC_CFGR_PPRE1_DIV_8 6
363 #define STM_RCC_CFGR_PPRE1_DIV_16 7
364 #define STM_RCC_CFGR_PPRE1_MASK 7
366 #define STM_RCC_CFGR_HPRE (4)
367 #define STM_RCC_CFGR_HPRE_DIV_1 0
368 #define STM_RCC_CFGR_HPRE_DIV_2 8
369 #define STM_RCC_CFGR_HPRE_DIV_4 9
370 #define STM_RCC_CFGR_HPRE_DIV_8 0xa
371 #define STM_RCC_CFGR_HPRE_DIV_16 0xb
372 #define STM_RCC_CFGR_HPRE_DIV_64 0xc
373 #define STM_RCC_CFGR_HPRE_DIV_128 0xd
374 #define STM_RCC_CFGR_HPRE_DIV_256 0xe
375 #define STM_RCC_CFGR_HPRE_DIV_512 0xf
376 #define STM_RCC_CFGR_HPRE_MASK 0xf
378 #define STM_RCC_CFGR_SWS (2)
379 #define STM_RCC_CFGR_SWS_MSI 0
380 #define STM_RCC_CFGR_SWS_HSI 1
381 #define STM_RCC_CFGR_SWS_HSE 2
382 #define STM_RCC_CFGR_SWS_PLL 3
383 #define STM_RCC_CFGR_SWS_MASK 3
385 #define STM_RCC_CFGR_SW (0)
386 #define STM_RCC_CFGR_SW_MSI 0
387 #define STM_RCC_CFGR_SW_HSI 1
388 #define STM_RCC_CFGR_SW_HSE 2
389 #define STM_RCC_CFGR_SW_PLL 3
390 #define STM_RCC_CFGR_SW_MASK 3
392 #define STM_RCC_AHBENR_DMA1EN (24)
393 #define STM_RCC_AHBENR_FLITFEN (15)
394 #define STM_RCC_AHBENR_CRCEN (12)
395 #define STM_RCC_AHBENR_GPIOHEN (5)
396 #define STM_RCC_AHBENR_GPIOEEN (4)
397 #define STM_RCC_AHBENR_GPIODEN (3)
398 #define STM_RCC_AHBENR_GPIOCEN (2)
399 #define STM_RCC_AHBENR_GPIOBEN (1)
400 #define STM_RCC_AHBENR_GPIOAEN (0)
402 #define STM_RCC_APB2ENR_USART1EN (14)
403 #define STM_RCC_APB2ENR_SPI1EN (12)
404 #define STM_RCC_APB2ENR_ADC1EN (9)
405 #define STM_RCC_APB2ENR_TIM11EN (4)
406 #define STM_RCC_APB2ENR_TIM10EN (3)
407 #define STM_RCC_APB2ENR_TIM9EN (2)
408 #define STM_RCC_APB2ENR_SYSCFGEN (0)
410 #define STM_RCC_APB1ENR_COMPEN (31)
411 #define STM_RCC_APB1ENR_DACEN (29)
412 #define STM_RCC_APB1ENR_PWREN (28)
413 #define STM_RCC_APB1ENR_USBEN (23)
414 #define STM_RCC_APB1ENR_I2C2EN (22)
415 #define STM_RCC_APB1ENR_I2C1EN (21)
416 #define STM_RCC_APB1ENR_USART3EN (18)
417 #define STM_RCC_APB1ENR_USART2EN (17)
418 #define STM_RCC_APB1ENR_SPI2EN (14)
419 #define STM_RCC_APB1ENR_WWDGEN (11)
420 #define STM_RCC_APB1ENR_LCDEN (9)
421 #define STM_RCC_APB1ENR_TIM7EN (5)
422 #define STM_RCC_APB1ENR_TIM6EN (4)
423 #define STM_RCC_APB1ENR_TIM4EN (2)
424 #define STM_RCC_APB1ENR_TIM3EN (1)
425 #define STM_RCC_APB1ENR_TIM2EN (0)
432 extern struct stm_pwr stm_pwr;
434 #define STM_PWR_CR_LPRUN (14)
436 #define STM_PWR_CR_VOS (11)
437 #define STM_PWR_CR_VOS_1_8 1
438 #define STM_PWR_CR_VOS_1_5 2
439 #define STM_PWR_CR_VOS_1_2 3
440 #define STM_PWR_CR_VOS_MASK 3
442 #define STM_PWR_CR_FWU (10)
443 #define STM_PWR_CR_ULP (9)
444 #define STM_PWR_CR_DBP (8)
446 #define STM_PWR_CR_PLS (5)
447 #define STM_PWR_CR_PLS_1_9 0
448 #define STM_PWR_CR_PLS_2_1 1
449 #define STM_PWR_CR_PLS_2_3 2
450 #define STM_PWR_CR_PLS_2_5 3
451 #define STM_PWR_CR_PLS_2_7 4
452 #define STM_PWR_CR_PLS_2_9 5
453 #define STM_PWR_CR_PLS_3_1 6
454 #define STM_PWR_CR_PLS_EXT 7
455 #define STM_PWR_CR_PLS_MASK 7
457 #define STM_PWR_CR_PVDE (4)
458 #define STM_PWR_CR_CSBF (3)
459 #define STM_PWR_CR_CWUF (2)
460 #define STM_PWR_CR_PDDS (1)
461 #define STM_PWR_CR_LPSDSR (0)
463 #define STM_PWR_CSR_EWUP3 (10)
464 #define STM_PWR_CSR_EWUP2 (9)
465 #define STM_PWR_CSR_EWUP1 (8)
466 #define STM_PWR_CSR_REGLPF (5)
467 #define STM_PWR_CSR_VOSF (4)
468 #define STM_PWR_CSR_VREFINTRDYF (3)
469 #define STM_PWR_CSR_PVDO (2)
470 #define STM_PWR_CSR_SBF (1)
471 #define STM_PWR_CSR_WUF (0)
490 extern struct stm_tim67 stm_tim6;
492 #define STM_TIM67_CR1_ARPE (7)
493 #define STM_TIM67_CR1_OPM (3)
494 #define STM_TIM67_CR1_URS (2)
495 #define STM_TIM67_CR1_UDIS (1)
496 #define STM_TIM67_CR1_CEN (0)
498 #define STM_TIM67_CR2_MMS (4)
499 #define STM_TIM67_CR2_MMS_RESET 0
500 #define STM_TIM67_CR2_MMS_ENABLE 1
501 #define STM_TIM67_CR2_MMS_UPDATE 2
502 #define STM_TIM67_CR2_MMS_MASK 7
504 #define STM_TIM67_DIER_UDE (8)
505 #define STM_TIM67_DIER_UIE (0)
507 #define STM_TIM67_SR_UIF (0)
509 #define STM_TIM67_EGR_UG (0)
512 vuint32_t iser[3]; /* 0x000 */
514 uint8_t _unused00c[0x080 - 0x00c];
516 vuint32_t icer[3]; /* 0x080 */
518 uint8_t _unused08c[0x100 - 0x08c];
520 vuint32_t ispr[3]; /* 0x100 */
522 uint8_t _unused10c[0x180 - 0x10c];
524 vuint32_t icpr[3]; /* 0x180 */
526 uint8_t _unused18c[0x200 - 0x18c];
528 vuint32_t iabr[3]; /* 0x200 */
530 uint8_t _unused20c[0x300 - 0x20c];
532 vuint32_t ipr[21]; /* 0x300 */
534 uint8_t _unused324[0xe00 - 0x324];
536 vuint32_t stir; /* 0xe00 */
539 extern struct stm_nvic stm_nvic;
541 #define IRQ_REG(irq) ((irq) >> 5)
542 #define IRQ_BIT(irq) ((irq) & 0x1f)
543 #define IRQ_MASK(irq) (1 << IRQ_BIT(irq))
544 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
547 stm_nvic_set_enable(int irq) {
548 stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
552 stm_nvic_clear_enable(int irq) {
553 stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
557 stm_nvic_enabled(int irq) {
558 return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
562 stm_nvic_set_pending(int irq) {
563 stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
567 stm_nvic_clear_pending(int irq) {
568 stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
572 stm_nvic_pending(int irq) {
573 return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
577 stm_nvic_active(int irq) {
578 return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
581 #define IRQ_PRIO_REG(irq) ((irq) >> 2)
582 #define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3)
583 #define IRQ_PRIO_MASK(irq) (0xff << IRQ_PRIO_BIT(irq))
586 stm_nvic_set_priority(int irq, uint8_t prio) {
587 int n = IRQ_PRIO_REG(irq);
591 v &= ~IRQ_PRIO_MASK(irq);
592 v |= (prio) << IRQ_PRIO_BIT(irq);
596 static inline uint8_t
597 stm_nvic_get_priority(int irq) {
598 return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
601 #define isr(name) void stm_ ## name ## _isr(void);
658 #define STM_ISR_TIM9_POS 25
659 #define STM_ISR_TIM10_POS 26
660 #define STM_ISR_TIM11_POS 27
661 #define STM_ISR_TIM2_POS 28
662 #define STM_ISR_TIM3_POS 29
663 #define STM_ISR_TIM4_POS 30
665 #define STM_ISR_SPI1_POS 35
666 #define STM_ISR_SPI2_POS 36
667 #define STM_ISR_USART1_POS 37
668 #define STM_ISR_USART2_POS 38
669 #define STM_ISR_USART3_POS 39
670 #define STM_ISR_TIM6_POS 43
671 #define STM_ISR_TIM7_POS 44
675 #endif /* _STM32L_H_ */