2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
23 typedef volatile uint32_t vuint32_t;
24 typedef volatile void * vvoid_t;
41 #define STM_MODER_SHIFT(pin) ((pin) << 1)
42 #define STM_MODER_MASK 3
43 #define STM_MODER_INPUT 0
44 #define STM_MODER_OUTPUT 1
45 #define STM_MODER_ALTERNATE 2
46 #define STM_MODER_ANALOG 3
49 stm_moder_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
50 gpio->moder = ((gpio->moder &
51 ~(STM_MODER_MASK << STM_MODER_SHIFT(pin))) |
52 value << STM_MODER_SHIFT(pin));
55 static inline uint32_t
56 stm_moder_get(struct stm_gpio *gpio, int pin) {
57 return (gpio->moder >> STM_MODER_SHIFT(pin)) & STM_MODER_MASK;
60 #define STM_OTYPER_SHIFT(pin) (pin)
61 #define STM_OTYPER_MASK 1
62 #define STM_OTYPER_PUSH_PULL 0
63 #define STM_OTYPER_OPEN_DRAIN 1
66 stm_otyper_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
67 gpio->otyper = ((gpio->otyper &
68 ~(STM_OTYPER_MASK << STM_OTYPER_SHIFT(pin))) |
69 value << STM_OTYPER_SHIFT(pin));
72 static inline uint32_t
73 stm_otyper_get(struct stm_gpio *gpio, int pin) {
74 return (gpio->otyper >> STM_OTYPER_SHIFT(pin)) & STM_OTYPER_MASK;
77 #define STM_OSPEEDR_SHIFT(pin) ((pin) << 1)
78 #define STM_OSPEEDR_MASK 3
79 #define STM_OSPEEDR_400kHz 0
80 #define STM_OSPEEDR_2MHz 1
81 #define STM_OSPEEDR_10MHz 2
82 #define STM_OSPEEDR_40MHz 3
85 stm_ospeedr_set(struct stm_gpio *gpio, int pin, vuint32_t value) {
86 gpio->ospeedr = ((gpio->ospeedr &
87 ~(STM_OSPEEDR_MASK << STM_OSPEEDR_SHIFT(pin))) |
88 value << STM_OSPEEDR_SHIFT(pin));
91 static inline uint32_t
92 stm_ospeedr_get(struct stm_gpio *gpio, int pin) {
93 return (gpio->ospeedr >> STM_OSPEEDR_SHIFT(pin)) & STM_OSPEEDR_MASK;
96 #define STM_PUPDR_SHIFT(pin) ((pin) << 1)
97 #define STM_PUPDR_MASK 3
98 #define STM_PUPDR_NONE 0
99 #define STM_PUPDR_PULL_UP 1
100 #define STM_PUPDR_PULL_DOWN 2
101 #define STM_PUPDR_RESERVED 3
104 stm_pupdr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
105 gpio->pupdr = ((gpio->pupdr &
106 ~(STM_PUPDR_MASK << STM_PUPDR_SHIFT(pin))) |
107 value << STM_PUPDR_SHIFT(pin));
110 static inline uint32_t
111 stm_pupdr_get(struct stm_gpio *gpio, int pin) {
112 return (gpio->pupdr >> STM_PUPDR_SHIFT(pin)) & STM_PUPDR_MASK;
115 #define STM_AFR_SHIFT(pin) ((pin) << 2)
116 #define STM_AFR_MASK 0xf
117 #define STM_AFR_NONE 0
118 #define STM_AFR_AF0 0x0
119 #define STM_AFR_AF1 0x1
120 #define STM_AFR_AF2 0x2
121 #define STM_AFR_AF3 0x3
122 #define STM_AFR_AF4 0x4
123 #define STM_AFR_AF5 0x5
124 #define STM_AFR_AF6 0x6
125 #define STM_AFR_AF7 0x7
126 #define STM_AFR_AF8 0x8
127 #define STM_AFR_AF9 0x9
128 #define STM_AFR_AF10 0xa
129 #define STM_AFR_AF11 0xb
130 #define STM_AFR_AF12 0xc
131 #define STM_AFR_AF13 0xd
132 #define STM_AFR_AF14 0xe
133 #define STM_AFR_AF15 0xf
136 stm_afr_set(struct stm_gpio *gpio, int pin, uint32_t value) {
138 * Set alternate pin mode too
140 stm_moder_set(gpio, pin, STM_MODER_ALTERNATE);
142 gpio->afrl = ((gpio->afrl &
143 ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
144 value << STM_AFR_SHIFT(pin));
147 gpio->afrh = ((gpio->afrh &
148 ~(STM_AFR_MASK << STM_AFR_SHIFT(pin))) |
149 value << STM_AFR_SHIFT(pin));
153 static inline uint32_t
154 stm_afr_get(struct stm_gpio *gpio, int pin) {
156 return (gpio->afrl >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
159 return (gpio->afrh >> STM_AFR_SHIFT(pin)) & STM_AFR_MASK;
164 stm_gpio_set(struct stm_gpio *gpio, int pin, uint8_t value) {
165 /* Use the bit set/reset register to do this atomically */
166 gpio->bsrr = ((uint32_t) (value ^ 1) << (pin + 16)) | ((uint32_t) value << pin);
169 static inline uint8_t
170 stm_gpio_get(struct stm_gpio *gpio, int pin) {
171 return (gpio->idr >> pin) & 1;
174 static inline uint16_t
175 stm_gpio_get_all(struct stm_gpio *gpio) {
180 * We can't define these in registers.ld or our fancy
181 * ao_enable_gpio macro will expand into a huge pile of code
182 * as the compiler won't do correct constant folding and
183 * dead-code elimination
185 extern struct stm_gpio stm_gpioa;
186 extern struct stm_gpio stm_gpiob;
187 extern struct stm_gpio stm_gpioc;
188 extern struct stm_gpio stm_gpiod;
189 extern struct stm_gpio stm_gpioe;
190 extern struct stm_gpio stm_gpioh;
194 #define stm_gpioh (*((struct stm_gpio *) 0x40021400))
195 #define stm_gpioe (*((struct stm_gpio *) 0x40021000))
196 #define stm_gpiod (*((struct stm_gpio *) 0x40020c00))
197 #define stm_gpioc (*((struct stm_gpio *) 0x40020800))
198 #define stm_gpiob (*((struct stm_gpio *) 0x40020400))
199 #define stm_gpioa (*((struct stm_gpio *) 0x40020000))
202 vuint32_t sr; /* status register */
203 vuint32_t dr; /* data register */
204 vuint32_t brr; /* baud rate register */
205 vuint32_t cr1; /* control register 1 */
207 vuint32_t cr2; /* control register 2 */
208 vuint32_t cr3; /* control register 3 */
209 vuint32_t gtpr; /* guard time and prescaler */
212 extern struct stm_usart stm_usart1;
213 extern struct stm_usart stm_usart2;
214 extern struct stm_usart stm_usart3;
216 #define STM_USART_SR_CTS (9) /* CTS flag */
217 #define STM_USART_SR_LBD (8) /* LIN break detection flag */
218 #define STM_USART_SR_TXE (7) /* Transmit data register empty */
219 #define STM_USART_SR_TC (6) /* Transmission complete */
220 #define STM_USART_SR_RXNE (5) /* Read data register not empty */
221 #define STM_USART_SR_IDLE (4) /* IDLE line detected */
222 #define STM_USART_SR_ORE (3) /* Overrun error */
223 #define STM_USART_SR_NF (2) /* Noise detected flag */
224 #define STM_USART_SR_FE (1) /* Framing error */
225 #define STM_USART_SR_PE (0) /* Parity error */
227 #define STM_USART_CR1_OVER8 (15) /* Oversampling mode */
228 #define STM_USART_CR1_UE (13) /* USART enable */
229 #define STM_USART_CR1_M (12) /* Word length */
230 #define STM_USART_CR1_WAKE (11) /* Wakeup method */
231 #define STM_USART_CR1_PCE (10) /* Parity control enable */
232 #define STM_USART_CR1_PS (9) /* Parity selection */
233 #define STM_USART_CR1_PEIE (8) /* PE interrupt enable */
234 #define STM_USART_CR1_TXEIE (7) /* TXE interrupt enable */
235 #define STM_USART_CR1_TCIE (6) /* Transmission complete interrupt enable */
236 #define STM_USART_CR1_RXNEIE (5) /* RXNE interrupt enable */
237 #define STM_USART_CR1_IDLEIE (4) /* IDLE interrupt enable */
238 #define STM_USART_CR1_TE (3) /* Transmitter enable */
239 #define STM_USART_CR1_RE (2) /* Receiver enable */
240 #define STM_USART_CR1_RWU (1) /* Receiver wakeup */
241 #define STM_USART_CR1_SBK (0) /* Send break */
243 #define STM_USART_CR2_LINEN (14) /* LIN mode enable */
244 #define STM_USART_CR2_STOP (12) /* STOP bits */
245 #define STM_USART_CR2_STOP_MASK 3
246 #define STM_USART_CR2_STOP_1 0
247 #define STM_USART_CR2_STOP_0_5 1
248 #define STM_USART_CR2_STOP_2 2
249 #define STM_USART_CR2_STOP_1_5 3
251 #define STM_USART_CR2_CLKEN (11) /* Clock enable */
252 #define STM_USART_CR2_CPOL (10) /* Clock polarity */
253 #define STM_USART_CR2_CPHA (9) /* Clock phase */
254 #define STM_USART_CR2_LBCL (8) /* Last bit clock pulse */
255 #define STM_USART_CR2_LBDIE (6) /* LIN break detection interrupt enable */
256 #define STM_USART_CR2_LBDL (5) /* lin break detection length */
257 #define STM_USART_CR2_ADD (0)
258 #define STM_USART_CR2_ADD_MASK 0xf
260 #define STM_USART_CR3_ONEBITE (11) /* One sample bit method enable */
261 #define STM_USART_CR3_CTSIE (10) /* CTS interrupt enable */
262 #define STM_USART_CR3_CTSE (9) /* CTS enable */
263 #define STM_USART_CR3_RTSE (8) /* RTS enable */
264 #define STM_USART_CR3_DMAT (7) /* DMA enable transmitter */
265 #define STM_USART_CR3_DMAR (6) /* DMA enable receiver */
266 #define STM_USART_CR3_SCEN (5) /* Smartcard mode enable */
267 #define STM_USART_CR3_NACK (4) /* Smartcard NACK enable */
268 #define STM_USART_CR3_HDSEL (3) /* Half-duplex selection */
269 #define STM_USART_CR3_IRLP (2) /* IrDA low-power */
270 #define STM_USART_CR3_IREN (1) /* IrDA mode enable */
271 #define STM_USART_CR3_EIE (0) /* Error interrupt enable */
276 extern struct stm_tim stm_tim9;
302 extern struct stm_tim1011 stm_tim10;
303 extern struct stm_tim1011 stm_tim11;
305 #define STM_TIM1011_CR1_CKD 8
306 #define STM_TIM1011_CR1_CKD_1 0
307 #define STM_TIM1011_CR1_CKD_2 1
308 #define STM_TIM1011_CR1_CKD_4 2
309 #define STM_TIM1011_CR1_CKD_MASK 3
310 #define STM_TIM1011_CR1_ARPE 7
311 #define STM_TIM1011_CR1_URS 2
312 #define STM_TIM1011_CR1_UDIS 1
313 #define STM_TIM1011_CR1_CEN 0
315 #define STM_TIM1011_SMCR_ETP 15
316 #define STM_TIM1011_SMCR_ECE 14
317 #define STM_TIM1011_SMCR_ETPS 12
318 #define STM_TIM1011_SMCR_ETPS_OFF 0
319 #define STM_TIM1011_SMCR_ETPS_2 1
320 #define STM_TIM1011_SMCR_ETPS_4 2
321 #define STM_TIM1011_SMCR_ETPS_8 3
322 #define STM_TIM1011_SMCR_ETPS_MASK 3
323 #define STM_TIM1011_SMCR_ETF 8
324 #define STM_TIM1011_SMCR_ETF_NONE 0
325 #define STM_TIM1011_SMCR_ETF_CK_INT_2 1
326 #define STM_TIM1011_SMCR_ETF_CK_INT_4 2
327 #define STM_TIM1011_SMCR_ETF_CK_INT_8 3
328 #define STM_TIM1011_SMCR_ETF_DTS_2_6 4
329 #define STM_TIM1011_SMCR_ETF_DTS_2_8 5
330 #define STM_TIM1011_SMCR_ETF_DTS_4_6 6
331 #define STM_TIM1011_SMCR_ETF_DTS_4_8 7
332 #define STM_TIM1011_SMCR_ETF_DTS_8_6 8
333 #define STM_TIM1011_SMCR_ETF_DTS_8_8 9
334 #define STM_TIM1011_SMCR_ETF_DTS_16_5 10
335 #define STM_TIM1011_SMCR_ETF_DTS_16_6 11
336 #define STM_TIM1011_SMCR_ETF_DTS_16_8 12
337 #define STM_TIM1011_SMCR_ETF_DTS_32_5 13
338 #define STM_TIM1011_SMCR_ETF_DTS_32_6 14
339 #define STM_TIM1011_SMCR_ETF_DTS_32_8 15
340 #define STM_TIM1011_SMCR_ETF_MASK 15
342 #define STM_TIM1011_DIER_CC1E 1
343 #define STM_TIM1011_DIER_UIE 0
345 #define STM_TIM1011_SR_CC1OF 9
346 #define STM_TIM1011_SR_CC1IF 1
347 #define STM_TIM1011_SR_UIF 0
349 #define STM_TIM1011_EGR_CC1G 1
350 #define STM_TIM1011_EGR_UG 0
352 #define STM_TIM1011_CCMR1_OC1CE 7
353 #define STM_TIM1011_CCMR1_OC1M 4
354 #define STM_TIM1011_CCMR1_OC1M_FROZEN 0
355 #define STM_TIM1011_CCMR1_OC1M_SET_1_ACTIVE_ON_MATCH 1
356 #define STM_TIM1011_CCMR1_OC1M_SET_1_INACTIVE_ON_MATCH 2
357 #define STM_TIM1011_CCMR1_OC1M_TOGGLE 3
358 #define STM_TIM1011_CCMR1_OC1M_FORCE_INACTIVE 4
359 #define STM_TIM1011_CCMR1_OC1M_FORCE_ACTIVE 5
360 #define STM_TIM1011_CCMR1_OC1M_PWM_MODE_1 6
361 #define STM_TIM1011_CCMR1_OC1M_PWM_MODE_2 7
362 #define STM_TIM1011_CCMR1_OC1M_MASK 7
363 #define STM_TIM1011_CCMR1_OC1PE 3
364 #define STM_TIM1011_CCMR1_OC1FE 2
365 #define STM_TIM1011_CCMR1_CC1S 0
366 #define STM_TIM1011_CCMR1_CC1S_OUTPUT 0
367 #define STM_TIM1011_CCMR1_CC1S_INPUT_TI1 1
368 #define STM_TIM1011_CCMR1_CC1S_INPUT_TI2 2
369 #define STM_TIM1011_CCMR1_CC1S_INPUT_TRC 3
370 #define STM_TIM1011_CCMR1_CC1S_MASK 3
372 #define STM_TIM1011_CCMR1_IC1F_NONE 0
373 #define STM_TIM1011_CCMR1_IC1F_CK_INT_2 1
374 #define STM_TIM1011_CCMR1_IC1F_CK_INT_4 2
375 #define STM_TIM1011_CCMR1_IC1F_CK_INT_8 3
376 #define STM_TIM1011_CCMR1_IC1F_DTS_2_6 4
377 #define STM_TIM1011_CCMR1_IC1F_DTS_2_8 5
378 #define STM_TIM1011_CCMR1_IC1F_DTS_4_6 6
379 #define STM_TIM1011_CCMR1_IC1F_DTS_4_8 7
380 #define STM_TIM1011_CCMR1_IC1F_DTS_8_6 8
381 #define STM_TIM1011_CCMR1_IC1F_DTS_8_8 9
382 #define STM_TIM1011_CCMR1_IC1F_DTS_16_5 10
383 #define STM_TIM1011_CCMR1_IC1F_DTS_16_6 11
384 #define STM_TIM1011_CCMR1_IC1F_DTS_16_8 12
385 #define STM_TIM1011_CCMR1_IC1F_DTS_32_5 13
386 #define STM_TIM1011_CCMR1_IC1F_DTS_32_6 14
387 #define STM_TIM1011_CCMR1_IC1F_DTS_32_8 15
388 #define STM_TIM1011_CCMR1_IC1F_MASK 15
389 #define STM_TIM1011_CCMR1_IC1PSC 2
390 #define STM_TIM1011_CCMR1_IC1PSC_1 0
391 #define STM_TIM1011_CCMR1_IC1PSC_2 1
392 #define STM_TIM1011_CCMR1_IC1PSC_4 2
393 #define STM_TIM1011_CCMR1_IC1PSC_8 3
394 #define STM_TIM1011_CCMR1_IC1PSC_MASK 3
395 #define STM_TIM1011_CCMR1_CC1S 0
397 #define STM_TIM1011_CCER_CC1NP 3
398 #define STM_TIM1011_CCER_CC1P 1
399 #define STM_TIM1011_CCER_CC1E 0
401 #define STM_TIM1011_OR_TI1_RMP_RI 3
402 #define STM_TIM1011_ETR_RMP 2
403 #define STM_TIM1011_TI1_RMP 0
404 #define STM_TIM1011_TI1_RMP_GPIO 0
405 #define STM_TIM1011_TI1_RMP_LSI 1
406 #define STM_TIM1011_TI1_RMP_LSE 2
407 #define STM_TIM1011_TI1_RMP_RTC 3
408 #define STM_TIM1011_TI1_RMP_MASK 3
410 /* Flash interface */
426 extern struct stm_flash stm_flash;
428 #define STM_FLASH_ACR_RUN_PD (4)
429 #define STM_FLASH_ACR_SLEEP_PD (3)
430 #define STM_FLASH_ACR_ACC64 (2)
431 #define STM_FLASH_ACR_PRFEN (1)
432 #define STM_FLASH_ACR_LATENCY (0)
434 #define STM_FLASH_PECR_OBL_LAUNCH 18
435 #define STM_FLASH_PECR_ERRIE 17
436 #define STM_FLASH_PECR_EOPIE 16
437 #define STM_FLASH_PECR_FPRG 10
438 #define STM_FLASH_PECR_ERASE 9
439 #define STM_FLASH_PECR_FTDW 8
440 #define STM_FLASH_PECR_DATA 4
441 #define STM_FLASH_PECR_PROG 3
442 #define STM_FLASH_PECR_OPTLOCK 2
443 #define STM_FLASH_PECR_PRGLOCK 1
444 #define STM_FLASH_PECR_PELOCK 0
446 #define STM_FLASH_SR_OPTVERR 11
447 #define STM_FLASH_SR_SIZERR 10
448 #define STM_FLASH_SR_PGAERR 9
449 #define STM_FLASH_SR_WRPERR 8
450 #define STM_FLASH_SR_READY 3
451 #define STM_FLASH_SR_ENDHV 2
452 #define STM_FLASH_SR_EOP 1
453 #define STM_FLASH_SR_BSY 0
455 #define STM_FLASH_PEKEYR_PEKEY1 0x89ABCDEF
456 #define STM_FLASH_PEKEYR_PEKEY2 0x02030405
458 #define STM_FLASH_PRGKEYR_PRGKEY1 0x8C9DAEBF
459 #define STM_FLASH_PRGKEYR_PRGKEY2 0x13141516
481 extern struct stm_rcc stm_rcc;
483 /* Nominal high speed internal oscillator frequency is 16MHz */
484 #define STM_HSI_FREQ 16000000
486 #define STM_RCC_CR_RTCPRE (29)
487 #define STM_RCC_CR_RTCPRE_HSE_DIV_2 0
488 #define STM_RCC_CR_RTCPRE_HSE_DIV_4 1
489 #define STM_RCC_CR_RTCPRE_HSE_DIV_8 2
490 #define STM_RCC_CR_RTCPRE_HSE_DIV_16 3
491 #define STM_RCC_CR_RTCPRE_HSE_MASK 3
493 #define STM_RCC_CR_CSSON (28)
494 #define STM_RCC_CR_PLLRDY (25)
495 #define STM_RCC_CR_PLLON (24)
496 #define STM_RCC_CR_HSEBYP (18)
497 #define STM_RCC_CR_HSERDY (17)
498 #define STM_RCC_CR_HSEON (16)
499 #define STM_RCC_CR_MSIRDY (9)
500 #define STM_RCC_CR_MSION (8)
501 #define STM_RCC_CR_HSIRDY (1)
502 #define STM_RCC_CR_HSION (0)
504 #define STM_RCC_CFGR_MCOPRE (28)
505 #define STM_RCC_CFGR_MCOPRE_DIV_1 0
506 #define STM_RCC_CFGR_MCOPRE_DIV_2 1
507 #define STM_RCC_CFGR_MCOPRE_DIV_4 2
508 #define STM_RCC_CFGR_MCOPRE_DIV_8 3
509 #define STM_RCC_CFGR_MCOPRE_DIV_16 4
510 #define STM_RCC_CFGR_MCOPRE_DIV_MASK 7
512 #define STM_RCC_CFGR_MCOSEL (24)
513 #define STM_RCC_CFGR_MCOSEL_DISABLE 0
514 #define STM_RCC_CFGR_MCOSEL_SYSCLK 1
515 #define STM_RCC_CFGR_MCOSEL_HSI 2
516 #define STM_RCC_CFGR_MCOSEL_MSI 3
517 #define STM_RCC_CFGR_MCOSEL_HSE 4
518 #define STM_RCC_CFGR_MCOSEL_PLL 5
519 #define STM_RCC_CFGR_MCOSEL_LSI 6
520 #define STM_RCC_CFGR_MCOSEL_LSE 7
521 #define STM_RCC_CFGR_MCOSEL_MASK 7
523 #define STM_RCC_CFGR_PLLDIV (22)
524 #define STM_RCC_CFGR_PLLDIV_2 1
525 #define STM_RCC_CFGR_PLLDIV_3 2
526 #define STM_RCC_CFGR_PLLDIV_4 3
527 #define STM_RCC_CFGR_PLLDIV_MASK 3
529 #define STM_RCC_CFGR_PLLMUL (18)
530 #define STM_RCC_CFGR_PLLMUL_3 0
531 #define STM_RCC_CFGR_PLLMUL_4 1
532 #define STM_RCC_CFGR_PLLMUL_6 2
533 #define STM_RCC_CFGR_PLLMUL_8 3
534 #define STM_RCC_CFGR_PLLMUL_12 4
535 #define STM_RCC_CFGR_PLLMUL_16 5
536 #define STM_RCC_CFGR_PLLMUL_24 6
537 #define STM_RCC_CFGR_PLLMUL_32 7
538 #define STM_RCC_CFGR_PLLMUL_48 8
539 #define STM_RCC_CFGR_PLLMUL_MASK 0xf
541 #define STM_RCC_CFGR_PLLSRC (16)
543 #define STM_RCC_CFGR_PPRE2 (11)
544 #define STM_RCC_CFGR_PPRE2_DIV_1 0
545 #define STM_RCC_CFGR_PPRE2_DIV_2 4
546 #define STM_RCC_CFGR_PPRE2_DIV_4 5
547 #define STM_RCC_CFGR_PPRE2_DIV_8 6
548 #define STM_RCC_CFGR_PPRE2_DIV_16 7
549 #define STM_RCC_CFGR_PPRE2_MASK 7
551 #define STM_RCC_CFGR_PPRE1 (8)
552 #define STM_RCC_CFGR_PPRE1_DIV_1 0
553 #define STM_RCC_CFGR_PPRE1_DIV_2 4
554 #define STM_RCC_CFGR_PPRE1_DIV_4 5
555 #define STM_RCC_CFGR_PPRE1_DIV_8 6
556 #define STM_RCC_CFGR_PPRE1_DIV_16 7
557 #define STM_RCC_CFGR_PPRE1_MASK 7
559 #define STM_RCC_CFGR_HPRE (4)
560 #define STM_RCC_CFGR_HPRE_DIV_1 0
561 #define STM_RCC_CFGR_HPRE_DIV_2 8
562 #define STM_RCC_CFGR_HPRE_DIV_4 9
563 #define STM_RCC_CFGR_HPRE_DIV_8 0xa
564 #define STM_RCC_CFGR_HPRE_DIV_16 0xb
565 #define STM_RCC_CFGR_HPRE_DIV_64 0xc
566 #define STM_RCC_CFGR_HPRE_DIV_128 0xd
567 #define STM_RCC_CFGR_HPRE_DIV_256 0xe
568 #define STM_RCC_CFGR_HPRE_DIV_512 0xf
569 #define STM_RCC_CFGR_HPRE_MASK 0xf
571 #define STM_RCC_CFGR_SWS (2)
572 #define STM_RCC_CFGR_SWS_MSI 0
573 #define STM_RCC_CFGR_SWS_HSI 1
574 #define STM_RCC_CFGR_SWS_HSE 2
575 #define STM_RCC_CFGR_SWS_PLL 3
576 #define STM_RCC_CFGR_SWS_MASK 3
578 #define STM_RCC_CFGR_SW (0)
579 #define STM_RCC_CFGR_SW_MSI 0
580 #define STM_RCC_CFGR_SW_HSI 1
581 #define STM_RCC_CFGR_SW_HSE 2
582 #define STM_RCC_CFGR_SW_PLL 3
583 #define STM_RCC_CFGR_SW_MASK 3
585 #define STM_RCC_AHBENR_DMA1EN (24)
586 #define STM_RCC_AHBENR_FLITFEN (15)
587 #define STM_RCC_AHBENR_CRCEN (12)
588 #define STM_RCC_AHBENR_GPIOHEN (5)
589 #define STM_RCC_AHBENR_GPIOEEN (4)
590 #define STM_RCC_AHBENR_GPIODEN (3)
591 #define STM_RCC_AHBENR_GPIOCEN (2)
592 #define STM_RCC_AHBENR_GPIOBEN (1)
593 #define STM_RCC_AHBENR_GPIOAEN (0)
595 #define STM_RCC_APB2ENR_USART1EN (14)
596 #define STM_RCC_APB2ENR_SPI1EN (12)
597 #define STM_RCC_APB2ENR_ADC1EN (9)
598 #define STM_RCC_APB2ENR_TIM11EN (4)
599 #define STM_RCC_APB2ENR_TIM10EN (3)
600 #define STM_RCC_APB2ENR_TIM9EN (2)
601 #define STM_RCC_APB2ENR_SYSCFGEN (0)
603 #define STM_RCC_APB1ENR_COMPEN (31)
604 #define STM_RCC_APB1ENR_DACEN (29)
605 #define STM_RCC_APB1ENR_PWREN (28)
606 #define STM_RCC_APB1ENR_USBEN (23)
607 #define STM_RCC_APB1ENR_I2C2EN (22)
608 #define STM_RCC_APB1ENR_I2C1EN (21)
609 #define STM_RCC_APB1ENR_USART3EN (18)
610 #define STM_RCC_APB1ENR_USART2EN (17)
611 #define STM_RCC_APB1ENR_SPI2EN (14)
612 #define STM_RCC_APB1ENR_WWDGEN (11)
613 #define STM_RCC_APB1ENR_LCDEN (9)
614 #define STM_RCC_APB1ENR_TIM7EN (5)
615 #define STM_RCC_APB1ENR_TIM6EN (4)
616 #define STM_RCC_APB1ENR_TIM4EN (2)
617 #define STM_RCC_APB1ENR_TIM3EN (1)
618 #define STM_RCC_APB1ENR_TIM2EN (0)
620 #define STM_RCC_CSR_LPWRRSTF (31)
621 #define STM_RCC_CSR_WWDGRSTF (30)
622 #define STM_RCC_CSR_IWDGRSTF (29)
623 #define STM_RCC_CSR_SFTRSTF (28)
624 #define STM_RCC_CSR_PORRSTF (27)
625 #define STM_RCC_CSR_PINRSTF (26)
626 #define STM_RCC_CSR_OBLRSTF (25)
627 #define STM_RCC_CSR_RMVF (24)
628 #define STM_RCC_CSR_RTFRST (23)
629 #define STM_RCC_CSR_RTCEN (22)
630 #define STM_RCC_CSR_RTCSEL (16)
632 #define STM_RCC_CSR_RTCSEL_NONE 0
633 #define STM_RCC_CSR_RTCSEL_LSE 1
634 #define STM_RCC_CSR_RTCSEL_LSI 2
635 #define STM_RCC_CSR_RTCSEL_HSE 3
636 #define STM_RCC_CSR_RTCSEL_MASK 3
638 #define STM_RCC_CSR_LSEBYP (10)
639 #define STM_RCC_CSR_LSERDY (9)
640 #define STM_RCC_CSR_LSEON (8)
641 #define STM_RCC_CSR_LSIRDY (1)
642 #define STM_RCC_CSR_LSION (0)
649 extern struct stm_pwr stm_pwr;
651 #define STM_PWR_CR_LPRUN (14)
653 #define STM_PWR_CR_VOS (11)
654 #define STM_PWR_CR_VOS_1_8 1
655 #define STM_PWR_CR_VOS_1_5 2
656 #define STM_PWR_CR_VOS_1_2 3
657 #define STM_PWR_CR_VOS_MASK 3
659 #define STM_PWR_CR_FWU (10)
660 #define STM_PWR_CR_ULP (9)
661 #define STM_PWR_CR_DBP (8)
663 #define STM_PWR_CR_PLS (5)
664 #define STM_PWR_CR_PLS_1_9 0
665 #define STM_PWR_CR_PLS_2_1 1
666 #define STM_PWR_CR_PLS_2_3 2
667 #define STM_PWR_CR_PLS_2_5 3
668 #define STM_PWR_CR_PLS_2_7 4
669 #define STM_PWR_CR_PLS_2_9 5
670 #define STM_PWR_CR_PLS_3_1 6
671 #define STM_PWR_CR_PLS_EXT 7
672 #define STM_PWR_CR_PLS_MASK 7
674 #define STM_PWR_CR_PVDE (4)
675 #define STM_PWR_CR_CSBF (3)
676 #define STM_PWR_CR_CWUF (2)
677 #define STM_PWR_CR_PDDS (1)
678 #define STM_PWR_CR_LPSDSR (0)
680 #define STM_PWR_CSR_EWUP3 (10)
681 #define STM_PWR_CSR_EWUP2 (9)
682 #define STM_PWR_CSR_EWUP1 (8)
683 #define STM_PWR_CSR_REGLPF (5)
684 #define STM_PWR_CSR_VOSF (4)
685 #define STM_PWR_CSR_VREFINTRDYF (3)
686 #define STM_PWR_CSR_PVDO (2)
687 #define STM_PWR_CSR_SBF (1)
688 #define STM_PWR_CSR_WUF (0)
707 extern struct stm_tim67 stm_tim6;
709 #define STM_TIM67_CR1_ARPE (7)
710 #define STM_TIM67_CR1_OPM (3)
711 #define STM_TIM67_CR1_URS (2)
712 #define STM_TIM67_CR1_UDIS (1)
713 #define STM_TIM67_CR1_CEN (0)
715 #define STM_TIM67_CR2_MMS (4)
716 #define STM_TIM67_CR2_MMS_RESET 0
717 #define STM_TIM67_CR2_MMS_ENABLE 1
718 #define STM_TIM67_CR2_MMS_UPDATE 2
719 #define STM_TIM67_CR2_MMS_MASK 7
721 #define STM_TIM67_DIER_UDE (8)
722 #define STM_TIM67_DIER_UIE (0)
724 #define STM_TIM67_SR_UIF (0)
726 #define STM_TIM67_EGR_UG (0)
733 uint32_t unused_0x10;
737 extern struct stm_lcd stm_lcd;
739 #define STM_LCD_CR_MUX_SEG (7)
741 #define STM_LCD_CR_BIAS (5)
742 #define STM_LCD_CR_BIAS_1_4 0
743 #define STM_LCD_CR_BIAS_1_2 1
744 #define STM_LCD_CR_BIAS_1_3 2
745 #define STM_LCD_CR_BIAS_MASK 3
747 #define STM_LCD_CR_DUTY (2)
748 #define STM_LCD_CR_DUTY_STATIC 0
749 #define STM_LCD_CR_DUTY_1_2 1
750 #define STM_LCD_CR_DUTY_1_3 2
751 #define STM_LCD_CR_DUTY_1_4 3
752 #define STM_LCD_CR_DUTY_1_8 4
753 #define STM_LCD_CR_DUTY_MASK 7
755 #define STM_LCD_CR_VSEL (1)
756 #define STM_LCD_CR_LCDEN (0)
758 #define STM_LCD_FCR_PS (22)
759 #define STM_LCD_FCR_PS_1 0x0
760 #define STM_LCD_FCR_PS_2 0x1
761 #define STM_LCD_FCR_PS_4 0x2
762 #define STM_LCD_FCR_PS_8 0x3
763 #define STM_LCD_FCR_PS_16 0x4
764 #define STM_LCD_FCR_PS_32 0x5
765 #define STM_LCD_FCR_PS_64 0x6
766 #define STM_LCD_FCR_PS_128 0x7
767 #define STM_LCD_FCR_PS_256 0x8
768 #define STM_LCD_FCR_PS_512 0x9
769 #define STM_LCD_FCR_PS_1024 0xa
770 #define STM_LCD_FCR_PS_2048 0xb
771 #define STM_LCD_FCR_PS_4096 0xc
772 #define STM_LCD_FCR_PS_8192 0xd
773 #define STM_LCD_FCR_PS_16384 0xe
774 #define STM_LCD_FCR_PS_32768 0xf
775 #define STM_LCD_FCR_PS_MASK 0xf
777 #define STM_LCD_FCR_DIV (18)
778 #define STM_LCD_FCR_DIV_16 0x0
779 #define STM_LCD_FCR_DIV_17 0x1
780 #define STM_LCD_FCR_DIV_18 0x2
781 #define STM_LCD_FCR_DIV_19 0x3
782 #define STM_LCD_FCR_DIV_20 0x4
783 #define STM_LCD_FCR_DIV_21 0x5
784 #define STM_LCD_FCR_DIV_22 0x6
785 #define STM_LCD_FCR_DIV_23 0x7
786 #define STM_LCD_FCR_DIV_24 0x8
787 #define STM_LCD_FCR_DIV_25 0x9
788 #define STM_LCD_FCR_DIV_26 0xa
789 #define STM_LCD_FCR_DIV_27 0xb
790 #define STM_LCD_FCR_DIV_28 0xc
791 #define STM_LCD_FCR_DIV_29 0xd
792 #define STM_LCD_FCR_DIV_30 0xe
793 #define STM_LCD_FCR_DIV_31 0xf
794 #define STM_LCD_FCR_DIV_MASK 0xf
796 #define STM_LCD_FCR_BLINK (16)
797 #define STM_LCD_FCR_BLINK_DISABLE 0
798 #define STM_LCD_FCR_BLINK_SEG0_COM0 1
799 #define STM_LCD_FCR_BLINK_SEG0_COMALL 2
800 #define STM_LCD_FCR_BLINK_SEGALL_COMALL 3
801 #define STM_LCD_FCR_BLINK_MASK 3
803 #define STM_LCD_FCR_BLINKF (13)
804 #define STM_LCD_FCR_BLINKF_8 0
805 #define STM_LCD_FCR_BLINKF_16 1
806 #define STM_LCD_FCR_BLINKF_32 2
807 #define STM_LCD_FCR_BLINKF_64 3
808 #define STM_LCD_FCR_BLINKF_128 4
809 #define STM_LCD_FCR_BLINKF_256 5
810 #define STM_LCD_FCR_BLINKF_512 6
811 #define STM_LCD_FCR_BLINKF_1024 7
812 #define STM_LCD_FCR_BLINKF_MASK 7
814 #define STM_LCD_FCR_CC (10)
815 #define STM_LCD_FCR_CC_MASK 7
817 #define STM_LCD_FCR_DEAD (7)
818 #define STM_LCD_FCR_DEAD_MASK 7
820 #define STM_LCD_FCR_PON (4)
821 #define STM_LCD_FCR_PON_MASK 7
823 #define STM_LCD_FCR_UDDIE (3)
824 #define STM_LCD_FCR_SOFIE (1)
825 #define STM_LCD_FCR_HD (0)
827 #define STM_LCD_SR_FCRSF (5)
828 #define STM_LCD_SR_RDY (4)
829 #define STM_LCD_SR_UDD (3)
830 #define STM_LCD_SR_UDR (2)
831 #define STM_LCD_SR_SOF (1)
832 #define STM_LCD_SR_ENS (0)
834 #define STM_LCD_CLR_UDDC (3)
835 #define STM_LCD_CLR_SOFC (1)
837 /* The SYSTICK starts at 0xe000e010 */
846 extern struct stm_systick stm_systick;
848 #define STM_SYSTICK_CSR_ENABLE 0
849 #define STM_SYSTICK_CSR_TICKINT 1
850 #define STM_SYSTICK_CSR_CLKSOURCE 2
851 #define STM_SYSTICK_CSR_CLKSOURCE_HCLK_8 0
852 #define STM_SYSTICK_CSR_CLKSOURCE_HCLK 1
853 #define STM_SYSTICK_CSR_COUNTFLAG 16
855 /* The NVIC starts at 0xe000e100, so add that to the offsets to find the absolute address */
858 vuint32_t iser[8]; /* 0x000 0xe000e100 Set Enable Register */
860 uint8_t _unused020[0x080 - 0x020];
862 vuint32_t icer[8]; /* 0x080 0xe000e180 Clear Enable Register */
864 uint8_t _unused0a0[0x100 - 0x0a0];
866 vuint32_t ispr[8]; /* 0x100 0xe000e200 Set Pending Register */
868 uint8_t _unused120[0x180 - 0x120];
870 vuint32_t icpr[8]; /* 0x180 0xe000e280 Clear Pending Register */
872 uint8_t _unused1a0[0x200 - 0x1a0];
874 vuint32_t iabr[8]; /* 0x200 0xe000e300 Active Bit Register */
876 uint8_t _unused220[0x300 - 0x220];
878 vuint32_t ipr[60]; /* 0x300 0xe000e400 Priority Register */
880 uint8_t _unused3f0[0xc00 - 0x3f0];
882 vuint32_t cpuid_base; /* 0xc00 0xe000ed00 CPUID Base Register */
883 vuint32_t ics; /* 0xc04 0xe000ed04 Interrupt Control State Register */
884 vuint32_t vto; /* 0xc08 0xe000ed08 Vector Table Offset Register */
885 vuint32_t ai_rc; /* 0xc0c 0xe000ed0c Application Interrupt/Reset Control Register */
886 vuint32_t sc; /* 0xc10 0xe000ed10 System Control Register */
887 vuint32_t cc; /* 0xc14 0xe000ed14 Configuration Control Register */
889 uint8_t _unusedc18[0xe00 - 0xc18];
891 vuint32_t stir; /* 0xe00 */
894 extern struct stm_nvic stm_nvic;
896 #define IRQ_REG(irq) ((irq) >> 5)
897 #define IRQ_BIT(irq) ((irq) & 0x1f)
898 #define IRQ_MASK(irq) (1 << IRQ_BIT(irq))
899 #define IRQ_BOOL(v,irq) (((v) >> IRQ_BIT(irq)) & 1)
902 stm_nvic_set_enable(int irq) {
903 stm_nvic.iser[IRQ_REG(irq)] = IRQ_MASK(irq);
907 stm_nvic_clear_enable(int irq) {
908 stm_nvic.icer[IRQ_REG(irq)] = IRQ_MASK(irq);
912 stm_nvic_enabled(int irq) {
913 return IRQ_BOOL(stm_nvic.iser[IRQ_REG(irq)], irq);
917 stm_nvic_set_pending(int irq) {
918 stm_nvic.ispr[IRQ_REG(irq)] = IRQ_MASK(irq);
922 stm_nvic_clear_pending(int irq) {
923 stm_nvic.icpr[IRQ_REG(irq)] = IRQ_MASK(irq);
927 stm_nvic_pending(int irq) {
928 return IRQ_BOOL(stm_nvic.ispr[IRQ_REG(irq)], irq);
932 stm_nvic_active(int irq) {
933 return IRQ_BOOL(stm_nvic.iabr[IRQ_REG(irq)], irq);
936 #define IRQ_PRIO_REG(irq) ((irq) >> 2)
937 #define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3)
938 #define IRQ_PRIO_MASK(irq) (0xff << IRQ_PRIO_BIT(irq))
941 stm_nvic_set_priority(int irq, uint8_t prio) {
942 int n = IRQ_PRIO_REG(irq);
946 v &= ~IRQ_PRIO_MASK(irq);
947 v |= (prio) << IRQ_PRIO_BIT(irq);
951 static inline uint8_t
952 stm_nvic_get_priority(int irq) {
953 return (stm_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
977 extern struct stm_scb stm_scb;
979 #define STM_SCB_AIRCR_VECTKEY 16
980 #define STM_SCB_AIRCR_VECTKEY_KEY 0x05fa
981 #define STM_SCB_AIRCR_PRIGROUP 8
982 #define STM_SCB_AIRCR_SYSRESETREQ 2
983 #define STM_SCB_AIRCR_VECTCLRACTIVE 1
984 #define STM_SCB_AIRCR_VECTRESET 0
1001 extern struct stm_mpu stm_mpu;
1003 #define STM_MPU_TYPER_IREGION 16
1004 #define STM_MPU_TYPER_IREGION_MASK 0xff
1005 #define STM_MPU_TYPER_DREGION 8
1006 #define STM_MPU_TYPER_DREGION_MASK 0xff
1007 #define STM_MPU_TYPER_SEPARATE 0
1009 #define STM_MPU_CR_PRIVDEFENA 2
1010 #define STM_MPU_CR_HFNMIENA 1
1011 #define STM_MPU_CR_ENABLE 0
1013 #define STM_MPU_RNR_REGION 0
1014 #define STM_MPU_RNR_REGION_MASK 0xff
1016 #define STM_MPU_RBAR_ADDR 5
1017 #define STM_MPU_RBAR_ADDR_MASK 0x7ffffff
1019 #define STM_MPU_RBAR_VALID 4
1020 #define STM_MPU_RBAR_REGION 0
1021 #define STM_MPU_RBAR_REGION_MASK 0xf
1023 #define STM_MPU_RASR_XN 28
1024 #define STM_MPU_RASR_AP 24
1025 #define STM_MPU_RASR_AP_NONE_NONE 0
1026 #define STM_MPU_RASR_AP_RW_NONE 1
1027 #define STM_MPU_RASR_AP_RW_RO 2
1028 #define STM_MPU_RASR_AP_RW_RW 3
1029 #define STM_MPU_RASR_AP_RO_NONE 5
1030 #define STM_MPU_RASR_AP_RO_RO 6
1031 #define STM_MPU_RASR_AP_MASK 7
1032 #define STM_MPU_RASR_TEX 19
1033 #define STM_MPU_RASR_TEX_MASK 7
1034 #define STM_MPU_RASR_S 18
1035 #define STM_MPU_RASR_C 17
1036 #define STM_MPU_RASR_B 16
1037 #define STM_MPU_RASR_SRD 8
1038 #define STM_MPU_RASR_SRD_MASK 0xff
1039 #define STM_MPU_RASR_SIZE 1
1040 #define STM_MPU_RASR_SIZE_MASK 0x1f
1041 #define STM_MPU_RASR_ENABLE 0
1043 #define isr(name) void stm_ ## name ## _isr(void);
1102 #define STM_ISR_WWDG_POS 0
1103 #define STM_ISR_PVD_POS 1
1104 #define STM_ISR_TAMPER_STAMP_POS 2
1105 #define STM_ISR_RTC_WKUP_POS 3
1106 #define STM_ISR_FLASH_POS 4
1107 #define STM_ISR_RCC_POS 5
1108 #define STM_ISR_EXTI0_POS 6
1109 #define STM_ISR_EXTI1_POS 7
1110 #define STM_ISR_EXTI2_POS 8
1111 #define STM_ISR_EXTI3_POS 9
1112 #define STM_ISR_EXTI4_POS 10
1113 #define STM_ISR_DMA1_CHANNEL1_POS 11
1114 #define STM_ISR_DMA2_CHANNEL1_POS 12
1115 #define STM_ISR_DMA3_CHANNEL1_POS 13
1116 #define STM_ISR_DMA4_CHANNEL1_POS 14
1117 #define STM_ISR_DMA5_CHANNEL1_POS 15
1118 #define STM_ISR_DMA6_CHANNEL1_POS 16
1119 #define STM_ISR_DMA7_CHANNEL1_POS 17
1120 #define STM_ISR_ADC1_POS 18
1121 #define STM_ISR_USB_HP_POS 19
1122 #define STM_ISR_USB_LP_POS 20
1123 #define STM_ISR_DAC_POS 21
1124 #define STM_ISR_COMP_POS 22
1125 #define STM_ISR_EXTI9_5_POS 23
1126 #define STM_ISR_LCD_POS 24
1127 #define STM_ISR_TIM9_POS 25
1128 #define STM_ISR_TIM10_POS 26
1129 #define STM_ISR_TIM11_POS 27
1130 #define STM_ISR_TIM2_POS 28
1131 #define STM_ISR_TIM3_POS 29
1132 #define STM_ISR_TIM4_POS 30
1133 #define STM_ISR_I2C1_EV_POS 31
1134 #define STM_ISR_I2C1_ER_POS 32
1135 #define STM_ISR_I2C2_EV_POS 33
1136 #define STM_ISR_I2C2_ER_POS 34
1137 #define STM_ISR_SPI1_POS 35
1138 #define STM_ISR_SPI2_POS 36
1139 #define STM_ISR_USART1_POS 37
1140 #define STM_ISR_USART2_POS 38
1141 #define STM_ISR_USART3_POS 39
1142 #define STM_ISR_EXTI15_10_POS 40
1143 #define STM_ISR_RTC_ALARM_POS 41
1144 #define STM_ISR_USB_FS_WKUP_POS 42
1145 #define STM_ISR_TIM6_POS 43
1146 #define STM_ISR_TIM7_POS 44
1151 vuint32_t exticr[4];
1154 extern struct stm_syscfg stm_syscfg;
1156 #define STM_SYSCFG_MEMRMP_MEM_MODE 0
1157 #define STM_SYSCFG_MEMRMP_MEM_MODE_MAIN_FLASH 0
1158 #define STM_SYSCFG_MEMRMP_MEM_MODE_SYSTEM_FLASH 1
1159 #define STM_SYSCFG_MEMRMP_MEM_MODE_SRAM 3
1160 #define STM_SYSCFG_MEMRMP_MEM_MODE_MASK 3
1162 #define STM_SYSCFG_PMC_USB_PU 0
1164 #define STM_SYSCFG_EXTICR_PA 0
1165 #define STM_SYSCFG_EXTICR_PB 1
1166 #define STM_SYSCFG_EXTICR_PC 2
1167 #define STM_SYSCFG_EXTICR_PD 3
1168 #define STM_SYSCFG_EXTICR_PE 4
1169 #define STM_SYSCFG_EXTICR_PH 5
1172 stm_exticr_set(struct stm_gpio *gpio, int pin) {
1173 uint8_t reg = pin >> 2;
1174 uint8_t shift = (pin & 3) << 2;
1178 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN);
1180 if (gpio == &stm_gpioa)
1181 val = STM_SYSCFG_EXTICR_PA;
1182 else if (gpio == &stm_gpiob)
1183 val = STM_SYSCFG_EXTICR_PB;
1184 else if (gpio == &stm_gpioc)
1185 val = STM_SYSCFG_EXTICR_PC;
1186 else if (gpio == &stm_gpiod)
1187 val = STM_SYSCFG_EXTICR_PD;
1188 else if (gpio == &stm_gpioe)
1189 val = STM_SYSCFG_EXTICR_PE;
1191 stm_syscfg.exticr[reg] = (stm_syscfg.exticr[reg] & ~(0xf << shift)) | val << shift;
1195 struct stm_dma_channel {
1203 #define STM_NUM_DMA 7
1208 struct stm_dma_channel channel[STM_NUM_DMA];
1211 extern struct stm_dma stm_dma;
1213 /* DMA channels go from 1 to 7, instead of 0 to 6 (sigh)
1216 #define STM_DMA_INDEX(channel) ((channel) - 1)
1218 #define STM_DMA_ISR(index) ((index) << 2)
1219 #define STM_DMA_ISR_MASK 0xf
1220 #define STM_DMA_ISR_TEIF 3
1221 #define STM_DMA_ISR_HTIF 2
1222 #define STM_DMA_ISR_TCIF 1
1223 #define STM_DMA_ISR_GIF 0
1225 #define STM_DMA_IFCR(index) ((index) << 2)
1226 #define STM_DMA_IFCR_MASK 0xf
1227 #define STM_DMA_IFCR_CTEIF 3
1228 #define STM_DMA_IFCR_CHTIF 2
1229 #define STM_DMA_IFCR_CTCIF 1
1230 #define STM_DMA_IFCR_CGIF 0
1232 #define STM_DMA_CCR_MEM2MEM (14)
1234 #define STM_DMA_CCR_PL (12)
1235 #define STM_DMA_CCR_PL_LOW (0)
1236 #define STM_DMA_CCR_PL_MEDIUM (1)
1237 #define STM_DMA_CCR_PL_HIGH (2)
1238 #define STM_DMA_CCR_PL_VERY_HIGH (3)
1239 #define STM_DMA_CCR_PL_MASK (3)
1241 #define STM_DMA_CCR_MSIZE (10)
1242 #define STM_DMA_CCR_MSIZE_8 (0)
1243 #define STM_DMA_CCR_MSIZE_16 (1)
1244 #define STM_DMA_CCR_MSIZE_32 (2)
1245 #define STM_DMA_CCR_MSIZE_MASK (3)
1247 #define STM_DMA_CCR_PSIZE (8)
1248 #define STM_DMA_CCR_PSIZE_8 (0)
1249 #define STM_DMA_CCR_PSIZE_16 (1)
1250 #define STM_DMA_CCR_PSIZE_32 (2)
1251 #define STM_DMA_CCR_PSIZE_MASK (3)
1253 #define STM_DMA_CCR_MINC (7)
1254 #define STM_DMA_CCR_PINC (6)
1255 #define STM_DMA_CCR_CIRC (5)
1256 #define STM_DMA_CCR_DIR (4)
1257 #define STM_DMA_CCR_DIR_PER_TO_MEM 0
1258 #define STM_DMA_CCR_DIR_MEM_TO_PER 1
1259 #define STM_DMA_CCR_TEIE (3)
1260 #define STM_DMA_CCR_HTIE (2)
1261 #define STM_DMA_CCR_TCIE (1)
1262 #define STM_DMA_CCR_EN (0)
1264 #define STM_DMA_CHANNEL_ADC1 1
1265 #define STM_DMA_CHANNEL_SPI1_RX 2
1266 #define STM_DMA_CHANNEL_SPI1_TX 3
1267 #define STM_DMA_CHANNEL_SPI2_RX 4
1268 #define STM_DMA_CHANNEL_SPI2_TX 5
1269 #define STM_DMA_CHANNEL_USART3_TX 2
1270 #define STM_DMA_CHANNEL_USART3_RX 3
1271 #define STM_DMA_CHANNEL_USART1_TX 4
1272 #define STM_DMA_CHANNEL_USART1_RX 5
1273 #define STM_DMA_CHANNEL_USART2_RX 6
1274 #define STM_DMA_CHANNEL_USART2_TX 7
1275 #define STM_DMA_CHANNEL_I2C2_TX 4
1276 #define STM_DMA_CHANNEL_I2C2_RX 5
1277 #define STM_DMA_CHANNEL_I2C1_TX 6
1278 #define STM_DMA_CHANNEL_I2C1_RX 7
1279 #define STM_DMA_CHANNEL_TIM2_CH3 1
1280 #define STM_DMA_CHANNEL_TIM2_UP 2
1281 #define STM_DMA_CHANNEL_TIM2_CH1 5
1282 #define STM_DMA_CHANNEL_TIM2_CH2 7
1283 #define STM_DMA_CHANNEL_TIM2_CH4 7
1284 #define STM_DMA_CHANNEL_TIM3_CH3 2
1285 #define STM_DMA_CHANNEL_TIM3_CH4 3
1286 #define STM_DMA_CHANNEL_TIM3_UP 3
1287 #define STM_DMA_CHANNEL_TIM3_CH1 6
1288 #define STM_DMA_CHANNEL_TIM3_TRIG 6
1289 #define STM_DMA_CHANNEL_TIM4_CH1 1
1290 #define STM_DMA_CHANNEL_TIM4_CH2 4
1291 #define STM_DMA_CHANNEL_TIM4_CH3 5
1292 #define STM_DMA_CHANNEL_TIM4_UP 7
1293 #define STM_DMA_CHANNEL_TIM6_UP_DA 2
1294 #define STM_DMA_CHANNEL_C_CHANNEL1 2
1295 #define STM_DMA_CHANNEL_TIM7_UP_DA 3
1296 #define STM_DMA_CHANNEL_C_CHANNEL2 3
1299 * Only spi channel 1 and 2 can use DMA
1301 #define STM_NUM_SPI 2
1313 extern struct stm_spi stm_spi1, stm_spi2, stm_spi3;
1315 /* SPI channels go from 1 to 3, instead of 0 to 2 (sigh)
1318 #define STM_SPI_INDEX(channel) ((channel) - 1)
1320 #define STM_SPI_CR1_BIDIMODE 15
1321 #define STM_SPI_CR1_BIDIOE 14
1322 #define STM_SPI_CR1_CRCEN 13
1323 #define STM_SPI_CR1_CRCNEXT 12
1324 #define STM_SPI_CR1_DFF 11
1325 #define STM_SPI_CR1_RXONLY 10
1326 #define STM_SPI_CR1_SSM 9
1327 #define STM_SPI_CR1_SSI 8
1328 #define STM_SPI_CR1_LSBFIRST 7
1329 #define STM_SPI_CR1_SPE 6
1330 #define STM_SPI_CR1_BR 3
1331 #define STM_SPI_CR1_BR_PCLK_2 0
1332 #define STM_SPI_CR1_BR_PCLK_4 1
1333 #define STM_SPI_CR1_BR_PCLK_8 2
1334 #define STM_SPI_CR1_BR_PCLK_16 3
1335 #define STM_SPI_CR1_BR_PCLK_32 4
1336 #define STM_SPI_CR1_BR_PCLK_64 5
1337 #define STM_SPI_CR1_BR_PCLK_128 6
1338 #define STM_SPI_CR1_BR_PCLK_256 7
1339 #define STM_SPI_CR1_BR_MASK 7
1341 #define STM_SPI_CR1_MSTR 2
1342 #define STM_SPI_CR1_CPOL 1
1343 #define STM_SPI_CR1_CPHA 0
1345 #define STM_SPI_CR2_TXEIE 7
1346 #define STM_SPI_CR2_RXNEIE 6
1347 #define STM_SPI_CR2_ERRIE 5
1348 #define STM_SPI_CR2_SSOE 2
1349 #define STM_SPI_CR2_TXDMAEN 1
1350 #define STM_SPI_CR2_RXDMAEN 0
1352 #define STM_SPI_SR_BSY 7
1353 #define STM_SPI_SR_OVR 6
1354 #define STM_SPI_SR_MODF 5
1355 #define STM_SPI_SR_CRCERR 4
1356 #define STM_SPI_SR_TXE 1
1357 #define STM_SPI_SR_RXNE 0
1383 uint8_t reserved[0x300 - 0x5c];
1388 extern struct stm_adc stm_adc;
1390 #define STM_ADC_SR_JCNR 9
1391 #define STM_ADC_SR_RCNR 8
1392 #define STM_ADC_SR_ADONS 6
1393 #define STM_ADC_SR_OVR 5
1394 #define STM_ADC_SR_STRT 4
1395 #define STM_ADC_SR_JSTRT 3
1396 #define STM_ADC_SR_JEOC 2
1397 #define STM_ADC_SR_EOC 1
1398 #define STM_ADC_SR_AWD 0
1400 #define STM_ADC_CR1_OVRIE 26
1401 #define STM_ADC_CR1_RES 24
1402 #define STM_ADC_CR1_RES_12 0
1403 #define STM_ADC_CR1_RES_10 1
1404 #define STM_ADC_CR1_RES_8 2
1405 #define STM_ADC_CR1_RES_6 3
1406 #define STM_ADC_CR1_RES_MASK 3
1407 #define STM_ADC_CR1_AWDEN 23
1408 #define STM_ADC_CR1_JAWDEN 22
1409 #define STM_ADC_CR1_PDI 17
1410 #define STM_ADC_CR1_PDD 16
1411 #define STM_ADC_CR1_DISCNUM 13
1412 #define STM_ADC_CR1_DISCNUM_1 0
1413 #define STM_ADC_CR1_DISCNUM_2 1
1414 #define STM_ADC_CR1_DISCNUM_3 2
1415 #define STM_ADC_CR1_DISCNUM_4 3
1416 #define STM_ADC_CR1_DISCNUM_5 4
1417 #define STM_ADC_CR1_DISCNUM_6 5
1418 #define STM_ADC_CR1_DISCNUM_7 6
1419 #define STM_ADC_CR1_DISCNUM_8 7
1420 #define STM_ADC_CR1_DISCNUM_MASK 7
1421 #define STM_ADC_CR1_JDISCEN 12
1422 #define STM_ADC_CR1_DISCEN 11
1423 #define STM_ADC_CR1_JAUTO 10
1424 #define STM_ADC_CR1_AWDSGL 9
1425 #define STM_ADC_CR1_SCAN 8
1426 #define STM_ADC_CR1_JEOCIE 7
1427 #define STM_ADC_CR1_AWDIE 6
1428 #define STM_ADC_CR1_EOCIE 5
1429 #define STM_ADC_CR1_AWDCH 0
1430 #define STM_ADC_CR1_AWDCH_MASK 0x1f
1432 #define STM_ADC_CR2_SWSTART 30
1433 #define STM_ADC_CR2_EXTEN 28
1434 #define STM_ADC_CR2_EXTEN_DISABLE 0
1435 #define STM_ADC_CR2_EXTEN_RISING 1
1436 #define STM_ADC_CR2_EXTEN_FALLING 2
1437 #define STM_ADC_CR2_EXTEN_BOTH 3
1438 #define STM_ADC_CR2_EXTEN_MASK 3
1439 #define STM_ADC_CR2_EXTSEL 24
1440 #define STM_ADC_CR2_EXTSEL_TIM9_CC2 0
1441 #define STM_ADC_CR2_EXTSEL_TIM9_TRGO 1
1442 #define STM_ADC_CR2_EXTSEL_TIM2_CC3 2
1443 #define STM_ADC_CR2_EXTSEL_TIM2_CC2 3
1444 #define STM_ADC_CR2_EXTSEL_TIM3_TRGO 4
1445 #define STM_ADC_CR2_EXTSEL_TIM4_CC4 5
1446 #define STM_ADC_CR2_EXTSEL_TIM2_TRGO 6
1447 #define STM_ADC_CR2_EXTSEL_TIM3_CC1 7
1448 #define STM_ADC_CR2_EXTSEL_TIM3_CC3 8
1449 #define STM_ADC_CR2_EXTSEL_TIM4_TRGO 9
1450 #define STM_ADC_CR2_EXTSEL_TIM6_TRGO 10
1451 #define STM_ADC_CR2_EXTSEL_EXTI_11 15
1452 #define STM_ADC_CR2_EXTSEL_MASK 15
1453 #define STM_ADC_CR2_JWSTART 22
1454 #define STM_ADC_CR2_JEXTEN 20
1455 #define STM_ADC_CR2_JEXTEN_DISABLE 0
1456 #define STM_ADC_CR2_JEXTEN_RISING 1
1457 #define STM_ADC_CR2_JEXTEN_FALLING 2
1458 #define STM_ADC_CR2_JEXTEN_BOTH 3
1459 #define STM_ADC_CR2_JEXTEN_MASK 3
1460 #define STM_ADC_CR2_JEXTSEL 16
1461 #define STM_ADC_CR2_JEXTSEL_TIM9_CC1 0
1462 #define STM_ADC_CR2_JEXTSEL_TIM9_TRGO 1
1463 #define STM_ADC_CR2_JEXTSEL_TIM2_TRGO 2
1464 #define STM_ADC_CR2_JEXTSEL_TIM2_CC1 3
1465 #define STM_ADC_CR2_JEXTSEL_TIM3_CC4 4
1466 #define STM_ADC_CR2_JEXTSEL_TIM4_TRGO 5
1467 #define STM_ADC_CR2_JEXTSEL_TIM4_CC1 6
1468 #define STM_ADC_CR2_JEXTSEL_TIM4_CC2 7
1469 #define STM_ADC_CR2_JEXTSEL_TIM4_CC3 8
1470 #define STM_ADC_CR2_JEXTSEL_TIM10_CC1 9
1471 #define STM_ADC_CR2_JEXTSEL_TIM7_TRGO 10
1472 #define STM_ADC_CR2_JEXTSEL_EXTI_15 15
1473 #define STM_ADC_CR2_JEXTSEL_MASK 15
1474 #define STM_ADC_CR2_ALIGN 11
1475 #define STM_ADC_CR2_EOCS 10
1476 #define STM_ADC_CR2_DDS 9
1477 #define STM_ADC_CR2_DMA 8
1478 #define STM_ADC_CR2_DELS 4
1479 #define STM_ADC_CR2_DELS_NONE 0
1480 #define STM_ADC_CR2_DELS_UNTIL_READ 1
1481 #define STM_ADC_CR2_DELS_7 2
1482 #define STM_ADC_CR2_DELS_15 3
1483 #define STM_ADC_CR2_DELS_31 4
1484 #define STM_ADC_CR2_DELS_63 5
1485 #define STM_ADC_CR2_DELS_127 6
1486 #define STM_ADC_CR2_DELS_255 7
1487 #define STM_ADC_CR2_DELS_MASK 7
1488 #define STM_ADC_CR2_CONT 1
1489 #define STM_ADC_CR2_ADON 0
1491 #define STM_ADC_CCR_TSVREFE 23
1492 #define STM_ADC_CCR_ADCPRE 16
1493 #define STM_ADC_CCR_ADCPRE_HSI_1 0
1494 #define STM_ADC_CCR_ADCPRE_HSI_2 1
1495 #define STM_ADC_CCR_ADCPRE_HSI_4 2
1496 #define STM_ADC_CCR_ADCPRE_MASK 3
1498 struct stm_temp_cal {
1500 uint16_t ts_cal_cold;
1502 uint16_t ts_cal_hot;
1505 extern struct stm_temp_cal stm_temp_cal;
1507 #define stm_temp_cal_cold 25
1508 #define stm_temp_cal_hot 110
1510 struct stm_dbg_mcu {
1514 extern struct stm_dbg_mcu stm_dbg_mcu;
1516 static inline uint16_t
1518 return stm_dbg_mcu.idcode & 0xfff;
1521 struct stm_flash_size {
1525 extern struct stm_flash_size stm_flash_size_medium;
1526 extern struct stm_flash_size stm_flash_size_large;
1528 /* Returns flash size in bytes */
1530 stm_flash_size(void);
1532 struct stm_device_id {
1538 extern struct stm_device_id stm_device_id;
1540 #define STM_NUM_I2C 2
1542 #define STM_I2C_INDEX(channel) ((channel) - 1)
1556 extern struct stm_i2c stm_i2c1, stm_i2c2;
1558 #define STM_I2C_CR1_SWRST 15
1559 #define STM_I2C_CR1_ALERT 13
1560 #define STM_I2C_CR1_PEC 12
1561 #define STM_I2C_CR1_POS 11
1562 #define STM_I2C_CR1_ACK 10
1563 #define STM_I2C_CR1_STOP 9
1564 #define STM_I2C_CR1_START 8
1565 #define STM_I2C_CR1_NOSTRETCH 7
1566 #define STM_I2C_CR1_ENGC 6
1567 #define STM_I2C_CR1_ENPEC 5
1568 #define STM_I2C_CR1_ENARP 4
1569 #define STM_I2C_CR1_SMBTYPE 3
1570 #define STM_I2C_CR1_SMBUS 1
1571 #define STM_I2C_CR1_PE 0
1573 #define STM_I2C_CR2_LAST 12
1574 #define STM_I2C_CR2_DMAEN 11
1575 #define STM_I2C_CR2_ITBUFEN 10
1576 #define STM_I2C_CR2_ITEVTEN 9
1577 #define STM_I2C_CR2_ITERREN 8
1578 #define STM_I2C_CR2_FREQ 0
1579 #define STM_I2C_CR2_FREQ_2_MHZ 2
1580 #define STM_I2C_CR2_FREQ_4_MHZ 4
1581 #define STM_I2C_CR2_FREQ_8_MHZ 8
1582 #define STM_I2C_CR2_FREQ_16_MHZ 16
1583 #define STM_I2C_CR2_FREQ_32_MHZ 32
1584 #define STM_I2C_CR2_FREQ_MASK 0x3f
1586 #define STM_I2C_SR1_SMBALERT 15
1587 #define STM_I2C_SR1_TIMEOUT 14
1588 #define STM_I2C_SR1_PECERR 12
1589 #define STM_I2C_SR1_OVR 11
1590 #define STM_I2C_SR1_AF 10
1591 #define STM_I2C_SR1_ARLO 9
1592 #define STM_I2C_SR1_BERR 8
1593 #define STM_I2C_SR1_TXE 7
1594 #define STM_I2C_SR1_RXNE 6
1595 #define STM_I2C_SR1_STOPF 4
1596 #define STM_I2C_SR1_ADD10 3
1597 #define STM_I2C_SR1_BTF 2
1598 #define STM_I2C_SR1_ADDR 1
1599 #define STM_I2C_SR1_SB 0
1601 #define STM_I2C_SR2_PEC 8
1602 #define STM_I2C_SR2_PEC_MASK 0xff00
1603 #define STM_I2C_SR2_DUALF 7
1604 #define STM_I2C_SR2_SMBHOST 6
1605 #define STM_I2C_SR2_SMBDEFAULT 5
1606 #define STM_I2C_SR2_GENCALL 4
1607 #define STM_I2C_SR2_TRA 2
1608 #define STM_I2C_SR2_BUSY 1
1609 #define STM_I2C_SR2_MSL 0
1611 #define STM_I2C_CCR_FS 15
1612 #define STM_I2C_CCR_DUTY 14
1613 #define STM_I2C_CCR_CCR 0
1614 #define STM_I2C_CCR_MASK 0x7ff
1632 uint32_t reserved_30;
1638 uint32_t reserved_44;
1642 uint32_t reserved_50;
1645 extern struct stm_tim234 stm_tim2, stm_tim3, stm_tim4;
1647 #define STM_TIM234_CR1_CKD 8
1648 #define STM_TIM234_CR1_CKD_1 0
1649 #define STM_TIM234_CR1_CKD_2 1
1650 #define STM_TIM234_CR1_CKD_4 2
1651 #define STM_TIM234_CR1_CKD_MASK 3
1652 #define STM_TIM234_CR1_ARPE 7
1653 #define STM_TIM234_CR1_CMS 5
1654 #define STM_TIM234_CR1_CMS_EDGE 0
1655 #define STM_TIM234_CR1_CMS_CENTER_1 1
1656 #define STM_TIM234_CR1_CMS_CENTER_2 2
1657 #define STM_TIM234_CR1_CMS_CENTER_3 3
1658 #define STM_TIM234_CR1_CMS_MASK 3
1659 #define STM_TIM234_CR1_DIR 4
1660 #define STM_TIM234_CR1_DIR_UP 0
1661 #define STM_TIM234_CR1_DIR_DOWN 1
1662 #define STM_TIM234_CR1_OPM 3
1663 #define STM_TIM234_CR1_URS 2
1664 #define STM_TIM234_CR1_UDIS 1
1665 #define STM_TIM234_CR1_CEN 0
1667 #define STM_TIM234_CR2_TI1S 7
1668 #define STM_TIM234_CR2_MMS 4
1669 #define STM_TIM234_CR2_MMS_RESET 0
1670 #define STM_TIM234_CR2_MMS_ENABLE 1
1671 #define STM_TIM234_CR2_MMS_UPDATE 2
1672 #define STM_TIM234_CR2_MMS_COMPARE_PULSE 3
1673 #define STM_TIM234_CR2_MMS_COMPARE_OC1REF 4
1674 #define STM_TIM234_CR2_MMS_COMPARE_OC2REF 5
1675 #define STM_TIM234_CR2_MMS_COMPARE_OC3REF 6
1676 #define STM_TIM234_CR2_MMS_COMPARE_OC4REF 7
1677 #define STM_TIM234_CR2_MMS_MASK 7
1678 #define STM_TIM234_CR2_CCDS 3
1680 #define STM_TIM234_SMCR_ETP 15
1681 #define STM_TIM234_SMCR_ECE 14
1682 #define STM_TIM234_SMCR_ETPS 12
1683 #define STM_TIM234_SMCR_ETPS_OFF 0
1684 #define STM_TIM234_SMCR_ETPS_DIV_2 1
1685 #define STM_TIM234_SMCR_ETPS_DIV_4 2
1686 #define STM_TIM234_SMCR_ETPS_DIV_8 3
1687 #define STM_TIM234_SMCR_ETPS_MASK 3
1688 #define STM_TIM234_SMCR_ETF 8
1689 #define STM_TIM234_SMCR_ETF_NONE 0
1690 #define STM_TIM234_SMCR_ETF_INT_N_2 1
1691 #define STM_TIM234_SMCR_ETF_INT_N_4 2
1692 #define STM_TIM234_SMCR_ETF_INT_N_8 3
1693 #define STM_TIM234_SMCR_ETF_DTS_2_N_6 4
1694 #define STM_TIM234_SMCR_ETF_DTS_2_N_8 5
1695 #define STM_TIM234_SMCR_ETF_DTS_4_N_6 6
1696 #define STM_TIM234_SMCR_ETF_DTS_4_N_8 7
1697 #define STM_TIM234_SMCR_ETF_DTS_8_N_6 8
1698 #define STM_TIM234_SMCR_ETF_DTS_8_N_8 9
1699 #define STM_TIM234_SMCR_ETF_DTS_16_N_5 10
1700 #define STM_TIM234_SMCR_ETF_DTS_16_N_6 11
1701 #define STM_TIM234_SMCR_ETF_DTS_16_N_8 12
1702 #define STM_TIM234_SMCR_ETF_DTS_32_N_5 13
1703 #define STM_TIM234_SMCR_ETF_DTS_32_N_6 14
1704 #define STM_TIM234_SMCR_ETF_DTS_32_N_8 15
1705 #define STM_TIM234_SMCR_ETF_MASK 15
1706 #define STM_TIM234_SMCR_MSM 7
1707 #define STM_TIM234_SMCR_TS 4
1708 #define STM_TIM234_SMCR_TS_ITR0 0
1709 #define STM_TIM234_SMCR_TS_ITR1 1
1710 #define STM_TIM234_SMCR_TS_ITR2 2
1711 #define STM_TIM234_SMCR_TS_ITR3 3
1712 #define STM_TIM234_SMCR_TS_TI1F_ED 4
1713 #define STM_TIM234_SMCR_TS_TI1FP1 5
1714 #define STM_TIM234_SMCR_TS_TI2FP2 6
1715 #define STM_TIM234_SMCR_TS_ETRF 7
1716 #define STM_TIM234_SMCR_TS_MASK 7
1717 #define STM_TIM234_SMCR_OCCS 3
1718 #define STM_TIM234_SMCR_SMS 0
1719 #define STM_TIM234_SMCR_SMS_DISABLE 0
1720 #define STM_TIM234_SMCR_SMS_ENCODER_MODE_1 1
1721 #define STM_TIM234_SMCR_SMS_ENCODER_MODE_2 2
1722 #define STM_TIM234_SMCR_SMS_ENCODER_MODE_3 3
1723 #define STM_TIM234_SMCR_SMS_RESET_MODE 4
1724 #define STM_TIM234_SMCR_SMS_GATED_MODE 5
1725 #define STM_TIM234_SMCR_SMS_TRIGGER_MODE 6
1726 #define STM_TIM234_SMCR_SMS_EXTERNAL_CLOCK 7
1727 #define STM_TIM234_SMCR_SMS_MASK 7
1729 #define STM_TIM234_SR_CC4OF 12
1730 #define STM_TIM234_SR_CC3OF 11
1731 #define STM_TIM234_SR_CC2OF 10
1732 #define STM_TIM234_SR_CC1OF 9
1733 #define STM_TIM234_SR_TIF 6
1734 #define STM_TIM234_SR_CC4IF 4
1735 #define STM_TIM234_SR_CC3IF 3
1736 #define STM_TIM234_SR_CC2IF 2
1737 #define STM_TIM234_SR_CC1IF 1
1738 #define STM_TIM234_SR_UIF 0
1740 #define STM_TIM234_EGR_TG 6
1741 #define STM_TIM234_EGR_CC4G 4
1742 #define STM_TIM234_EGR_CC3G 3
1743 #define STM_TIM234_EGR_CC2G 2
1744 #define STM_TIM234_EGR_CC1G 1
1745 #define STM_TIM234_EGR_UG 0
1747 #define STM_TIM234_CCMR1_OC2CE 15
1748 #define STM_TIM234_CCMR1_OC2M 12
1749 #define STM_TIM234_CCMR1_OC2M_FROZEN 0
1750 #define STM_TIM234_CCMR1_OC2M_SET_HIGH_ON_MATCH 1
1751 #define STM_TIM234_CCMR1_OC2M_SET_LOW_ON_MATCH 2
1752 #define STM_TIM234_CCMR1_OC2M_TOGGLE 3
1753 #define STM_TIM234_CCMR1_OC2M_FORCE_LOW 4
1754 #define STM_TIM234_CCMR1_OC2M_FORCE_HIGH 5
1755 #define STM_TIM234_CCMR1_OC2M_PWM_MODE_1 6
1756 #define STM_TIM234_CCMR1_OC2M_PWM_MODE_2 7
1757 #define STM_TIM234_CCMR1_OC2M_MASK 7
1758 #define STM_TIM234_CCMR1_OC2PE 11
1759 #define STM_TIM234_CCMR1_OC2FE 10
1760 #define STM_TIM234_CCMR1_CC2S 8
1761 #define STM_TIM234_CCMR1_CC2S_OUTPUT 0
1762 #define STM_TIM234_CCMR1_CC2S_INPUT_TI2 1
1763 #define STM_TIM234_CCMR1_CC2S_INPUT_TI1 2
1764 #define STM_TIM234_CCMR1_CC2S_INPUT_TRC 3
1765 #define STM_TIM234_CCMR1_CC2S_MASK 3
1767 #define STM_TIM234_CCMR1_OC1CE 7
1768 #define STM_TIM234_CCMR1_OC1M 4
1769 #define STM_TIM234_CCMR1_OC1M_FROZEN 0
1770 #define STM_TIM234_CCMR1_OC1M_SET_HIGH_ON_MATCH 1
1771 #define STM_TIM234_CCMR1_OC1M_SET_LOW_ON_MATCH 2
1772 #define STM_TIM234_CCMR1_OC1M_TOGGLE 3
1773 #define STM_TIM234_CCMR1_OC1M_FORCE_LOW 4
1774 #define STM_TIM234_CCMR1_OC1M_FORCE_HIGH 5
1775 #define STM_TIM234_CCMR1_OC1M_PWM_MODE_1 6
1776 #define STM_TIM234_CCMR1_OC1M_PWM_MODE_2 7
1777 #define STM_TIM234_CCMR1_OC1M_MASK 7
1778 #define STM_TIM234_CCMR1_OC1PE 3
1779 #define STM_TIM234_CCMR1_OC1FE 2
1780 #define STM_TIM234_CCMR1_CC1S 0
1781 #define STM_TIM234_CCMR1_CC1S_OUTPUT 0
1782 #define STM_TIM234_CCMR1_CC1S_INPUT_TI1 1
1783 #define STM_TIM234_CCMR1_CC1S_INPUT_TI2 2
1784 #define STM_TIM234_CCMR1_CC1S_INPUT_TRC 3
1785 #define STM_TIM234_CCMR1_CC1S_MASK 3
1787 #define STM_TIM234_CCMR2_OC4CE 15
1788 #define STM_TIM234_CCMR2_OC4M 12
1789 #define STM_TIM234_CCMR2_OC4M_FROZEN 0
1790 #define STM_TIM234_CCMR2_OC4M_SET_HIGH_ON_MATCH 1
1791 #define STM_TIM234_CCMR2_OC4M_SET_LOW_ON_MATCH 2
1792 #define STM_TIM234_CCMR2_OC4M_TOGGLE 3
1793 #define STM_TIM234_CCMR2_OC4M_FORCE_LOW 4
1794 #define STM_TIM234_CCMR2_OC4M_FORCE_HIGH 5
1795 #define STM_TIM234_CCMR2_OC4M_PWM_MODE_1 6
1796 #define STM_TIM234_CCMR2_OC4M_PWM_MODE_2 7
1797 #define STM_TIM234_CCMR2_OC4M_MASK 7
1798 #define STM_TIM234_CCMR2_OC4PE 11
1799 #define STM_TIM234_CCMR2_OC4FE 10
1800 #define STM_TIM234_CCMR2_CC4S 8
1801 #define STM_TIM234_CCMR2_CC4S_OUTPUT 0
1802 #define STM_TIM234_CCMR2_CC4S_INPUT_TI4 1
1803 #define STM_TIM234_CCMR2_CC4S_INPUT_TI3 2
1804 #define STM_TIM234_CCMR2_CC4S_INPUT_TRC 3
1805 #define STM_TIM234_CCMR2_CC4S_MASK 3
1807 #define STM_TIM234_CCMR2_OC3CE 7
1808 #define STM_TIM234_CCMR2_OC3M 4
1809 #define STM_TIM234_CCMR2_OC3M_FROZEN 0
1810 #define STM_TIM234_CCMR2_OC3M_SET_HIGH_ON_MATCH 1
1811 #define STM_TIM234_CCMR2_OC3M_SET_LOW_ON_MATCH 2
1812 #define STM_TIM234_CCMR2_OC3M_TOGGLE 3
1813 #define STM_TIM234_CCMR2_OC3M_FORCE_LOW 4
1814 #define STM_TIM234_CCMR2_OC3M_FORCE_HIGH 5
1815 #define STM_TIM234_CCMR2_OC3M_PWM_MODE_1 6
1816 #define STM_TIM234_CCMR2_OC3M_PWM_MODE_2 7
1817 #define STM_TIM234_CCMR2_OC3M_MASK 7
1818 #define STM_TIM234_CCMR2_OC3PE 3
1819 #define STM_TIM234_CCMR2_OC3FE 2
1820 #define STM_TIM234_CCMR2_CC3S 0
1821 #define STM_TIM234_CCMR2_CC3S_OUTPUT 0
1822 #define STM_TIM234_CCMR2_CC3S_INPUT_TI3 1
1823 #define STM_TIM234_CCMR2_CC3S_INPUT_TI4 2
1824 #define STM_TIM234_CCMR2_CC3S_INPUT_TRC 3
1825 #define STM_TIM234_CCMR2_CC3S_MASK 3
1827 #define STM_TIM234_CCER_CC4NP 15
1828 #define STM_TIM234_CCER_CC4P 13
1829 #define STM_TIM234_CCER_CC4E 12
1830 #define STM_TIM234_CCER_CC3NP 11
1831 #define STM_TIM234_CCER_CC3P 9
1832 #define STM_TIM234_CCER_CC3E 8
1833 #define STM_TIM234_CCER_CC2NP 7
1834 #define STM_TIM234_CCER_CC2P 5
1835 #define STM_TIM234_CCER_CC2E 4
1836 #define STM_TIM234_CCER_CC1NP 3
1837 #define STM_TIM234_CCER_CC1P 1
1838 #define STM_TIM234_CCER_CC1E 0
1842 uint8_t reserved_20[0x40 - 0x20];
1850 #define STM_USB_EPR_CTR_RX 15
1851 #define STM_USB_EPR_CTR_RX_WRITE_INVARIANT 1
1852 #define STM_USB_EPR_DTOG_RX 14
1853 #define STM_USB_EPR_DTOG_RX_WRITE_INVARIANT 0
1854 #define STM_USB_EPR_STAT_RX 12
1855 #define STM_USB_EPR_STAT_RX_DISABLED 0
1856 #define STM_USB_EPR_STAT_RX_STALL 1
1857 #define STM_USB_EPR_STAT_RX_NAK 2
1858 #define STM_USB_EPR_STAT_RX_VALID 3
1859 #define STM_USB_EPR_STAT_RX_MASK 3
1860 #define STM_USB_EPR_STAT_RX_WRITE_INVARIANT 0
1861 #define STM_USB_EPR_SETUP 11
1862 #define STM_USB_EPR_EP_TYPE 9
1863 #define STM_USB_EPR_EP_TYPE_BULK 0
1864 #define STM_USB_EPR_EP_TYPE_CONTROL 1
1865 #define STM_USB_EPR_EP_TYPE_ISO 2
1866 #define STM_USB_EPR_EP_TYPE_INTERRUPT 3
1867 #define STM_USB_EPR_EP_TYPE_MASK 3
1868 #define STM_USB_EPR_EP_KIND 8
1869 #define STM_USB_EPR_EP_KIND_DBL_BUF 1 /* Bulk */
1870 #define STM_USB_EPR_EP_KIND_STATUS_OUT 1 /* Control */
1871 #define STM_USB_EPR_CTR_TX 7
1872 #define STM_USB_CTR_TX_WRITE_INVARIANT 1
1873 #define STM_USB_EPR_DTOG_TX 6
1874 #define STM_USB_EPR_DTOG_TX_WRITE_INVARIANT 0
1875 #define STM_USB_EPR_STAT_TX 4
1876 #define STM_USB_EPR_STAT_TX_DISABLED 0
1877 #define STM_USB_EPR_STAT_TX_STALL 1
1878 #define STM_USB_EPR_STAT_TX_NAK 2
1879 #define STM_USB_EPR_STAT_TX_VALID 3
1880 #define STM_USB_EPR_STAT_TX_WRITE_INVARIANT 0
1881 #define STM_USB_EPR_STAT_TX_MASK 3
1882 #define STM_USB_EPR_EA 0
1883 #define STM_USB_EPR_EA_MASK 0xf
1885 #define STM_USB_CNTR_CTRM 15
1886 #define STM_USB_CNTR_PMAOVRM 14
1887 #define STM_USB_CNTR_ERRM 13
1888 #define STM_USB_CNTR_WKUPM 12
1889 #define STM_USB_CNTR_SUSPM 11
1890 #define STM_USB_CNTR_RESETM 10
1891 #define STM_USB_CNTR_SOFM 9
1892 #define STM_USB_CNTR_ESOFM 8
1893 #define STM_USB_CNTR_RESUME 4
1894 #define STM_USB_CNTR_FSUSP 3
1895 #define STM_USB_CNTR_LP_MODE 2
1896 #define STM_USB_CNTR_PDWN 1
1897 #define STM_USB_CNTR_FRES 0
1899 #define STM_USB_ISTR_CTR 15
1900 #define STM_USB_ISTR_PMAOVR 14
1901 #define STM_USB_ISTR_ERR 13
1902 #define STM_USB_ISTR_WKUP 12
1903 #define STM_USB_ISTR_SUSP 11
1904 #define STM_USB_ISTR_RESET 10
1905 #define STM_USB_ISTR_SOF 9
1906 #define STM_USB_ISTR_ESOF 8
1907 #define STM_USB_ISTR_DIR 4
1908 #define STM_USB_ISTR_EP_ID 0
1909 #define STM_USB_ISTR_EP_ID_MASK 0xf
1911 #define STM_USB_FNR_RXDP 15
1912 #define STM_USB_FNR_RXDM 14
1913 #define STM_USB_FNR_LCK 13
1914 #define STM_USB_FNR_LSOF 11
1915 #define STM_USB_FNR_LSOF_MASK 0x3
1916 #define STM_USB_FNR_FN 0
1917 #define STM_USB_FNR_FN_MASK 0x7ff
1919 #define STM_USB_DADDR_EF 7
1920 #define STM_USB_DADDR_ADD 0
1921 #define STM_USB_DADDR_ADD_MASK 0x7f
1923 extern struct stm_usb stm_usb;
1942 #define STM_USB_BDT_COUNT_RX_BL_SIZE 15
1943 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK 10
1944 #define STM_USB_BDT_COUNT_RX_NUM_BLOCK_MASK 0x1f
1945 #define STM_USB_BDT_COUNT_RX_COUNT_RX 0
1946 #define STM_USB_BDT_COUNT_RX_COUNT_RX_MASK 0x1ff
1948 #define STM_USB_BDT_SIZE 8
1950 extern uint8_t stm_usb_sram[];
1962 extern struct stm_exti stm_exti;
1964 #endif /* _STM32L_H_ */