2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 #include "ao_product.h"
23 #define USB_DEBUG_DATA 0
27 #define debug(format, args...) printf(format, ## args);
29 #define debug(format, args...)
33 #define debug_data(format, args...) printf(format, ## args);
35 #define debug_data(format, args...)
38 struct ao_task ao_usb_task;
41 uint8_t dir_type_recip;
48 static uint8_t ao_usb_ep0_state;
50 /* Pending EP0 IN data */
51 static const uint8_t *ao_usb_ep0_in_data; /* Remaining data */
52 static uint8_t ao_usb_ep0_in_len; /* Remaining amount */
54 /* Temp buffer for smaller EP0 in data */
55 static uint8_t ao_usb_ep0_in_buf[2];
57 /* Pending EP0 OUT data */
58 static uint8_t *ao_usb_ep0_out_data;
59 static uint8_t ao_usb_ep0_out_len;
62 * Objects allocated in special USB memory
65 /* Buffer description tables */
66 static union stm_usb_bdt *ao_usb_bdt;
67 /* USB address of end of allocated storage */
68 static uint16_t ao_usb_sram_addr;
70 /* Pointer to ep0 tx/rx buffers in USB memory */
71 static uint32_t *ao_usb_ep0_tx_buffer;
72 static uint32_t *ao_usb_ep0_rx_buffer;
74 /* Pointer to bulk data tx/rx buffers in USB memory */
75 static uint32_t *ao_usb_in_tx_buffer;
76 static uint32_t *ao_usb_out_rx_buffer;
78 /* System ram shadow of USB buffer; writing individual bytes is
79 * too much of a pain (sigh) */
80 static uint8_t ao_usb_tx_buffer[AO_USB_IN_SIZE];
81 static uint8_t ao_usb_tx_count;
83 static uint8_t ao_usb_rx_buffer[AO_USB_OUT_SIZE];
84 static uint8_t ao_usb_rx_count, ao_usb_rx_pos;
87 * End point register indices
90 #define AO_USB_CONTROL_EPR 0
91 #define AO_USB_INT_EPR 1
92 #define AO_USB_OUT_EPR 2
93 #define AO_USB_IN_EPR 3
95 /* Marks when we don't need to send an IN packet.
96 * This happens only when the last IN packet is not full,
97 * otherwise the host will expect to keep seeing packets.
98 * Send a zero-length packet as required
100 static uint8_t ao_usb_in_flushed;
102 /* Marks when we have delivered an IN packet to the hardware
103 * and it has not been received yet. ao_sleep on this address
104 * to wait for it to be delivered.
106 static uint8_t ao_usb_in_pending;
108 /* Marks when an OUT packet has been received by the hardware
109 * but not pulled to the shadow buffer.
111 static uint8_t ao_usb_out_avail;
112 static uint8_t ao_usb_running;
113 static uint8_t ao_usb_configuration;
114 static uint8_t ueienx_0;
116 #define AO_USB_EP0_GOT_RESET 1
117 #define AO_USB_EP0_GOT_SETUP 2
118 #define AO_USB_EP0_GOT_RX_DATA 4
119 #define AO_USB_EP0_GOT_TX_ACK 8
121 static uint8_t ao_usb_ep0_receive;
122 static uint8_t ao_usb_address;
123 static uint8_t ao_usb_address_pending;
125 static inline uint32_t set_toggle(uint32_t current_value,
127 uint32_t desired_value)
129 return (current_value ^ desired_value) & mask;
132 static inline uint32_t *ao_usb_packet_buffer_addr(uint16_t sram_addr)
134 return (uint32_t *) (stm_usb_sram + 2 * sram_addr);
137 static inline uint32_t ao_usb_epr_stat_rx(uint32_t epr) {
138 return (epr >> STM_USB_EPR_STAT_RX) & STM_USB_EPR_STAT_RX_MASK;
141 static inline uint32_t ao_usb_epr_stat_tx(uint32_t epr) {
142 return (epr >> STM_USB_EPR_STAT_TX) & STM_USB_EPR_STAT_TX_MASK;
145 static inline uint32_t ao_usb_epr_ctr_rx(uint32_t epr) {
146 return (epr >> STM_USB_EPR_CTR_RX) & 1;
149 static inline uint32_t ao_usb_epr_ctr_tx(uint32_t epr) {
150 return (epr >> STM_USB_EPR_CTR_TX) & 1;
153 static inline uint32_t ao_usb_epr_setup(uint32_t epr) {
154 return (epr >> STM_USB_EPR_SETUP) & 1;
157 static inline uint32_t ao_usb_epr_dtog_rx(uint32_t epr) {
158 return (epr >> STM_USB_EPR_DTOG_RX) & 1;
161 static inline uint32_t ao_usb_epr_dtog_tx(uint32_t epr) {
162 return (epr >> STM_USB_EPR_DTOG_TX) & 1;
166 * Set current device address and mark the
167 * interface as active
170 ao_usb_set_address(uint8_t address)
172 debug("ao_usb_set_address %02x\n", address);
173 stm_usb.daddr = (1 << STM_USB_DADDR_EF) | address;
174 ao_usb_address_pending = 0;
178 * Write these values to preserve register contents under HW changes
181 #define STM_USB_EPR_INVARIANT ((1 << STM_USB_EPR_CTR_RX) | \
182 (STM_USB_EPR_DTOG_RX_WRITE_INVARIANT << STM_USB_EPR_DTOG_RX) | \
183 (STM_USB_EPR_STAT_RX_WRITE_INVARIANT << STM_USB_EPR_STAT_RX) | \
184 (1 << STM_USB_EPR_CTR_TX) | \
185 (STM_USB_EPR_DTOG_TX_WRITE_INVARIANT << STM_USB_EPR_DTOG_TX) | \
186 (STM_USB_EPR_STAT_TX_WRITE_INVARIANT << STM_USB_EPR_STAT_TX))
188 #define STM_USB_EPR_INVARIANT_MASK ((1 << STM_USB_EPR_CTR_RX) | \
189 (STM_USB_EPR_DTOG_RX_MASK << STM_USB_EPR_DTOG_RX) | \
190 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) | \
191 (1 << STM_USB_EPR_CTR_TX) | \
192 (STM_USB_EPR_DTOG_TX_MASK << STM_USB_EPR_DTOG_TX) | \
193 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX))
196 * These bits are purely under sw control, so preserve them in the
197 * register by re-writing what was read
199 #define STM_USB_EPR_PRESERVE_MASK ((STM_USB_EPR_EP_TYPE_MASK << STM_USB_EPR_EP_TYPE) | \
200 (1 << STM_USB_EPR_EP_KIND) | \
201 (STM_USB_EPR_EA_MASK << STM_USB_EPR_EA))
207 #define _tx_dbg0(msg) _dbg(__LINE__,msg,0)
208 #define _tx_dbg1(msg,value) _dbg(__LINE__,msg,value)
210 #define _tx_dbg0(msg)
211 #define _tx_dbg1(msg,value)
215 #define _rx_dbg0(msg) _dbg(__LINE__,msg,0)
216 #define _rx_dbg1(msg,value) _dbg(__LINE__,msg,value)
218 #define _rx_dbg0(msg)
219 #define _rx_dbg1(msg,value)
223 static void _dbg(int line, char *msg, uint32_t value);
227 * Set the state of the specified endpoint register to a new
228 * value. This is tricky because the bits toggle where the new
229 * value is one, and we need to write invariant values in other
230 * spots of the register. This hardware is strange...
233 _ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
235 uint32_t epr_write, epr_old;
237 _tx_dbg1("set_stat_tx top", stat_tx);
238 epr_old = epr_write = stm_usb.epr[ep];
239 epr_write &= STM_USB_EPR_PRESERVE_MASK;
240 epr_write |= STM_USB_EPR_INVARIANT;
241 epr_write |= set_toggle(epr_old,
242 STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX,
243 stat_tx << STM_USB_EPR_STAT_TX);
244 stm_usb.epr[ep] = epr_write;
245 _tx_dbg1("set_stat_tx bottom", epr_write);
249 ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
251 ao_arch_block_interrupts();
252 _ao_usb_set_stat_tx(ep, stat_tx);
253 ao_arch_release_interrupts();
257 _ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
258 uint32_t epr_write, epr_old;
260 epr_write = epr_old = stm_usb.epr[ep];
261 epr_write &= STM_USB_EPR_PRESERVE_MASK;
262 epr_write |= STM_USB_EPR_INVARIANT;
263 epr_write |= set_toggle(epr_old,
264 STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX,
265 stat_rx << STM_USB_EPR_STAT_RX);
266 stm_usb.epr[ep] = epr_write;
270 ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
271 ao_arch_block_interrupts();
272 _ao_usb_set_stat_rx(ep, stat_rx);
273 ao_arch_release_interrupts();
277 * Set just endpoint 0, for use during startup
281 ao_usb_init_ep(uint8_t ep, uint32_t addr, uint32_t type, uint32_t stat_rx, uint32_t stat_tx)
284 ao_arch_block_interrupts();
285 epr = stm_usb.epr[ep];
286 epr = ((0 << STM_USB_EPR_CTR_RX) |
287 (epr & (1 << STM_USB_EPR_DTOG_RX)) |
289 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX),
290 (stat_rx << STM_USB_EPR_STAT_RX)) |
291 (type << STM_USB_EPR_EP_TYPE) |
292 (0 << STM_USB_EPR_EP_KIND) |
293 (0 << STM_USB_EPR_CTR_TX) |
294 (epr & (1 << STM_USB_EPR_DTOG_TX)) |
296 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX),
297 (stat_tx << STM_USB_EPR_STAT_TX)) |
298 (addr << STM_USB_EPR_EA));
299 stm_usb.epr[ep] = epr;
300 ao_arch_release_interrupts();
301 debug ("writing epr[%d] 0x%08x wrote 0x%08x\n",
302 ep, epr, stm_usb.epr[ep]);
311 ao_usb_sram_addr = 0;
313 /* buffer table is at the start of USB memory */
315 ao_usb_bdt = (void *) stm_usb_sram;
317 ao_usb_sram_addr += 8 * STM_USB_BDT_SIZE;
319 /* Set up EP 0 - a Control end point with 32 bytes of in and out buffers */
321 ao_usb_bdt[0].single.addr_tx = ao_usb_sram_addr;
322 ao_usb_bdt[0].single.count_tx = 0;
323 ao_usb_ep0_tx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
324 ao_usb_sram_addr += AO_USB_CONTROL_SIZE;
326 ao_usb_bdt[0].single.addr_rx = ao_usb_sram_addr;
327 ao_usb_bdt[0].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
328 (((AO_USB_CONTROL_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
329 ao_usb_ep0_rx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
330 ao_usb_sram_addr += AO_USB_CONTROL_SIZE;
332 ao_usb_init_ep(AO_USB_CONTROL_EPR, AO_USB_CONTROL_EP,
333 STM_USB_EPR_EP_TYPE_CONTROL,
334 STM_USB_EPR_STAT_RX_VALID,
335 STM_USB_EPR_STAT_TX_NAK);
337 /* Clear all of the other endpoints */
338 for (e = 1; e < 8; e++) {
340 STM_USB_EPR_EP_TYPE_CONTROL,
341 STM_USB_EPR_STAT_RX_DISABLED,
342 STM_USB_EPR_STAT_TX_DISABLED);
345 ao_usb_set_address(0);
349 ao_usb_set_configuration(void)
353 debug ("ao_usb_set_configuration\n");
355 /* Set up the INT end point */
356 ao_usb_bdt[AO_USB_INT_EPR].single.addr_tx = ao_usb_sram_addr;
357 ao_usb_bdt[AO_USB_INT_EPR].single.count_tx = 0;
358 ao_usb_in_tx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
359 ao_usb_sram_addr += AO_USB_INT_SIZE;
361 ao_usb_init_ep(AO_USB_INT_EPR,
363 STM_USB_EPR_EP_TYPE_INTERRUPT,
364 STM_USB_EPR_STAT_RX_DISABLED,
365 STM_USB_EPR_STAT_TX_NAK);
367 /* Set up the OUT end point */
368 ao_usb_bdt[AO_USB_OUT_EPR].single.addr_rx = ao_usb_sram_addr;
369 ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
370 (((AO_USB_OUT_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
371 ao_usb_out_rx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
372 ao_usb_sram_addr += AO_USB_OUT_SIZE;
374 ao_usb_init_ep(AO_USB_OUT_EPR,
376 STM_USB_EPR_EP_TYPE_BULK,
377 STM_USB_EPR_STAT_RX_VALID,
378 STM_USB_EPR_STAT_TX_DISABLED);
380 /* Set up the IN end point */
381 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_sram_addr;
382 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = 0;
383 ao_usb_in_tx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
384 ao_usb_sram_addr += AO_USB_IN_SIZE;
386 ao_usb_init_ep(AO_USB_IN_EPR,
388 STM_USB_EPR_EP_TYPE_BULK,
389 STM_USB_EPR_STAT_RX_DISABLED,
390 STM_USB_EPR_STAT_TX_NAK);
395 static uint16_t control_count;
396 static uint16_t int_count;
397 static uint16_t in_count;
398 static uint16_t out_count;
399 static uint16_t reset_count;
404 uint32_t istr = stm_usb.istr;
406 if (istr & (1 << STM_USB_ISTR_CTR)) {
407 uint8_t ep = istr & STM_USB_ISTR_EP_ID_MASK;
408 uint32_t epr, epr_write;
410 /* Preserve the SW write bits, don't mess with most HW writable bits,
411 * clear the CTR_RX and CTR_TX bits
413 epr = stm_usb.epr[ep];
415 epr_write &= STM_USB_EPR_PRESERVE_MASK;
416 epr_write |= STM_USB_EPR_INVARIANT;
417 epr_write &= ~(1 << STM_USB_EPR_CTR_RX);
418 epr_write &= ~(1 << STM_USB_EPR_CTR_TX);
419 stm_usb.epr[ep] = epr_write;
424 if (ao_usb_epr_ctr_rx(epr)) {
425 if (ao_usb_epr_setup(epr))
426 ao_usb_ep0_receive |= AO_USB_EP0_GOT_SETUP;
428 ao_usb_ep0_receive |= AO_USB_EP0_GOT_RX_DATA;
430 if (ao_usb_epr_ctr_tx(epr))
431 ao_usb_ep0_receive |= AO_USB_EP0_GOT_TX_ACK;
432 ao_wakeup(&ao_usb_ep0_receive);
436 if (ao_usb_epr_ctr_rx(epr)) {
437 _rx_dbg1("RX ISR", epr);
438 ao_usb_out_avail = 1;
439 _rx_dbg0("out avail set");
440 ao_wakeup(&ao_stdin_ready);
441 _rx_dbg0("stdin awoken");
446 _tx_dbg1("TX ISR", epr);
447 if (ao_usb_epr_ctr_tx(epr)) {
448 ao_usb_in_pending = 0;
449 ao_wakeup(&ao_usb_in_pending);
454 if (ao_usb_epr_ctr_tx(epr))
455 _ao_usb_set_stat_tx(AO_USB_INT_EPR, STM_USB_EPR_STAT_TX_NAK);
461 if (istr & (1 << STM_USB_ISTR_RESET)) {
463 stm_usb.istr &= ~(1 << STM_USB_ISTR_RESET);
464 ao_usb_ep0_receive |= AO_USB_EP0_GOT_RESET;
465 ao_wakeup(&ao_usb_ep0_receive);
470 stm_usb_fs_wkup(void)
472 /* USB wakeup, just clear the bit for now */
473 stm_usb.istr &= ~(1 << STM_USB_ISTR_WKUP);
476 /* The USB memory holds 16 bit values on 32 bit boundaries
477 * and must be accessed only in 32 bit units. Sigh.
481 ao_usb_write_byte(uint8_t byte, uint32_t *base, uint16_t offset)
485 *base = (*base & 0xff) | ((uint32_t) byte << 8);
487 *base = (*base & 0xff00) | byte;
492 ao_usb_write_short(uint16_t data, uint32_t *base, uint16_t offset)
494 base[offset>>1] = data;
498 ao_usb_write(const uint8_t *src, uint32_t *base, uint16_t offset, uint16_t bytes)
503 debug_data (" %02x", src[0]);
504 ao_usb_write_byte(*src++, base, offset++);
508 debug_data (" %02x %02x", src[0], src[1]);
509 ao_usb_write_short((src[1] << 8) | src[0], base, offset);
515 debug_data (" %02x", src[0]);
516 ao_usb_write_byte(*src, base, offset);
520 static inline uint8_t
521 ao_usb_read_byte(uint32_t *base, uint16_t offset)
525 return (*base >> 8) & 0xff;
530 static inline uint16_t
531 ao_usb_read_short(uint32_t *base, uint16_t offset)
533 return base[offset>>1];
537 ao_usb_read(uint8_t *dst, uint32_t *base, uint16_t offset, uint16_t bytes)
542 *dst++ = ao_usb_read_byte(base, offset++);
543 debug_data (" %02x", dst[-1]);
547 uint16_t s = ao_usb_read_short(base, offset);
550 debug_data (" %02x %02x", dst[0], dst[1]);
556 *dst = ao_usb_read_byte(base, offset);
557 debug_data (" %02x", dst[0]);
561 /* Send an IN data packet */
563 ao_usb_ep0_flush(void)
567 /* Check to see if the endpoint is still busy */
568 if (ao_usb_epr_stat_tx(stm_usb.epr[0]) == STM_USB_EPR_STAT_TX_VALID) {
569 debug("EP0 not accepting IN data\n");
573 this_len = ao_usb_ep0_in_len;
574 if (this_len > AO_USB_CONTROL_SIZE)
575 this_len = AO_USB_CONTROL_SIZE;
577 if (this_len < AO_USB_CONTROL_SIZE)
578 ao_usb_ep0_state = AO_USB_EP0_IDLE;
580 ao_usb_ep0_in_len -= this_len;
582 debug_data ("Flush EP0 len %d:", this_len);
583 ao_usb_write(ao_usb_ep0_in_data, ao_usb_ep0_tx_buffer, 0, this_len);
585 ao_usb_ep0_in_data += this_len;
587 /* Mark the endpoint as TX valid to send the packet */
588 ao_usb_bdt[AO_USB_CONTROL_EPR].single.count_tx = this_len;
589 ao_usb_set_stat_tx(AO_USB_CONTROL_EPR, STM_USB_EPR_STAT_TX_VALID);
590 debug ("queue tx. epr 0 now %08x\n", stm_usb.epr[AO_USB_CONTROL_EPR]);
593 /* Read data from the ep0 OUT fifo */
595 ao_usb_ep0_fill(void)
597 uint16_t len = ao_usb_bdt[0].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
599 if (len > ao_usb_ep0_out_len)
600 len = ao_usb_ep0_out_len;
601 ao_usb_ep0_out_len -= len;
603 /* Pull all of the data out of the packet */
604 debug_data ("Fill EP0 len %d:", len);
605 ao_usb_read(ao_usb_ep0_out_data, ao_usb_ep0_rx_buffer, 0, len);
607 ao_usb_ep0_out_data += len;
610 ao_usb_set_stat_rx(0, STM_USB_EPR_STAT_RX_VALID);
614 ao_usb_ep0_in_reset(void)
616 ao_usb_ep0_in_data = ao_usb_ep0_in_buf;
617 ao_usb_ep0_in_len = 0;
621 ao_usb_ep0_in_queue_byte(uint8_t a)
623 if (ao_usb_ep0_in_len < sizeof (ao_usb_ep0_in_buf))
624 ao_usb_ep0_in_buf[ao_usb_ep0_in_len++] = a;
628 ao_usb_ep0_in_set(const uint8_t *data, uint8_t len)
630 ao_usb_ep0_in_data = data;
631 ao_usb_ep0_in_len = len;
635 ao_usb_ep0_out_set(uint8_t *data, uint8_t len)
637 ao_usb_ep0_out_data = data;
638 ao_usb_ep0_out_len = len;
642 ao_usb_ep0_in_start(uint8_t max)
644 /* Don't send more than asked for */
645 if (ao_usb_ep0_in_len > max)
646 ao_usb_ep0_in_len = max;
650 static struct ao_usb_line_coding ao_usb_line_coding = {115200, 0, 0, 8};
652 /* Walk through the list of descriptors and find a match
655 ao_usb_get_descriptor(uint16_t value)
657 const uint8_t *descriptor;
658 uint8_t type = value >> 8;
659 uint8_t index = value;
661 descriptor = ao_usb_descriptors;
662 while (descriptor[0] != 0) {
663 if (descriptor[1] == type && index-- == 0) {
665 if (type == AO_USB_DESC_CONFIGURATION)
669 ao_usb_ep0_in_set(descriptor, len);
672 descriptor += descriptor[0];
677 ao_usb_ep0_setup(void)
679 /* Pull the setup packet out of the fifo */
680 ao_usb_ep0_out_set((uint8_t *) &ao_usb_setup, 8);
682 if (ao_usb_ep0_out_len != 0) {
683 debug ("invalid setup packet length\n");
687 if ((ao_usb_setup.dir_type_recip & AO_USB_DIR_IN) || ao_usb_setup.length == 0)
688 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
690 ao_usb_ep0_state = AO_USB_EP0_DATA_OUT;
692 ao_usb_ep0_in_reset();
694 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_TYPE_MASK) {
695 case AO_USB_TYPE_STANDARD:
696 debug ("Standard setup packet\n");
697 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_RECIP_MASK) {
698 case AO_USB_RECIP_DEVICE:
699 debug ("Device setup packet\n");
700 switch(ao_usb_setup.request) {
701 case AO_USB_REQ_GET_STATUS:
702 debug ("get status\n");
703 ao_usb_ep0_in_queue_byte(0);
704 ao_usb_ep0_in_queue_byte(0);
706 case AO_USB_REQ_SET_ADDRESS:
707 debug ("set address %d\n", ao_usb_setup.value);
708 ao_usb_address = ao_usb_setup.value;
709 ao_usb_address_pending = 1;
711 case AO_USB_REQ_GET_DESCRIPTOR:
712 debug ("get descriptor %d\n", ao_usb_setup.value);
713 ao_usb_get_descriptor(ao_usb_setup.value);
715 case AO_USB_REQ_GET_CONFIGURATION:
716 debug ("get configuration %d\n", ao_usb_configuration);
717 ao_usb_ep0_in_queue_byte(ao_usb_configuration);
719 case AO_USB_REQ_SET_CONFIGURATION:
720 ao_usb_configuration = ao_usb_setup.value;
721 debug ("set configuration %d\n", ao_usb_configuration);
722 ao_usb_set_configuration();
726 case AO_USB_RECIP_INTERFACE:
727 debug ("Interface setup packet\n");
728 switch(ao_usb_setup.request) {
729 case AO_USB_REQ_GET_STATUS:
730 ao_usb_ep0_in_queue_byte(0);
731 ao_usb_ep0_in_queue_byte(0);
733 case AO_USB_REQ_GET_INTERFACE:
734 ao_usb_ep0_in_queue_byte(0);
736 case AO_USB_REQ_SET_INTERFACE:
740 case AO_USB_RECIP_ENDPOINT:
741 debug ("Endpoint setup packet\n");
742 switch(ao_usb_setup.request) {
743 case AO_USB_REQ_GET_STATUS:
744 ao_usb_ep0_in_queue_byte(0);
745 ao_usb_ep0_in_queue_byte(0);
751 case AO_USB_TYPE_CLASS:
752 debug ("Class setup packet\n");
753 switch (ao_usb_setup.request) {
754 case AO_USB_SET_LINE_CODING:
755 debug ("set line coding\n");
756 ao_usb_ep0_out_set((uint8_t *) &ao_usb_line_coding, 7);
758 case AO_USB_GET_LINE_CODING:
759 debug ("get line coding\n");
760 ao_usb_ep0_in_set((const uint8_t *) &ao_usb_line_coding, 7);
762 case AO_USB_SET_CONTROL_LINE_STATE:
768 /* If we're not waiting to receive data from the host,
769 * queue an IN response
771 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
772 ao_usb_ep0_in_start(ao_usb_setup.length);
775 /* End point 0 receives all of the control messages. */
781 debug ("usb task started\n");
782 ao_usb_ep0_state = AO_USB_EP0_IDLE;
786 while (!(receive = ao_usb_ep0_receive))
787 ao_sleep(&ao_usb_ep0_receive);
788 ao_usb_ep0_receive = 0;
791 if (receive & AO_USB_EP0_GOT_RESET) {
796 if (receive & AO_USB_EP0_GOT_SETUP) {
800 if (receive & AO_USB_EP0_GOT_RX_DATA) {
801 debug ("\tgot rx data\n");
802 if (ao_usb_ep0_state == AO_USB_EP0_DATA_OUT) {
804 if (ao_usb_ep0_out_len == 0) {
805 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
806 ao_usb_ep0_in_start(0);
810 if (receive & AO_USB_EP0_GOT_TX_ACK) {
811 debug ("\tgot tx ack\n");
813 /* Wait until the IN packet is received from addr 0
814 * before assigning our local address
816 if (ao_usb_address_pending)
817 ao_usb_set_address(ao_usb_address);
818 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
824 /* Queue the current IN buffer for transmission */
826 _ao_usb_in_send(void)
828 _tx_dbg0("in_send start");
829 debug ("send %d\n", ao_usb_tx_count);
830 while (ao_usb_in_pending)
831 ao_sleep(&ao_usb_in_pending);
832 ao_usb_in_pending = 1;
833 if (ao_usb_tx_count != AO_USB_IN_SIZE)
834 ao_usb_in_flushed = 1;
835 ao_usb_write(ao_usb_tx_buffer, ao_usb_in_tx_buffer, 0, ao_usb_tx_count);
836 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = ao_usb_tx_count;
838 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
839 _tx_dbg0("in_send end");
842 /* Wait for a free IN buffer. Interrupts are blocked */
844 _ao_usb_in_wait(void)
847 /* Check if the current buffer is writable */
848 if (ao_usb_tx_count < AO_USB_IN_SIZE)
851 _tx_dbg0("in_wait top");
852 /* Wait for an IN buffer to be ready */
853 while (ao_usb_in_pending)
854 ao_sleep(&ao_usb_in_pending);
855 _tx_dbg0("in_wait bottom");
865 /* Anytime we've sent a character since
866 * the last time we flushed, we'll need
867 * to send a packet -- the only other time
868 * we would send a packet is when that
869 * packet was full, in which case we now
870 * want to send an empty packet
872 ao_arch_block_interrupts();
873 while (!ao_usb_in_flushed) {
874 _tx_dbg0("flush top");
876 _tx_dbg0("flush end");
878 ao_arch_release_interrupts();
882 ao_usb_putchar(char c)
887 ao_arch_block_interrupts();
890 ao_usb_in_flushed = 0;
891 ao_usb_tx_buffer[ao_usb_tx_count++] = (uint8_t) c;
893 /* Send the packet when full */
894 if (ao_usb_tx_count == AO_USB_IN_SIZE) {
895 _tx_dbg0("putchar full");
897 _tx_dbg0("putchar flushed");
899 ao_arch_release_interrupts();
903 _ao_usb_out_recv(void)
905 _rx_dbg0("out_recv top");
906 ao_usb_out_avail = 0;
908 ao_usb_rx_count = ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
910 _rx_dbg1("out_recv count", ao_usb_rx_count);
911 debug ("recv %d\n", ao_usb_rx_count);
912 debug_data("Fill OUT len %d:", ao_usb_rx_count);
913 ao_usb_read(ao_usb_rx_buffer, ao_usb_out_rx_buffer, 0, ao_usb_rx_count);
918 _ao_usb_set_stat_rx(AO_USB_OUT_EPR, STM_USB_EPR_STAT_RX_VALID);
922 _ao_usb_pollchar(void)
927 return AO_READ_AGAIN;
930 if (ao_usb_rx_pos != ao_usb_rx_count)
933 _rx_dbg0("poll check");
934 /* Check to see if a packet has arrived */
935 if (!ao_usb_out_avail) {
936 _rx_dbg0("poll none");
937 return AO_READ_AGAIN;
942 /* Pull a character out of the fifo */
943 c = ao_usb_rx_buffer[ao_usb_rx_pos++];
952 ao_arch_block_interrupts();
953 while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN)
954 ao_sleep(&ao_stdin_ready);
955 ao_arch_release_interrupts();
962 ao_arch_block_interrupts();
963 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
966 /* Disable USB pull-up */
967 stm_syscfg.pmc &= ~(1 << STM_SYSCFG_PMC_USB_PU);
969 /* Switch off the device */
970 stm_usb.cntr = (1 << STM_USB_CNTR_PDWN) | (1 << STM_USB_CNTR_FRES);
972 /* Disable the interface */
973 stm_rcc.apb1enr &+ ~(1 << STM_RCC_APB1ENR_USBEN);
974 ao_arch_release_interrupts();
983 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN);
985 /* Disable USB pull-up */
986 stm_syscfg.pmc &= ~(1 << STM_SYSCFG_PMC_USB_PU);
988 /* Enable USB device */
989 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USBEN);
991 /* Do not touch the GPIOA configuration; USB takes priority
992 * over GPIO on pins A11 and A12, but if you select alternate
993 * input 10 (the documented correct selection), then USB is
994 * pulled low and doesn't work at all
997 ao_arch_block_interrupts();
999 /* Route interrupts */
1000 stm_nvic_set_priority(STM_ISR_USB_LP_POS, 3);
1001 stm_nvic_set_enable(STM_ISR_USB_LP_POS);
1003 ao_usb_configuration = 0;
1005 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1007 /* Clear the power down bit */
1010 /* Clear any spurious interrupts */
1013 debug ("ao_usb_enable\n");
1015 /* Enable interrupts */
1016 stm_usb.cntr = ((1 << STM_USB_CNTR_CTRM) |
1017 (0 << STM_USB_CNTR_PMAOVRM) |
1018 (0 << STM_USB_CNTR_ERRM) |
1019 (0 << STM_USB_CNTR_WKUPM) |
1020 (0 << STM_USB_CNTR_SUSPM) |
1021 (1 << STM_USB_CNTR_RESETM) |
1022 (0 << STM_USB_CNTR_SOFM) |
1023 (0 << STM_USB_CNTR_ESOFM) |
1024 (0 << STM_USB_CNTR_RESUME) |
1025 (0 << STM_USB_CNTR_FSUSP) |
1026 (0 << STM_USB_CNTR_LP_MODE) |
1027 (0 << STM_USB_CNTR_PDWN) |
1028 (0 << STM_USB_CNTR_FRES));
1030 ao_arch_release_interrupts();
1032 for (t = 0; t < 1000; t++)
1034 /* Enable USB pull-up */
1035 stm_syscfg.pmc |= (1 << STM_SYSCFG_PMC_USB_PU);
1039 struct ao_task ao_usb_echo_task;
1047 c = ao_usb_getchar();
1058 printf ("control: %d out: %d in: %d int: %d reset: %d\n",
1059 control_count, out_count, in_count, int_count, reset_count);
1062 __code struct ao_cmds ao_usb_cmds[] = {
1063 { ao_usb_irq, "I\0Show USB interrupt counts" },
1073 debug ("ao_usb_init\n");
1074 ao_add_task(&ao_usb_task, ao_usb_ep0, "usb");
1076 ao_add_task(&ao_usb_echo_task, ao_usb_echo, "usb echo");
1079 ao_cmd_register(&ao_usb_cmds[0]);
1082 ao_add_stdio(_ao_usb_pollchar, ao_usb_putchar, ao_usb_flush);
1086 #if TX_DBG || RX_DBG
1096 uint32_t in_pending;
1098 uint32_t in_flushed;
1108 #define NUM_USB_DBG 128
1110 static struct ao_usb_dbg dbg[128];
1113 static void _dbg(int line, char *msg, uint32_t value)
1116 dbg[dbg_i].line = line;
1117 dbg[dbg_i].msg = msg;
1118 dbg[dbg_i].value = value;
1119 asm("mrs %0,primask" : "=&r" (primask));
1120 dbg[dbg_i].primask = primask;
1122 dbg[dbg_i].in_count = in_count;
1123 dbg[dbg_i].in_epr = stm_usb.epr[AO_USB_IN_EPR];
1124 dbg[dbg_i].in_pending = ao_usb_in_pending;
1125 dbg[dbg_i].tx_count = ao_usb_tx_count;
1126 dbg[dbg_i].in_flushed = ao_usb_in_flushed;
1129 dbg[dbg_i].rx_count = ao_usb_rx_count;
1130 dbg[dbg_i].rx_pos = ao_usb_rx_pos;
1131 dbg[dbg_i].out_avail = ao_usb_out_avail;
1132 dbg[dbg_i].out_epr = stm_usb.epr[AO_USB_OUT_EPR];
1134 if (++dbg_i == NUM_USB_DBG)