2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 #include "ao_product.h"
24 #define USB_DEBUG_DATA 0
28 #define USE_USB_STDIO 1
32 #define AO_USB_OUT_SLEEP_ADDR (&ao_stdin_ready)
34 #define AO_USB_OUT_SLEEP_ADDR (&ao_usb_out_avail)
38 #define debug(format, args...) printf(format, ## args);
40 #define debug(format, args...)
44 #define debug_data(format, args...) printf(format, ## args);
46 #define debug_data(format, args...)
50 uint8_t dir_type_recip;
57 static uint8_t ao_usb_ep0_state;
59 /* Pending EP0 IN data */
60 static const uint8_t *ao_usb_ep0_in_data; /* Remaining data */
61 static uint8_t ao_usb_ep0_in_len; /* Remaining amount */
63 /* Temp buffer for smaller EP0 in data */
64 static uint8_t ao_usb_ep0_in_buf[2];
66 /* Pending EP0 OUT data */
67 static uint8_t *ao_usb_ep0_out_data;
68 static uint8_t ao_usb_ep0_out_len;
71 * Objects allocated in special USB memory
74 /* Buffer description tables */
75 static union stm_usb_bdt *ao_usb_bdt;
76 /* USB address of end of allocated storage */
77 static uint16_t ao_usb_sram_addr;
79 /* Pointer to ep0 tx/rx buffers in USB memory */
80 static uint32_t *ao_usb_ep0_tx_buffer;
81 static uint32_t *ao_usb_ep0_rx_buffer;
83 /* Pointer to bulk data tx/rx buffers in USB memory */
84 static uint32_t *ao_usb_in_tx_buffer;
85 static uint32_t *ao_usb_out_rx_buffer;
87 /* System ram shadow of USB buffer; writing individual bytes is
88 * too much of a pain (sigh) */
89 static uint8_t ao_usb_tx_buffer[AO_USB_IN_SIZE];
90 static uint8_t ao_usb_tx_count;
92 static uint8_t ao_usb_rx_buffer[AO_USB_OUT_SIZE];
93 static uint8_t ao_usb_rx_count, ao_usb_rx_pos;
96 * End point register indices
99 #define AO_USB_CONTROL_EPR 0
100 #define AO_USB_INT_EPR 1
101 #define AO_USB_OUT_EPR 2
102 #define AO_USB_IN_EPR 3
104 /* Marks when we don't need to send an IN packet.
105 * This happens only when the last IN packet is not full,
106 * otherwise the host will expect to keep seeing packets.
107 * Send a zero-length packet as required
109 static uint8_t ao_usb_in_flushed;
111 /* Marks when we have delivered an IN packet to the hardware
112 * and it has not been received yet. ao_sleep on this address
113 * to wait for it to be delivered.
115 static uint8_t ao_usb_in_pending;
117 /* Marks when an OUT packet has been received by the hardware
118 * but not pulled to the shadow buffer.
120 static uint8_t ao_usb_out_avail;
121 uint8_t ao_usb_running;
122 static uint8_t ao_usb_configuration;
124 #define AO_USB_EP0_GOT_RESET 1
125 #define AO_USB_EP0_GOT_SETUP 2
126 #define AO_USB_EP0_GOT_RX_DATA 4
127 #define AO_USB_EP0_GOT_TX_ACK 8
129 static uint8_t ao_usb_ep0_receive;
130 static uint8_t ao_usb_address;
131 static uint8_t ao_usb_address_pending;
133 static inline uint32_t set_toggle(uint32_t current_value,
135 uint32_t desired_value)
137 return (current_value ^ desired_value) & mask;
140 static inline uint32_t *ao_usb_packet_buffer_addr(uint16_t sram_addr)
142 return (uint32_t *) (((void *) ((uint8_t *) stm_usb_sram + 2 * sram_addr)));
145 static inline uint32_t ao_usb_epr_stat_rx(uint32_t epr) {
146 return (epr >> STM_USB_EPR_STAT_RX) & STM_USB_EPR_STAT_RX_MASK;
149 static inline uint32_t ao_usb_epr_stat_tx(uint32_t epr) {
150 return (epr >> STM_USB_EPR_STAT_TX) & STM_USB_EPR_STAT_TX_MASK;
153 static inline uint32_t ao_usb_epr_ctr_rx(uint32_t epr) {
154 return (epr >> STM_USB_EPR_CTR_RX) & 1;
157 static inline uint32_t ao_usb_epr_ctr_tx(uint32_t epr) {
158 return (epr >> STM_USB_EPR_CTR_TX) & 1;
161 static inline uint32_t ao_usb_epr_setup(uint32_t epr) {
162 return (epr >> STM_USB_EPR_SETUP) & 1;
165 static inline uint32_t ao_usb_epr_dtog_rx(uint32_t epr) {
166 return (epr >> STM_USB_EPR_DTOG_RX) & 1;
169 static inline uint32_t ao_usb_epr_dtog_tx(uint32_t epr) {
170 return (epr >> STM_USB_EPR_DTOG_TX) & 1;
174 * Set current device address and mark the
175 * interface as active
178 ao_usb_set_address(uint8_t address)
180 debug("ao_usb_set_address %02x\n", address);
181 stm_usb.daddr = (1 << STM_USB_DADDR_EF) | address;
182 ao_usb_address_pending = 0;
186 * Write these values to preserve register contents under HW changes
189 #define STM_USB_EPR_INVARIANT ((1 << STM_USB_EPR_CTR_RX) | \
190 (STM_USB_EPR_DTOG_RX_WRITE_INVARIANT << STM_USB_EPR_DTOG_RX) | \
191 (STM_USB_EPR_STAT_RX_WRITE_INVARIANT << STM_USB_EPR_STAT_RX) | \
192 (1 << STM_USB_EPR_CTR_TX) | \
193 (STM_USB_EPR_DTOG_TX_WRITE_INVARIANT << STM_USB_EPR_DTOG_TX) | \
194 (STM_USB_EPR_STAT_TX_WRITE_INVARIANT << STM_USB_EPR_STAT_TX))
196 #define STM_USB_EPR_INVARIANT_MASK ((1 << STM_USB_EPR_CTR_RX) | \
197 (STM_USB_EPR_DTOG_RX_MASK << STM_USB_EPR_DTOG_RX) | \
198 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) | \
199 (1 << STM_USB_EPR_CTR_TX) | \
200 (STM_USB_EPR_DTOG_TX_MASK << STM_USB_EPR_DTOG_TX) | \
201 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX))
204 * These bits are purely under sw control, so preserve them in the
205 * register by re-writing what was read
207 #define STM_USB_EPR_PRESERVE_MASK ((STM_USB_EPR_EP_TYPE_MASK << STM_USB_EPR_EP_TYPE) | \
208 (1 << STM_USB_EPR_EP_KIND) | \
209 (STM_USB_EPR_EA_MASK << STM_USB_EPR_EA))
215 #define _tx_dbg0(msg) _dbg(__LINE__,msg,0)
216 #define _tx_dbg1(msg,value) _dbg(__LINE__,msg,value)
218 #define _tx_dbg0(msg)
219 #define _tx_dbg1(msg,value)
223 #define _rx_dbg0(msg) _dbg(__LINE__,msg,0)
224 #define _rx_dbg1(msg,value) _dbg(__LINE__,msg,value)
226 #define _rx_dbg0(msg)
227 #define _rx_dbg1(msg,value)
231 static void _dbg(int line, char *msg, uint32_t value);
235 * Set the state of the specified endpoint register to a new
236 * value. This is tricky because the bits toggle where the new
237 * value is one, and we need to write invariant values in other
238 * spots of the register. This hardware is strange...
241 _ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
243 uint32_t epr_write, epr_old;
245 _tx_dbg1("set_stat_tx top", stat_tx);
246 epr_old = epr_write = stm_usb.epr[ep];
247 epr_write &= STM_USB_EPR_PRESERVE_MASK;
248 epr_write |= STM_USB_EPR_INVARIANT;
249 epr_write |= set_toggle(epr_old,
250 STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX,
251 stat_tx << STM_USB_EPR_STAT_TX);
252 stm_usb.epr[ep] = epr_write;
253 _tx_dbg1("set_stat_tx bottom", epr_write);
257 ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
259 ao_arch_block_interrupts();
260 _ao_usb_set_stat_tx(ep, stat_tx);
261 ao_arch_release_interrupts();
265 _ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
266 uint32_t epr_write, epr_old;
268 epr_write = epr_old = stm_usb.epr[ep];
269 epr_write &= STM_USB_EPR_PRESERVE_MASK;
270 epr_write |= STM_USB_EPR_INVARIANT;
271 epr_write |= set_toggle(epr_old,
272 STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX,
273 stat_rx << STM_USB_EPR_STAT_RX);
274 stm_usb.epr[ep] = epr_write;
278 ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
279 ao_arch_block_interrupts();
280 _ao_usb_set_stat_rx(ep, stat_rx);
281 ao_arch_release_interrupts();
285 * Set just endpoint 0, for use during startup
289 ao_usb_init_ep(uint8_t ep, uint32_t addr, uint32_t type, uint32_t stat_rx, uint32_t stat_tx)
292 ao_arch_block_interrupts();
293 epr = stm_usb.epr[ep];
294 epr = ((0 << STM_USB_EPR_CTR_RX) |
295 (epr & (1 << STM_USB_EPR_DTOG_RX)) |
297 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX),
298 (stat_rx << STM_USB_EPR_STAT_RX)) |
299 (type << STM_USB_EPR_EP_TYPE) |
300 (0 << STM_USB_EPR_EP_KIND) |
301 (0 << STM_USB_EPR_CTR_TX) |
302 (epr & (1 << STM_USB_EPR_DTOG_TX)) |
304 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX),
305 (stat_tx << STM_USB_EPR_STAT_TX)) |
306 (addr << STM_USB_EPR_EA));
307 stm_usb.epr[ep] = epr;
308 ao_arch_release_interrupts();
309 debug ("writing epr[%d] 0x%08x wrote 0x%08x\n",
310 ep, epr, stm_usb.epr[ep]);
318 ao_usb_sram_addr = 0;
320 /* buffer table is at the start of USB memory */
322 ao_usb_bdt = (void *) stm_usb_sram;
324 ao_usb_sram_addr += 8 * STM_USB_BDT_SIZE;
326 /* Set up EP 0 - a Control end point with 32 bytes of in and out buffers */
328 ao_usb_bdt[0].single.addr_tx = ao_usb_sram_addr;
329 ao_usb_bdt[0].single.count_tx = 0;
330 ao_usb_ep0_tx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
331 ao_usb_sram_addr += AO_USB_CONTROL_SIZE;
333 ao_usb_bdt[0].single.addr_rx = ao_usb_sram_addr;
334 ao_usb_bdt[0].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
335 (((AO_USB_CONTROL_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
336 ao_usb_ep0_rx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
337 ao_usb_sram_addr += AO_USB_CONTROL_SIZE;
339 ao_usb_init_ep(AO_USB_CONTROL_EPR, AO_USB_CONTROL_EP,
340 STM_USB_EPR_EP_TYPE_CONTROL,
341 STM_USB_EPR_STAT_RX_VALID,
342 STM_USB_EPR_STAT_TX_NAK);
344 /* Clear all of the other endpoints */
345 for (e = 1; e < 8; e++) {
347 STM_USB_EPR_EP_TYPE_CONTROL,
348 STM_USB_EPR_STAT_RX_DISABLED,
349 STM_USB_EPR_STAT_TX_DISABLED);
352 ao_usb_set_address(0);
356 /* Reset our internal state
359 ao_usb_ep0_state = AO_USB_EP0_IDLE;
361 ao_usb_ep0_in_data = NULL;
362 ao_usb_ep0_in_len = 0;
364 ao_usb_ep0_out_data = 0;
365 ao_usb_ep0_out_len = 0;
369 ao_usb_set_configuration(void)
371 debug ("ao_usb_set_configuration\n");
373 /* Set up the INT end point */
374 ao_usb_bdt[AO_USB_INT_EPR].single.addr_tx = ao_usb_sram_addr;
375 ao_usb_bdt[AO_USB_INT_EPR].single.count_tx = 0;
376 ao_usb_in_tx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
377 ao_usb_sram_addr += AO_USB_INT_SIZE;
379 ao_usb_init_ep(AO_USB_INT_EPR,
381 STM_USB_EPR_EP_TYPE_INTERRUPT,
382 STM_USB_EPR_STAT_RX_DISABLED,
383 STM_USB_EPR_STAT_TX_NAK);
385 /* Set up the OUT end point */
386 ao_usb_bdt[AO_USB_OUT_EPR].single.addr_rx = ao_usb_sram_addr;
387 ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
388 (((AO_USB_OUT_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
389 ao_usb_out_rx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
390 ao_usb_sram_addr += AO_USB_OUT_SIZE;
392 ao_usb_init_ep(AO_USB_OUT_EPR,
394 STM_USB_EPR_EP_TYPE_BULK,
395 STM_USB_EPR_STAT_RX_VALID,
396 STM_USB_EPR_STAT_TX_DISABLED);
398 /* Set up the IN end point */
399 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_sram_addr;
400 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = 0;
401 ao_usb_in_tx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
402 ao_usb_sram_addr += AO_USB_IN_SIZE;
404 ao_usb_init_ep(AO_USB_IN_EPR,
406 STM_USB_EPR_EP_TYPE_BULK,
407 STM_USB_EPR_STAT_RX_DISABLED,
408 STM_USB_EPR_STAT_TX_NAK);
410 ao_usb_in_flushed = 0;
411 ao_usb_in_pending = 0;
412 ao_wakeup(&ao_usb_in_pending);
414 ao_usb_out_avail = 0;
415 ao_usb_configuration = 0;
418 ao_wakeup(&ao_usb_running);
421 static uint16_t control_count;
422 static uint16_t int_count;
423 static uint16_t in_count;
424 static uint16_t out_count;
425 static uint16_t reset_count;
427 /* The USB memory holds 16 bit values on 32 bit boundaries
428 * and must be accessed only in 32 bit units. Sigh.
432 ao_usb_write_byte(uint8_t byte, uint32_t *base, uint16_t offset)
436 *base = (*base & 0xff) | ((uint32_t) byte << 8);
438 *base = (*base & 0xff00) | byte;
443 ao_usb_write_short(uint16_t data, uint32_t *base, uint16_t offset)
445 base[offset>>1] = data;
449 ao_usb_write(const uint8_t *src, uint32_t *base, uint16_t bytes)
455 debug_data (" %02x %02x", src[0], src[1]);
456 ao_usb_write_short((uint16_t) ((uint16_t) (src[1] << 8) | (uint16_t) src[0]), base, offset);
462 debug_data (" %02x", src[0]);
463 ao_usb_write_byte(*src, base, offset);
467 static inline uint8_t
468 ao_usb_read_byte(uint32_t *base, uint16_t offset)
472 return (*base >> 8) & 0xff;
477 static inline uint16_t
478 ao_usb_read_short(uint32_t *base, uint16_t offset)
480 return (uint16_t) (base[offset>>1]);
484 ao_usb_read(uint8_t *dst, uint32_t *base, uint16_t offset, uint16_t bytes)
489 *dst++ = ao_usb_read_byte(base, offset++);
490 debug_data (" %02x", dst[-1]);
494 uint16_t s = ao_usb_read_short(base, offset);
495 dst[0] = (uint8_t) s;
496 dst[1] = (uint8_t) (s >> 8);
497 debug_data (" %02x %02x", dst[0], dst[1]);
503 *dst = ao_usb_read_byte(base, offset);
504 debug_data (" %02x", dst[0]);
508 /* Send an IN data packet */
510 ao_usb_ep0_flush(void)
514 /* Check to see if the endpoint is still busy */
515 if (ao_usb_epr_stat_tx(stm_usb.epr[0]) == STM_USB_EPR_STAT_TX_VALID) {
516 debug("EP0 not accepting IN data\n");
520 this_len = ao_usb_ep0_in_len;
521 if (this_len > AO_USB_CONTROL_SIZE)
522 this_len = AO_USB_CONTROL_SIZE;
524 if (this_len < AO_USB_CONTROL_SIZE)
525 ao_usb_ep0_state = AO_USB_EP0_IDLE;
527 ao_usb_ep0_in_len -= this_len;
529 debug_data ("Flush EP0 len %d:", this_len);
530 ao_usb_write(ao_usb_ep0_in_data, ao_usb_ep0_tx_buffer, this_len);
532 ao_usb_ep0_in_data += this_len;
534 /* Mark the endpoint as TX valid to send the packet */
535 ao_usb_bdt[AO_USB_CONTROL_EPR].single.count_tx = this_len;
536 ao_usb_set_stat_tx(AO_USB_CONTROL_EPR, STM_USB_EPR_STAT_TX_VALID);
537 debug ("queue tx. epr 0 now %08x\n", stm_usb.epr[AO_USB_CONTROL_EPR]);
540 /* Read data from the ep0 OUT fifo */
542 ao_usb_ep0_fill(void)
544 uint16_t len = ao_usb_bdt[0].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
546 if (len > ao_usb_ep0_out_len)
547 len = ao_usb_ep0_out_len;
548 ao_usb_ep0_out_len -= (uint8_t) len;
550 /* Pull all of the data out of the packet */
551 debug_data ("Fill EP0 len %d:", len);
552 ao_usb_read(ao_usb_ep0_out_data, ao_usb_ep0_rx_buffer, 0, len);
554 ao_usb_ep0_out_data += len;
557 ao_usb_set_stat_rx(0, STM_USB_EPR_STAT_RX_VALID);
561 ao_usb_ep0_in_reset(void)
563 ao_usb_ep0_in_data = ao_usb_ep0_in_buf;
564 ao_usb_ep0_in_len = 0;
568 ao_usb_ep0_in_queue_byte(uint8_t a)
570 if (ao_usb_ep0_in_len < sizeof (ao_usb_ep0_in_buf))
571 ao_usb_ep0_in_buf[ao_usb_ep0_in_len++] = a;
575 ao_usb_ep0_in_set(const uint8_t *data, uint8_t len)
577 ao_usb_ep0_in_data = data;
578 ao_usb_ep0_in_len = len;
582 ao_usb_ep0_out_set(uint8_t *data, uint8_t len)
584 ao_usb_ep0_out_data = data;
585 ao_usb_ep0_out_len = len;
589 ao_usb_ep0_in_start(uint16_t max)
591 /* Don't send more than asked for */
592 if (ao_usb_ep0_in_len > max)
593 ao_usb_ep0_in_len = (uint8_t) max;
597 struct ao_usb_line_coding ao_usb_line_coding = {115200, 0, 0, 8};
599 /* Walk through the list of descriptors and find a match
602 ao_usb_get_descriptor(uint16_t value, uint16_t length)
604 const uint8_t *descriptor;
605 uint8_t type = (uint8_t) (value >> 8);
606 uint8_t index = (uint8_t) value;
608 descriptor = ao_usb_descriptors;
609 while (descriptor[0] != 0) {
610 if (descriptor[1] == type && index-- == 0) {
612 if (type == AO_USB_DESC_CONFIGURATION)
617 len = (uint8_t) length;
618 ao_usb_ep0_in_set(descriptor, len);
621 descriptor += descriptor[0];
626 ao_usb_ep0_setup(void)
628 /* Pull the setup packet out of the fifo */
629 ao_usb_ep0_out_set((uint8_t *) &ao_usb_setup, 8);
631 if (ao_usb_ep0_out_len != 0) {
632 debug ("invalid setup packet length\n");
636 if ((ao_usb_setup.dir_type_recip & AO_USB_DIR_IN) || ao_usb_setup.length == 0)
637 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
639 ao_usb_ep0_state = AO_USB_EP0_DATA_OUT;
641 ao_usb_ep0_in_reset();
643 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_TYPE_MASK) {
644 case AO_USB_TYPE_STANDARD:
645 debug ("Standard setup packet\n");
646 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_RECIP_MASK) {
647 case AO_USB_RECIP_DEVICE:
648 debug ("Device setup packet\n");
649 switch(ao_usb_setup.request) {
650 case AO_USB_REQ_GET_STATUS:
651 debug ("get status\n");
652 ao_usb_ep0_in_queue_byte(0);
653 ao_usb_ep0_in_queue_byte(0);
655 case AO_USB_REQ_SET_ADDRESS:
656 debug ("set address %d\n", ao_usb_setup.value);
657 ao_usb_address = (uint8_t) ao_usb_setup.value;
658 ao_usb_address_pending = 1;
660 case AO_USB_REQ_GET_DESCRIPTOR:
661 debug ("get descriptor %d\n", ao_usb_setup.value);
662 ao_usb_get_descriptor(ao_usb_setup.value, ao_usb_setup.length);
664 case AO_USB_REQ_GET_CONFIGURATION:
665 debug ("get configuration %d\n", ao_usb_configuration);
666 ao_usb_ep0_in_queue_byte(ao_usb_configuration);
668 case AO_USB_REQ_SET_CONFIGURATION:
669 ao_usb_configuration = (uint8_t) ao_usb_setup.value;
670 debug ("set configuration %d\n", ao_usb_configuration);
671 ao_usb_set_configuration();
675 case AO_USB_RECIP_INTERFACE:
676 debug ("Interface setup packet\n");
677 switch(ao_usb_setup.request) {
678 case AO_USB_REQ_GET_STATUS:
679 ao_usb_ep0_in_queue_byte(0);
680 ao_usb_ep0_in_queue_byte(0);
682 case AO_USB_REQ_GET_INTERFACE:
683 ao_usb_ep0_in_queue_byte(0);
685 case AO_USB_REQ_SET_INTERFACE:
689 case AO_USB_RECIP_ENDPOINT:
690 debug ("Endpoint setup packet\n");
691 switch(ao_usb_setup.request) {
692 case AO_USB_REQ_GET_STATUS:
693 ao_usb_ep0_in_queue_byte(0);
694 ao_usb_ep0_in_queue_byte(0);
700 case AO_USB_TYPE_CLASS:
701 debug ("Class setup packet\n");
702 switch (ao_usb_setup.request) {
703 case AO_USB_SET_LINE_CODING:
704 debug ("set line coding\n");
705 ao_usb_ep0_out_set((uint8_t *) &ao_usb_line_coding, 7);
707 case AO_USB_GET_LINE_CODING:
708 debug ("get line coding\n");
709 ao_usb_ep0_in_set((const uint8_t *) &ao_usb_line_coding, 7);
711 case AO_USB_SET_CONTROL_LINE_STATE:
717 /* If we're not waiting to receive data from the host,
718 * queue an IN response
720 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
721 ao_usb_ep0_in_start(ao_usb_setup.length);
725 ao_usb_ep0_handle(uint8_t receive)
727 ao_usb_ep0_receive = 0;
728 if (receive & AO_USB_EP0_GOT_RESET) {
733 if (receive & AO_USB_EP0_GOT_SETUP) {
737 if (receive & AO_USB_EP0_GOT_RX_DATA) {
738 debug ("\tgot rx data\n");
739 if (ao_usb_ep0_state == AO_USB_EP0_DATA_OUT) {
741 if (ao_usb_ep0_out_len == 0) {
742 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
743 ao_usb_ep0_in_start(0);
747 if (receive & AO_USB_EP0_GOT_TX_ACK) {
748 debug ("\tgot tx ack\n");
750 #if HAS_FLIGHT && AO_USB_FORCE_IDLE
751 ao_flight_force_idle = 1;
753 /* Wait until the IN packet is received from addr 0
754 * before assigning our local address
756 if (ao_usb_address_pending)
757 ao_usb_set_address(ao_usb_address);
758 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
766 uint32_t istr = stm_usb.istr;
768 if (istr & (1 << STM_USB_ISTR_CTR)) {
769 uint8_t ep = istr & STM_USB_ISTR_EP_ID_MASK;
770 uint32_t epr, epr_write;
772 /* Preserve the SW write bits, don't mess with most HW writable bits,
773 * clear the CTR_RX and CTR_TX bits
775 epr = stm_usb.epr[ep];
777 epr_write &= STM_USB_EPR_PRESERVE_MASK;
778 epr_write |= STM_USB_EPR_INVARIANT;
779 epr_write &= ~(1UL << STM_USB_EPR_CTR_RX);
780 epr_write &= ~(1UL << STM_USB_EPR_CTR_TX);
781 stm_usb.epr[ep] = epr_write;
786 if (ao_usb_epr_ctr_rx(epr)) {
787 if (ao_usb_epr_setup(epr))
788 ao_usb_ep0_receive |= AO_USB_EP0_GOT_SETUP;
790 ao_usb_ep0_receive |= AO_USB_EP0_GOT_RX_DATA;
792 if (ao_usb_epr_ctr_tx(epr))
793 ao_usb_ep0_receive |= AO_USB_EP0_GOT_TX_ACK;
794 ao_usb_ep0_handle(ao_usb_ep0_receive);
798 if (ao_usb_epr_ctr_rx(epr)) {
799 _rx_dbg1("RX ISR", epr);
800 ao_usb_out_avail = 1;
801 _rx_dbg0("out avail set");
802 ao_wakeup(AO_USB_OUT_SLEEP_ADDR);
803 _rx_dbg0("stdin awoken");
808 _tx_dbg1("TX ISR", epr);
809 if (ao_usb_epr_ctr_tx(epr)) {
810 ao_usb_in_pending = 0;
811 ao_wakeup(&ao_usb_in_pending);
816 if (ao_usb_epr_ctr_tx(epr))
817 _ao_usb_set_stat_tx(AO_USB_INT_EPR, STM_USB_EPR_STAT_TX_NAK);
823 if (istr & (1 << STM_USB_ISTR_RESET)) {
825 stm_usb.istr &= ~(1UL << STM_USB_ISTR_RESET);
826 ao_usb_ep0_receive |= AO_USB_EP0_GOT_RESET;
827 ao_usb_ep0_handle(ao_usb_ep0_receive);
832 stm_usb_fs_wkup_isr(void)
834 /* USB wakeup, just clear the bit for now */
835 stm_usb.istr &= ~(1UL << STM_USB_ISTR_WKUP);
838 /* Queue the current IN buffer for transmission */
840 _ao_usb_in_send(void)
842 _tx_dbg0("in_send start");
843 debug ("send %d\n", ao_usb_tx_count);
844 while (ao_usb_in_pending)
845 ao_sleep(&ao_usb_in_pending);
846 ao_usb_in_pending = 1;
847 if (ao_usb_tx_count != AO_USB_IN_SIZE)
848 ao_usb_in_flushed = 1;
849 ao_usb_write(ao_usb_tx_buffer, ao_usb_in_tx_buffer, ao_usb_tx_count);
850 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = ao_usb_tx_count;
852 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
853 _tx_dbg0("in_send end");
856 /* Wait for a free IN buffer. Interrupts are blocked */
858 _ao_usb_in_wait(void)
861 /* Check if the current buffer is writable */
862 if (ao_usb_tx_count < AO_USB_IN_SIZE)
865 _tx_dbg0("in_wait top");
866 /* Wait for an IN buffer to be ready */
867 while (ao_usb_in_pending)
868 ao_sleep(&ao_usb_in_pending);
869 _tx_dbg0("in_wait bottom");
879 /* Anytime we've sent a character since
880 * the last time we flushed, we'll need
881 * to send a packet -- the only other time
882 * we would send a packet is when that
883 * packet was full, in which case we now
884 * want to send an empty packet
886 ao_arch_block_interrupts();
887 while (!ao_usb_in_flushed) {
888 _tx_dbg0("flush top");
890 _tx_dbg0("flush end");
892 ao_arch_release_interrupts();
896 ao_usb_putchar(char c)
901 ao_arch_block_interrupts();
904 ao_usb_in_flushed = 0;
905 ao_usb_tx_buffer[ao_usb_tx_count++] = (uint8_t) c;
907 /* Send the packet when full */
908 if (ao_usb_tx_count == AO_USB_IN_SIZE) {
909 _tx_dbg0("putchar full");
911 _tx_dbg0("putchar flushed");
913 ao_arch_release_interrupts();
917 _ao_usb_out_recv(void)
919 _rx_dbg0("out_recv top");
920 ao_usb_out_avail = 0;
922 ao_usb_rx_count = (uint8_t) (ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK);
924 _rx_dbg1("out_recv count", ao_usb_rx_count);
925 debug ("recv %d\n", ao_usb_rx_count);
926 debug_data("Fill OUT len %d:", ao_usb_rx_count);
927 ao_usb_read(ao_usb_rx_buffer, ao_usb_out_rx_buffer, 0, ao_usb_rx_count);
932 _ao_usb_set_stat_rx(AO_USB_OUT_EPR, STM_USB_EPR_STAT_RX_VALID);
936 _ao_usb_pollchar(void)
941 return AO_READ_AGAIN;
944 if (ao_usb_rx_pos != ao_usb_rx_count)
947 _rx_dbg0("poll check");
948 /* Check to see if a packet has arrived */
949 if (!ao_usb_out_avail) {
950 _rx_dbg0("poll none");
951 return AO_READ_AGAIN;
956 /* Pull a character out of the fifo */
957 c = ao_usb_rx_buffer[ao_usb_rx_pos++];
966 ao_arch_block_interrupts();
967 while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN)
968 ao_sleep(AO_USB_OUT_SLEEP_ADDR);
969 ao_arch_release_interrupts();
973 #ifndef HAS_USB_DISABLE
974 #define HAS_USB_DISABLE 1
981 ao_arch_block_interrupts();
982 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
985 /* Disable USB pull-up */
986 stm_syscfg.pmc &= ~(1UL << STM_SYSCFG_PMC_USB_PU);
988 /* Switch off the device */
989 stm_usb.cntr = (1 << STM_USB_CNTR_PDWN) | (1 << STM_USB_CNTR_FRES);
991 /* Disable the interface */
992 stm_rcc.apb1enr &= ~(1UL << STM_RCC_APB1ENR_USBEN);
993 ao_arch_release_interrupts();
1003 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN);
1005 /* Disable USB pull-up */
1006 stm_syscfg.pmc &= ~(1UL << STM_SYSCFG_PMC_USB_PU);
1008 /* Enable USB device */
1009 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USBEN);
1011 /* Do not touch the GPIOA configuration; USB takes priority
1012 * over GPIO on pins A11 and A12, but if you select alternate
1013 * input 10 (the documented correct selection), then USB is
1014 * pulled low and doesn't work at all
1017 ao_arch_block_interrupts();
1019 /* Route interrupts */
1020 stm_nvic_set_priority(STM_ISR_USB_LP_POS, AO_STM_NVIC_LOW_PRIORITY);
1021 stm_nvic_set_enable(STM_ISR_USB_LP_POS);
1023 ao_usb_configuration = 0;
1025 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1027 /* Clear the power down bit */
1030 /* Clear any spurious interrupts */
1033 debug ("ao_usb_enable\n");
1035 /* Enable interrupts */
1036 stm_usb.cntr = ((1 << STM_USB_CNTR_CTRM) |
1037 (0 << STM_USB_CNTR_PMAOVRM) |
1038 (0 << STM_USB_CNTR_ERRM) |
1039 (0 << STM_USB_CNTR_WKUPM) |
1040 (0 << STM_USB_CNTR_SUSPM) |
1041 (1 << STM_USB_CNTR_RESETM) |
1042 (0 << STM_USB_CNTR_SOFM) |
1043 (0 << STM_USB_CNTR_ESOFM) |
1044 (0 << STM_USB_CNTR_RESUME) |
1045 (0 << STM_USB_CNTR_FSUSP) |
1046 (0 << STM_USB_CNTR_LP_MODE) |
1047 (0 << STM_USB_CNTR_PDWN) |
1048 (0 << STM_USB_CNTR_FRES));
1050 ao_arch_release_interrupts();
1052 for (t = 0; t < 1000; t++)
1054 /* Enable USB pull-up */
1055 stm_syscfg.pmc |= (1 << STM_SYSCFG_PMC_USB_PU);
1059 struct ao_task ao_usb_echo_task;
1067 c = ao_usb_getchar();
1078 printf ("control: %d out: %d in: %d int: %d reset: %d\n",
1079 control_count, out_count, in_count, int_count, reset_count);
1082 const struct ao_cmds ao_usb_cmds[] = {
1083 { ao_usb_irq, "I\0Show USB interrupt counts" },
1093 debug ("ao_usb_init\n");
1094 ao_usb_ep0_state = AO_USB_EP0_IDLE;
1096 ao_add_task(&ao_usb_echo_task, ao_usb_echo, "usb echo");
1099 ao_cmd_register(&ao_usb_cmds[0]);
1103 ao_add_stdio(_ao_usb_pollchar, ao_usb_putchar, ao_usb_flush);
1108 #if TX_DBG || RX_DBG
1118 uint32_t in_pending;
1120 uint32_t in_flushed;
1130 #define NUM_USB_DBG 16
1132 static struct ao_usb_dbg dbg[NUM_USB_DBG];
1135 static void _dbg(int line, char *msg, uint32_t value)
1138 dbg[dbg_i].line = line;
1139 dbg[dbg_i].msg = msg;
1140 dbg[dbg_i].value = value;
1141 #if AO_NONMASK_INTERRUPT
1142 asm("mrs %0,basepri" : "=&r" (prival));
1144 asm("mrs %0,primask" : "=&r" (prival));
1146 dbg[dbg_i].prival = prival;
1148 dbg[dbg_i].in_count = in_count;
1149 dbg[dbg_i].in_epr = stm_usb.epr[AO_USB_IN_EPR];
1150 dbg[dbg_i].in_pending = ao_usb_in_pending;
1151 dbg[dbg_i].tx_count = ao_usb_tx_count;
1152 dbg[dbg_i].in_flushed = ao_usb_in_flushed;
1155 dbg[dbg_i].rx_count = ao_usb_rx_count;
1156 dbg[dbg_i].rx_pos = ao_usb_rx_pos;
1157 dbg[dbg_i].out_avail = ao_usb_out_avail;
1158 dbg[dbg_i].out_epr = stm_usb.epr[AO_USB_OUT_EPR];
1160 if (++dbg_i == NUM_USB_DBG)