2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 #include "ao_product.h"
23 #define USB_DEBUG_DATA 0
27 #define USE_USB_STDIO 1
31 #define AO_USB_OUT_SLEEP_ADDR (&ao_stdin_ready)
33 #define AO_USB_OUT_SLEEP_ADDR (&ao_usb_out_avail)
37 #define debug(format, args...) printf(format, ## args);
39 #define debug(format, args...)
43 #define debug_data(format, args...) printf(format, ## args);
45 #define debug_data(format, args...)
49 uint8_t dir_type_recip;
56 static uint8_t ao_usb_ep0_state;
58 /* Pending EP0 IN data */
59 static const uint8_t *ao_usb_ep0_in_data; /* Remaining data */
60 static uint8_t ao_usb_ep0_in_len; /* Remaining amount */
62 /* Temp buffer for smaller EP0 in data */
63 static uint8_t ao_usb_ep0_in_buf[2];
65 /* Pending EP0 OUT data */
66 static uint8_t *ao_usb_ep0_out_data;
67 static uint8_t ao_usb_ep0_out_len;
70 * Objects allocated in special USB memory
73 /* Buffer description tables */
74 static union stm_usb_bdt *ao_usb_bdt;
75 /* USB address of end of allocated storage */
76 static uint16_t ao_usb_sram_addr;
78 /* Pointer to ep0 tx/rx buffers in USB memory */
79 static uint32_t *ao_usb_ep0_tx_buffer;
80 static uint32_t *ao_usb_ep0_rx_buffer;
82 /* Pointer to bulk data tx/rx buffers in USB memory */
83 static uint32_t *ao_usb_in_tx_buffer;
84 static uint32_t *ao_usb_out_rx_buffer;
86 /* System ram shadow of USB buffer; writing individual bytes is
87 * too much of a pain (sigh) */
88 static uint8_t ao_usb_tx_buffer[AO_USB_IN_SIZE];
89 static uint8_t ao_usb_tx_count;
91 static uint8_t ao_usb_rx_buffer[AO_USB_OUT_SIZE];
92 static uint8_t ao_usb_rx_count, ao_usb_rx_pos;
95 * End point register indices
98 #define AO_USB_CONTROL_EPR 0
99 #define AO_USB_INT_EPR 1
100 #define AO_USB_OUT_EPR 2
101 #define AO_USB_IN_EPR 3
103 /* Marks when we don't need to send an IN packet.
104 * This happens only when the last IN packet is not full,
105 * otherwise the host will expect to keep seeing packets.
106 * Send a zero-length packet as required
108 static uint8_t ao_usb_in_flushed;
110 /* Marks when we have delivered an IN packet to the hardware
111 * and it has not been received yet. ao_sleep on this address
112 * to wait for it to be delivered.
114 static uint8_t ao_usb_in_pending;
116 /* Marks when an OUT packet has been received by the hardware
117 * but not pulled to the shadow buffer.
119 static uint8_t ao_usb_out_avail;
120 uint8_t ao_usb_running;
121 static uint8_t ao_usb_configuration;
123 #define AO_USB_EP0_GOT_RESET 1
124 #define AO_USB_EP0_GOT_SETUP 2
125 #define AO_USB_EP0_GOT_RX_DATA 4
126 #define AO_USB_EP0_GOT_TX_ACK 8
128 static uint8_t ao_usb_ep0_receive;
129 static uint8_t ao_usb_address;
130 static uint8_t ao_usb_address_pending;
132 static inline uint32_t set_toggle(uint32_t current_value,
134 uint32_t desired_value)
136 return (current_value ^ desired_value) & mask;
139 static inline uint32_t *ao_usb_packet_buffer_addr(uint16_t sram_addr)
141 return (uint32_t *) (stm_usb_sram + 2 * sram_addr);
144 static inline uint32_t ao_usb_epr_stat_rx(uint32_t epr) {
145 return (epr >> STM_USB_EPR_STAT_RX) & STM_USB_EPR_STAT_RX_MASK;
148 static inline uint32_t ao_usb_epr_stat_tx(uint32_t epr) {
149 return (epr >> STM_USB_EPR_STAT_TX) & STM_USB_EPR_STAT_TX_MASK;
152 static inline uint32_t ao_usb_epr_ctr_rx(uint32_t epr) {
153 return (epr >> STM_USB_EPR_CTR_RX) & 1;
156 static inline uint32_t ao_usb_epr_ctr_tx(uint32_t epr) {
157 return (epr >> STM_USB_EPR_CTR_TX) & 1;
160 static inline uint32_t ao_usb_epr_setup(uint32_t epr) {
161 return (epr >> STM_USB_EPR_SETUP) & 1;
164 static inline uint32_t ao_usb_epr_dtog_rx(uint32_t epr) {
165 return (epr >> STM_USB_EPR_DTOG_RX) & 1;
168 static inline uint32_t ao_usb_epr_dtog_tx(uint32_t epr) {
169 return (epr >> STM_USB_EPR_DTOG_TX) & 1;
173 * Set current device address and mark the
174 * interface as active
177 ao_usb_set_address(uint8_t address)
179 debug("ao_usb_set_address %02x\n", address);
180 stm_usb.daddr = (1 << STM_USB_DADDR_EF) | address;
181 ao_usb_address_pending = 0;
185 * Write these values to preserve register contents under HW changes
188 #define STM_USB_EPR_INVARIANT ((1 << STM_USB_EPR_CTR_RX) | \
189 (STM_USB_EPR_DTOG_RX_WRITE_INVARIANT << STM_USB_EPR_DTOG_RX) | \
190 (STM_USB_EPR_STAT_RX_WRITE_INVARIANT << STM_USB_EPR_STAT_RX) | \
191 (1 << STM_USB_EPR_CTR_TX) | \
192 (STM_USB_EPR_DTOG_TX_WRITE_INVARIANT << STM_USB_EPR_DTOG_TX) | \
193 (STM_USB_EPR_STAT_TX_WRITE_INVARIANT << STM_USB_EPR_STAT_TX))
195 #define STM_USB_EPR_INVARIANT_MASK ((1 << STM_USB_EPR_CTR_RX) | \
196 (STM_USB_EPR_DTOG_RX_MASK << STM_USB_EPR_DTOG_RX) | \
197 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX) | \
198 (1 << STM_USB_EPR_CTR_TX) | \
199 (STM_USB_EPR_DTOG_TX_MASK << STM_USB_EPR_DTOG_TX) | \
200 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX))
203 * These bits are purely under sw control, so preserve them in the
204 * register by re-writing what was read
206 #define STM_USB_EPR_PRESERVE_MASK ((STM_USB_EPR_EP_TYPE_MASK << STM_USB_EPR_EP_TYPE) | \
207 (1 << STM_USB_EPR_EP_KIND) | \
208 (STM_USB_EPR_EA_MASK << STM_USB_EPR_EA))
214 #define _tx_dbg0(msg) _dbg(__LINE__,msg,0)
215 #define _tx_dbg1(msg,value) _dbg(__LINE__,msg,value)
217 #define _tx_dbg0(msg)
218 #define _tx_dbg1(msg,value)
222 #define _rx_dbg0(msg) _dbg(__LINE__,msg,0)
223 #define _rx_dbg1(msg,value) _dbg(__LINE__,msg,value)
225 #define _rx_dbg0(msg)
226 #define _rx_dbg1(msg,value)
230 static void _dbg(int line, char *msg, uint32_t value);
234 * Set the state of the specified endpoint register to a new
235 * value. This is tricky because the bits toggle where the new
236 * value is one, and we need to write invariant values in other
237 * spots of the register. This hardware is strange...
240 _ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
242 uint32_t epr_write, epr_old;
244 _tx_dbg1("set_stat_tx top", stat_tx);
245 epr_old = epr_write = stm_usb.epr[ep];
246 epr_write &= STM_USB_EPR_PRESERVE_MASK;
247 epr_write |= STM_USB_EPR_INVARIANT;
248 epr_write |= set_toggle(epr_old,
249 STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX,
250 stat_tx << STM_USB_EPR_STAT_TX);
251 stm_usb.epr[ep] = epr_write;
252 _tx_dbg1("set_stat_tx bottom", epr_write);
256 ao_usb_set_stat_tx(int ep, uint32_t stat_tx)
258 ao_arch_block_interrupts();
259 _ao_usb_set_stat_tx(ep, stat_tx);
260 ao_arch_release_interrupts();
264 _ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
265 uint32_t epr_write, epr_old;
267 epr_write = epr_old = stm_usb.epr[ep];
268 epr_write &= STM_USB_EPR_PRESERVE_MASK;
269 epr_write |= STM_USB_EPR_INVARIANT;
270 epr_write |= set_toggle(epr_old,
271 STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX,
272 stat_rx << STM_USB_EPR_STAT_RX);
273 stm_usb.epr[ep] = epr_write;
277 ao_usb_set_stat_rx(int ep, uint32_t stat_rx) {
278 ao_arch_block_interrupts();
279 _ao_usb_set_stat_rx(ep, stat_rx);
280 ao_arch_release_interrupts();
284 * Set just endpoint 0, for use during startup
288 ao_usb_init_ep(uint8_t ep, uint32_t addr, uint32_t type, uint32_t stat_rx, uint32_t stat_tx)
291 ao_arch_block_interrupts();
292 epr = stm_usb.epr[ep];
293 epr = ((0 << STM_USB_EPR_CTR_RX) |
294 (epr & (1 << STM_USB_EPR_DTOG_RX)) |
296 (STM_USB_EPR_STAT_RX_MASK << STM_USB_EPR_STAT_RX),
297 (stat_rx << STM_USB_EPR_STAT_RX)) |
298 (type << STM_USB_EPR_EP_TYPE) |
299 (0 << STM_USB_EPR_EP_KIND) |
300 (0 << STM_USB_EPR_CTR_TX) |
301 (epr & (1 << STM_USB_EPR_DTOG_TX)) |
303 (STM_USB_EPR_STAT_TX_MASK << STM_USB_EPR_STAT_TX),
304 (stat_tx << STM_USB_EPR_STAT_TX)) |
305 (addr << STM_USB_EPR_EA));
306 stm_usb.epr[ep] = epr;
307 ao_arch_release_interrupts();
308 debug ("writing epr[%d] 0x%08x wrote 0x%08x\n",
309 ep, epr, stm_usb.epr[ep]);
317 ao_usb_sram_addr = 0;
319 /* buffer table is at the start of USB memory */
321 ao_usb_bdt = (void *) stm_usb_sram;
323 ao_usb_sram_addr += 8 * STM_USB_BDT_SIZE;
325 /* Set up EP 0 - a Control end point with 32 bytes of in and out buffers */
327 ao_usb_bdt[0].single.addr_tx = ao_usb_sram_addr;
328 ao_usb_bdt[0].single.count_tx = 0;
329 ao_usb_ep0_tx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
330 ao_usb_sram_addr += AO_USB_CONTROL_SIZE;
332 ao_usb_bdt[0].single.addr_rx = ao_usb_sram_addr;
333 ao_usb_bdt[0].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
334 (((AO_USB_CONTROL_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
335 ao_usb_ep0_rx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
336 ao_usb_sram_addr += AO_USB_CONTROL_SIZE;
338 ao_usb_init_ep(AO_USB_CONTROL_EPR, AO_USB_CONTROL_EP,
339 STM_USB_EPR_EP_TYPE_CONTROL,
340 STM_USB_EPR_STAT_RX_VALID,
341 STM_USB_EPR_STAT_TX_NAK);
343 /* Clear all of the other endpoints */
344 for (e = 1; e < 8; e++) {
346 STM_USB_EPR_EP_TYPE_CONTROL,
347 STM_USB_EPR_STAT_RX_DISABLED,
348 STM_USB_EPR_STAT_TX_DISABLED);
351 ao_usb_set_address(0);
355 /* Reset our internal state
358 ao_usb_ep0_state = AO_USB_EP0_IDLE;
360 ao_usb_ep0_in_data = NULL;
361 ao_usb_ep0_in_len = 0;
363 ao_usb_ep0_out_data = 0;
364 ao_usb_ep0_out_len = 0;
368 ao_usb_set_configuration(void)
370 debug ("ao_usb_set_configuration\n");
372 /* Set up the INT end point */
373 ao_usb_bdt[AO_USB_INT_EPR].single.addr_tx = ao_usb_sram_addr;
374 ao_usb_bdt[AO_USB_INT_EPR].single.count_tx = 0;
375 ao_usb_in_tx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
376 ao_usb_sram_addr += AO_USB_INT_SIZE;
378 ao_usb_init_ep(AO_USB_INT_EPR,
380 STM_USB_EPR_EP_TYPE_INTERRUPT,
381 STM_USB_EPR_STAT_RX_DISABLED,
382 STM_USB_EPR_STAT_TX_NAK);
384 /* Set up the OUT end point */
385 ao_usb_bdt[AO_USB_OUT_EPR].single.addr_rx = ao_usb_sram_addr;
386 ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx = ((1 << STM_USB_BDT_COUNT_RX_BL_SIZE) |
387 (((AO_USB_OUT_SIZE / 32) - 1) << STM_USB_BDT_COUNT_RX_NUM_BLOCK));
388 ao_usb_out_rx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
389 ao_usb_sram_addr += AO_USB_OUT_SIZE;
391 ao_usb_init_ep(AO_USB_OUT_EPR,
393 STM_USB_EPR_EP_TYPE_BULK,
394 STM_USB_EPR_STAT_RX_VALID,
395 STM_USB_EPR_STAT_TX_DISABLED);
397 /* Set up the IN end point */
398 ao_usb_bdt[AO_USB_IN_EPR].single.addr_tx = ao_usb_sram_addr;
399 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = 0;
400 ao_usb_in_tx_buffer = ao_usb_packet_buffer_addr(ao_usb_sram_addr);
401 ao_usb_sram_addr += AO_USB_IN_SIZE;
403 ao_usb_init_ep(AO_USB_IN_EPR,
405 STM_USB_EPR_EP_TYPE_BULK,
406 STM_USB_EPR_STAT_RX_DISABLED,
407 STM_USB_EPR_STAT_TX_NAK);
409 ao_usb_in_flushed = 0;
410 ao_usb_in_pending = 0;
411 ao_wakeup(&ao_usb_in_pending);
413 ao_usb_out_avail = 0;
414 ao_usb_configuration = 0;
417 ao_wakeup(&ao_usb_running);
420 static uint16_t control_count;
421 static uint16_t int_count;
422 static uint16_t in_count;
423 static uint16_t out_count;
424 static uint16_t reset_count;
426 /* The USB memory holds 16 bit values on 32 bit boundaries
427 * and must be accessed only in 32 bit units. Sigh.
431 ao_usb_write_byte(uint8_t byte, uint32_t *base, uint16_t offset)
435 *base = (*base & 0xff) | ((uint32_t) byte << 8);
437 *base = (*base & 0xff00) | byte;
442 ao_usb_write_short(uint16_t data, uint32_t *base, uint16_t offset)
444 base[offset>>1] = data;
448 ao_usb_write(const uint8_t *src, uint32_t *base, uint16_t offset, uint16_t bytes)
453 debug_data (" %02x", src[0]);
454 ao_usb_write_byte(*src++, base, offset++);
458 debug_data (" %02x %02x", src[0], src[1]);
459 ao_usb_write_short((src[1] << 8) | src[0], base, offset);
465 debug_data (" %02x", src[0]);
466 ao_usb_write_byte(*src, base, offset);
470 static inline uint8_t
471 ao_usb_read_byte(uint32_t *base, uint16_t offset)
475 return (*base >> 8) & 0xff;
480 static inline uint16_t
481 ao_usb_read_short(uint32_t *base, uint16_t offset)
483 return base[offset>>1];
487 ao_usb_read(uint8_t *dst, uint32_t *base, uint16_t offset, uint16_t bytes)
492 *dst++ = ao_usb_read_byte(base, offset++);
493 debug_data (" %02x", dst[-1]);
497 uint16_t s = ao_usb_read_short(base, offset);
500 debug_data (" %02x %02x", dst[0], dst[1]);
506 *dst = ao_usb_read_byte(base, offset);
507 debug_data (" %02x", dst[0]);
511 /* Send an IN data packet */
513 ao_usb_ep0_flush(void)
517 /* Check to see if the endpoint is still busy */
518 if (ao_usb_epr_stat_tx(stm_usb.epr[0]) == STM_USB_EPR_STAT_TX_VALID) {
519 debug("EP0 not accepting IN data\n");
523 this_len = ao_usb_ep0_in_len;
524 if (this_len > AO_USB_CONTROL_SIZE)
525 this_len = AO_USB_CONTROL_SIZE;
527 if (this_len < AO_USB_CONTROL_SIZE)
528 ao_usb_ep0_state = AO_USB_EP0_IDLE;
530 ao_usb_ep0_in_len -= this_len;
532 debug_data ("Flush EP0 len %d:", this_len);
533 ao_usb_write(ao_usb_ep0_in_data, ao_usb_ep0_tx_buffer, 0, this_len);
535 ao_usb_ep0_in_data += this_len;
537 /* Mark the endpoint as TX valid to send the packet */
538 ao_usb_bdt[AO_USB_CONTROL_EPR].single.count_tx = this_len;
539 ao_usb_set_stat_tx(AO_USB_CONTROL_EPR, STM_USB_EPR_STAT_TX_VALID);
540 debug ("queue tx. epr 0 now %08x\n", stm_usb.epr[AO_USB_CONTROL_EPR]);
543 /* Read data from the ep0 OUT fifo */
545 ao_usb_ep0_fill(void)
547 uint16_t len = ao_usb_bdt[0].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
549 if (len > ao_usb_ep0_out_len)
550 len = ao_usb_ep0_out_len;
551 ao_usb_ep0_out_len -= len;
553 /* Pull all of the data out of the packet */
554 debug_data ("Fill EP0 len %d:", len);
555 ao_usb_read(ao_usb_ep0_out_data, ao_usb_ep0_rx_buffer, 0, len);
557 ao_usb_ep0_out_data += len;
560 ao_usb_set_stat_rx(0, STM_USB_EPR_STAT_RX_VALID);
564 ao_usb_ep0_in_reset(void)
566 ao_usb_ep0_in_data = ao_usb_ep0_in_buf;
567 ao_usb_ep0_in_len = 0;
571 ao_usb_ep0_in_queue_byte(uint8_t a)
573 if (ao_usb_ep0_in_len < sizeof (ao_usb_ep0_in_buf))
574 ao_usb_ep0_in_buf[ao_usb_ep0_in_len++] = a;
578 ao_usb_ep0_in_set(const uint8_t *data, uint8_t len)
580 ao_usb_ep0_in_data = data;
581 ao_usb_ep0_in_len = len;
585 ao_usb_ep0_out_set(uint8_t *data, uint8_t len)
587 ao_usb_ep0_out_data = data;
588 ao_usb_ep0_out_len = len;
592 ao_usb_ep0_in_start(uint16_t max)
594 /* Don't send more than asked for */
595 if (ao_usb_ep0_in_len > max)
596 ao_usb_ep0_in_len = max;
600 static struct ao_usb_line_coding ao_usb_line_coding = {115200, 0, 0, 8};
602 /* Walk through the list of descriptors and find a match
605 ao_usb_get_descriptor(uint16_t value, uint16_t length)
607 const uint8_t *descriptor;
608 uint8_t type = value >> 8;
609 uint8_t index = value;
611 descriptor = ao_usb_descriptors;
612 while (descriptor[0] != 0) {
613 if (descriptor[1] == type && index-- == 0) {
615 if (type == AO_USB_DESC_CONFIGURATION)
621 ao_usb_ep0_in_set(descriptor, len);
624 descriptor += descriptor[0];
629 ao_usb_ep0_setup(void)
631 /* Pull the setup packet out of the fifo */
632 ao_usb_ep0_out_set((uint8_t *) &ao_usb_setup, 8);
634 if (ao_usb_ep0_out_len != 0) {
635 debug ("invalid setup packet length\n");
639 if ((ao_usb_setup.dir_type_recip & AO_USB_DIR_IN) || ao_usb_setup.length == 0)
640 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
642 ao_usb_ep0_state = AO_USB_EP0_DATA_OUT;
644 ao_usb_ep0_in_reset();
646 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_TYPE_MASK) {
647 case AO_USB_TYPE_STANDARD:
648 debug ("Standard setup packet\n");
649 switch(ao_usb_setup.dir_type_recip & AO_USB_SETUP_RECIP_MASK) {
650 case AO_USB_RECIP_DEVICE:
651 debug ("Device setup packet\n");
652 switch(ao_usb_setup.request) {
653 case AO_USB_REQ_GET_STATUS:
654 debug ("get status\n");
655 ao_usb_ep0_in_queue_byte(0);
656 ao_usb_ep0_in_queue_byte(0);
658 case AO_USB_REQ_SET_ADDRESS:
659 debug ("set address %d\n", ao_usb_setup.value);
660 ao_usb_address = ao_usb_setup.value;
661 ao_usb_address_pending = 1;
663 case AO_USB_REQ_GET_DESCRIPTOR:
664 debug ("get descriptor %d\n", ao_usb_setup.value);
665 ao_usb_get_descriptor(ao_usb_setup.value, ao_usb_setup.length);
667 case AO_USB_REQ_GET_CONFIGURATION:
668 debug ("get configuration %d\n", ao_usb_configuration);
669 ao_usb_ep0_in_queue_byte(ao_usb_configuration);
671 case AO_USB_REQ_SET_CONFIGURATION:
672 ao_usb_configuration = ao_usb_setup.value;
673 debug ("set configuration %d\n", ao_usb_configuration);
674 ao_usb_set_configuration();
678 case AO_USB_RECIP_INTERFACE:
679 debug ("Interface setup packet\n");
680 switch(ao_usb_setup.request) {
681 case AO_USB_REQ_GET_STATUS:
682 ao_usb_ep0_in_queue_byte(0);
683 ao_usb_ep0_in_queue_byte(0);
685 case AO_USB_REQ_GET_INTERFACE:
686 ao_usb_ep0_in_queue_byte(0);
688 case AO_USB_REQ_SET_INTERFACE:
692 case AO_USB_RECIP_ENDPOINT:
693 debug ("Endpoint setup packet\n");
694 switch(ao_usb_setup.request) {
695 case AO_USB_REQ_GET_STATUS:
696 ao_usb_ep0_in_queue_byte(0);
697 ao_usb_ep0_in_queue_byte(0);
703 case AO_USB_TYPE_CLASS:
704 debug ("Class setup packet\n");
705 switch (ao_usb_setup.request) {
706 case AO_USB_SET_LINE_CODING:
707 debug ("set line coding\n");
708 ao_usb_ep0_out_set((uint8_t *) &ao_usb_line_coding, 7);
710 case AO_USB_GET_LINE_CODING:
711 debug ("get line coding\n");
712 ao_usb_ep0_in_set((const uint8_t *) &ao_usb_line_coding, 7);
714 case AO_USB_SET_CONTROL_LINE_STATE:
720 /* If we're not waiting to receive data from the host,
721 * queue an IN response
723 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
724 ao_usb_ep0_in_start(ao_usb_setup.length);
728 ao_usb_ep0_handle(uint8_t receive)
730 ao_usb_ep0_receive = 0;
731 if (receive & AO_USB_EP0_GOT_RESET) {
736 if (receive & AO_USB_EP0_GOT_SETUP) {
740 if (receive & AO_USB_EP0_GOT_RX_DATA) {
741 debug ("\tgot rx data\n");
742 if (ao_usb_ep0_state == AO_USB_EP0_DATA_OUT) {
744 if (ao_usb_ep0_out_len == 0) {
745 ao_usb_ep0_state = AO_USB_EP0_DATA_IN;
746 ao_usb_ep0_in_start(0);
750 if (receive & AO_USB_EP0_GOT_TX_ACK) {
751 debug ("\tgot tx ack\n");
753 #if HAS_FLIGHT && AO_USB_FORCE_IDLE
754 ao_flight_force_idle = 1;
756 /* Wait until the IN packet is received from addr 0
757 * before assigning our local address
759 if (ao_usb_address_pending)
760 ao_usb_set_address(ao_usb_address);
761 if (ao_usb_ep0_state == AO_USB_EP0_DATA_IN)
769 uint32_t istr = stm_usb.istr;
771 if (istr & (1 << STM_USB_ISTR_CTR)) {
772 uint8_t ep = istr & STM_USB_ISTR_EP_ID_MASK;
773 uint32_t epr, epr_write;
775 /* Preserve the SW write bits, don't mess with most HW writable bits,
776 * clear the CTR_RX and CTR_TX bits
778 epr = stm_usb.epr[ep];
780 epr_write &= STM_USB_EPR_PRESERVE_MASK;
781 epr_write |= STM_USB_EPR_INVARIANT;
782 epr_write &= ~(1 << STM_USB_EPR_CTR_RX);
783 epr_write &= ~(1 << STM_USB_EPR_CTR_TX);
784 stm_usb.epr[ep] = epr_write;
789 if (ao_usb_epr_ctr_rx(epr)) {
790 if (ao_usb_epr_setup(epr))
791 ao_usb_ep0_receive |= AO_USB_EP0_GOT_SETUP;
793 ao_usb_ep0_receive |= AO_USB_EP0_GOT_RX_DATA;
795 if (ao_usb_epr_ctr_tx(epr))
796 ao_usb_ep0_receive |= AO_USB_EP0_GOT_TX_ACK;
797 ao_usb_ep0_handle(ao_usb_ep0_receive);
801 if (ao_usb_epr_ctr_rx(epr)) {
802 _rx_dbg1("RX ISR", epr);
803 ao_usb_out_avail = 1;
804 _rx_dbg0("out avail set");
805 ao_wakeup(AO_USB_OUT_SLEEP_ADDR);
806 _rx_dbg0("stdin awoken");
811 _tx_dbg1("TX ISR", epr);
812 if (ao_usb_epr_ctr_tx(epr)) {
813 ao_usb_in_pending = 0;
814 ao_wakeup(&ao_usb_in_pending);
819 if (ao_usb_epr_ctr_tx(epr))
820 _ao_usb_set_stat_tx(AO_USB_INT_EPR, STM_USB_EPR_STAT_TX_NAK);
826 if (istr & (1 << STM_USB_ISTR_RESET)) {
828 stm_usb.istr &= ~(1 << STM_USB_ISTR_RESET);
829 ao_usb_ep0_receive |= AO_USB_EP0_GOT_RESET;
830 ao_usb_ep0_handle(ao_usb_ep0_receive);
835 stm_usb_fs_wkup(void)
837 /* USB wakeup, just clear the bit for now */
838 stm_usb.istr &= ~(1 << STM_USB_ISTR_WKUP);
841 /* Queue the current IN buffer for transmission */
843 _ao_usb_in_send(void)
845 _tx_dbg0("in_send start");
846 debug ("send %d\n", ao_usb_tx_count);
847 while (ao_usb_in_pending)
848 ao_sleep(&ao_usb_in_pending);
849 ao_usb_in_pending = 1;
850 if (ao_usb_tx_count != AO_USB_IN_SIZE)
851 ao_usb_in_flushed = 1;
852 ao_usb_write(ao_usb_tx_buffer, ao_usb_in_tx_buffer, 0, ao_usb_tx_count);
853 ao_usb_bdt[AO_USB_IN_EPR].single.count_tx = ao_usb_tx_count;
855 _ao_usb_set_stat_tx(AO_USB_IN_EPR, STM_USB_EPR_STAT_TX_VALID);
856 _tx_dbg0("in_send end");
859 /* Wait for a free IN buffer. Interrupts are blocked */
861 _ao_usb_in_wait(void)
864 /* Check if the current buffer is writable */
865 if (ao_usb_tx_count < AO_USB_IN_SIZE)
868 _tx_dbg0("in_wait top");
869 /* Wait for an IN buffer to be ready */
870 while (ao_usb_in_pending)
871 ao_sleep(&ao_usb_in_pending);
872 _tx_dbg0("in_wait bottom");
882 /* Anytime we've sent a character since
883 * the last time we flushed, we'll need
884 * to send a packet -- the only other time
885 * we would send a packet is when that
886 * packet was full, in which case we now
887 * want to send an empty packet
889 ao_arch_block_interrupts();
890 while (!ao_usb_in_flushed) {
891 _tx_dbg0("flush top");
893 _tx_dbg0("flush end");
895 ao_arch_release_interrupts();
899 ao_usb_putchar(char c)
904 ao_arch_block_interrupts();
907 ao_usb_in_flushed = 0;
908 ao_usb_tx_buffer[ao_usb_tx_count++] = (uint8_t) c;
910 /* Send the packet when full */
911 if (ao_usb_tx_count == AO_USB_IN_SIZE) {
912 _tx_dbg0("putchar full");
914 _tx_dbg0("putchar flushed");
916 ao_arch_release_interrupts();
920 _ao_usb_out_recv(void)
922 _rx_dbg0("out_recv top");
923 ao_usb_out_avail = 0;
925 ao_usb_rx_count = ao_usb_bdt[AO_USB_OUT_EPR].single.count_rx & STM_USB_BDT_COUNT_RX_COUNT_RX_MASK;
927 _rx_dbg1("out_recv count", ao_usb_rx_count);
928 debug ("recv %d\n", ao_usb_rx_count);
929 debug_data("Fill OUT len %d:", ao_usb_rx_count);
930 ao_usb_read(ao_usb_rx_buffer, ao_usb_out_rx_buffer, 0, ao_usb_rx_count);
935 _ao_usb_set_stat_rx(AO_USB_OUT_EPR, STM_USB_EPR_STAT_RX_VALID);
939 _ao_usb_pollchar(void)
944 return AO_READ_AGAIN;
947 if (ao_usb_rx_pos != ao_usb_rx_count)
950 _rx_dbg0("poll check");
951 /* Check to see if a packet has arrived */
952 if (!ao_usb_out_avail) {
953 _rx_dbg0("poll none");
954 return AO_READ_AGAIN;
959 /* Pull a character out of the fifo */
960 c = ao_usb_rx_buffer[ao_usb_rx_pos++];
969 ao_arch_block_interrupts();
970 while ((c = _ao_usb_pollchar()) == AO_READ_AGAIN)
971 ao_sleep(AO_USB_OUT_SLEEP_ADDR);
972 ao_arch_release_interrupts();
979 ao_arch_block_interrupts();
980 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
983 /* Disable USB pull-up */
984 stm_syscfg.pmc &= ~(1 << STM_SYSCFG_PMC_USB_PU);
986 /* Switch off the device */
987 stm_usb.cntr = (1 << STM_USB_CNTR_PDWN) | (1 << STM_USB_CNTR_FRES);
989 /* Disable the interface */
990 stm_rcc.apb1enr &= ~(1 << STM_RCC_APB1ENR_USBEN);
991 ao_arch_release_interrupts();
1000 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_SYSCFGEN);
1002 /* Disable USB pull-up */
1003 stm_syscfg.pmc &= ~(1 << STM_SYSCFG_PMC_USB_PU);
1005 /* Enable USB device */
1006 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_USBEN);
1008 /* Do not touch the GPIOA configuration; USB takes priority
1009 * over GPIO on pins A11 and A12, but if you select alternate
1010 * input 10 (the documented correct selection), then USB is
1011 * pulled low and doesn't work at all
1014 ao_arch_block_interrupts();
1016 /* Route interrupts */
1017 stm_nvic_set_priority(STM_ISR_USB_LP_POS, 3);
1018 stm_nvic_set_enable(STM_ISR_USB_LP_POS);
1020 ao_usb_configuration = 0;
1022 stm_usb.cntr = (1 << STM_USB_CNTR_FRES);
1024 /* Clear the power down bit */
1027 /* Clear any spurious interrupts */
1030 debug ("ao_usb_enable\n");
1032 /* Enable interrupts */
1033 stm_usb.cntr = ((1 << STM_USB_CNTR_CTRM) |
1034 (0 << STM_USB_CNTR_PMAOVRM) |
1035 (0 << STM_USB_CNTR_ERRM) |
1036 (0 << STM_USB_CNTR_WKUPM) |
1037 (0 << STM_USB_CNTR_SUSPM) |
1038 (1 << STM_USB_CNTR_RESETM) |
1039 (0 << STM_USB_CNTR_SOFM) |
1040 (0 << STM_USB_CNTR_ESOFM) |
1041 (0 << STM_USB_CNTR_RESUME) |
1042 (0 << STM_USB_CNTR_FSUSP) |
1043 (0 << STM_USB_CNTR_LP_MODE) |
1044 (0 << STM_USB_CNTR_PDWN) |
1045 (0 << STM_USB_CNTR_FRES));
1047 ao_arch_release_interrupts();
1049 for (t = 0; t < 1000; t++)
1051 /* Enable USB pull-up */
1052 stm_syscfg.pmc |= (1 << STM_SYSCFG_PMC_USB_PU);
1056 struct ao_task ao_usb_echo_task;
1064 c = ao_usb_getchar();
1075 printf ("control: %d out: %d in: %d int: %d reset: %d\n",
1076 control_count, out_count, in_count, int_count, reset_count);
1079 __code struct ao_cmds ao_usb_cmds[] = {
1080 { ao_usb_irq, "I\0Show USB interrupt counts" },
1090 debug ("ao_usb_init\n");
1091 ao_usb_ep0_state = AO_USB_EP0_IDLE;
1093 ao_add_task(&ao_usb_echo_task, ao_usb_echo, "usb echo");
1096 ao_cmd_register(&ao_usb_cmds[0]);
1100 ao_add_stdio(_ao_usb_pollchar, ao_usb_putchar, ao_usb_flush);
1105 #if TX_DBG || RX_DBG
1115 uint32_t in_pending;
1117 uint32_t in_flushed;
1127 #define NUM_USB_DBG 128
1129 static struct ao_usb_dbg dbg[128];
1132 static void _dbg(int line, char *msg, uint32_t value)
1135 dbg[dbg_i].line = line;
1136 dbg[dbg_i].msg = msg;
1137 dbg[dbg_i].value = value;
1138 asm("mrs %0,primask" : "=&r" (primask));
1139 dbg[dbg_i].primask = primask;
1141 dbg[dbg_i].in_count = in_count;
1142 dbg[dbg_i].in_epr = stm_usb.epr[AO_USB_IN_EPR];
1143 dbg[dbg_i].in_pending = ao_usb_in_pending;
1144 dbg[dbg_i].tx_count = ao_usb_tx_count;
1145 dbg[dbg_i].in_flushed = ao_usb_in_flushed;
1148 dbg[dbg_i].rx_count = ao_usb_rx_count;
1149 dbg[dbg_i].rx_pos = ao_usb_rx_pos;
1150 dbg[dbg_i].out_avail = ao_usb_out_avail;
1151 dbg[dbg_i].out_epr = stm_usb.epr[AO_USB_OUT_EPR];
1153 if (++dbg_i == NUM_USB_DBG)