2 * Copyright © 2015 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
22 static uint8_t pwm_running;
24 static uint16_t pwm_value[NUM_PWM];
29 if (pwm_running++ == 0) {
30 struct stm_tim234 *tim = &AO_PWM_TIMER;
36 tim->arr = PWM_MAX - 1; /* turn on the timer */
37 tim->cr1 = ((STM_TIM234_CR1_CKD_1 << STM_TIM234_CR1_CKD) |
38 (0 << STM_TIM234_CR1_ARPE) |
39 (STM_TIM234_CR1_CMS_EDGE << STM_TIM234_CR1_CMS) |
40 (STM_TIM234_CR1_DIR_UP << STM_TIM234_CR1_DIR) |
41 (0 << STM_TIM234_CR1_OPM) |
42 (0 << STM_TIM234_CR1_URS) |
43 (0 << STM_TIM234_CR1_UDIS) |
44 (1 << STM_TIM234_CR1_CEN));
46 /* Set the timer running */
47 tim->egr = (1 << STM_TIM234_EGR_UG);
54 if (--pwm_running == 0) {
55 struct stm_tim234 *tim = &AO_PWM_TIMER;
58 tim->cr1 = ((STM_TIM234_CR1_CKD_1 << STM_TIM234_CR1_CKD) |
59 (0 << STM_TIM234_CR1_ARPE) |
60 (STM_TIM234_CR1_CMS_EDGE << STM_TIM234_CR1_CMS) |
61 (STM_TIM234_CR1_DIR_UP << STM_TIM234_CR1_DIR) |
62 (0 << STM_TIM234_CR1_OPM) |
63 (0 << STM_TIM234_CR1_URS) |
64 (0 << STM_TIM234_CR1_UDIS) |
65 (0 << STM_TIM234_CR1_CEN));
68 tim->egr = (1 << STM_TIM234_EGR_UG);
73 ao_pwm_set(uint8_t pwm, uint16_t value)
75 struct stm_tim234 *tim = &AO_PWM_TIMER;
80 if (pwm_value[pwm] == 0)
98 if (pwm_value[pwm] != 0)
101 pwm_value[pwm] = value;
110 ch = (uint8_t) ao_cmd_decimal();
111 val = (uint16_t) ao_cmd_decimal();
112 if (ao_cmd_status != ao_cmd_success)
115 printf("Set channel %d to %d\n", ch, val);
119 static const struct ao_cmds ao_pwm_cmds[] = {
120 { ao_pwm_cmd, "P <ch> <val>\0Set PWM ch to val" },
127 struct stm_tim234 *tim = &AO_PWM_TIMER;
129 stm_rcc.apb1enr |= (1 << AO_PWM_TIMER_ENABLE);
132 tim->psc = AO_PWM_TIMER_SCALE - 1;
134 tim->ccer = ((1 << STM_TIM234_CCER_CC1E) |
135 (0 << STM_TIM234_CCER_CC1P) |
136 (1 << STM_TIM234_CCER_CC2E) |
137 (0 << STM_TIM234_CCER_CC2P) |
138 (1 << STM_TIM234_CCER_CC3E) |
139 (0 << STM_TIM234_CCER_CC3P) |
140 (1 << STM_TIM234_CCER_CC4E) |
141 (0 << STM_TIM234_CCER_CC4P));
143 tim->ccmr1 = ((0 << STM_TIM234_CCMR1_OC2CE) |
144 (STM_TIM234_CCMR1_OC2M_PWM_MODE_1 << STM_TIM234_CCMR1_OC2M) |
145 (0 << STM_TIM234_CCMR1_OC2PE) |
146 (0 << STM_TIM234_CCMR1_OC2FE) |
147 (STM_TIM234_CCMR1_CC2S_OUTPUT << STM_TIM234_CCMR1_CC2S) |
149 (0 << STM_TIM234_CCMR1_OC1CE) |
150 (STM_TIM234_CCMR1_OC1M_PWM_MODE_1 << STM_TIM234_CCMR1_OC1M) |
151 (0 << STM_TIM234_CCMR1_OC1PE) |
152 (0 << STM_TIM234_CCMR1_OC1FE) |
153 (STM_TIM234_CCMR1_CC1S_OUTPUT << STM_TIM234_CCMR1_CC1S));
156 tim->ccmr2 = ((0 << STM_TIM234_CCMR2_OC4CE) |
157 (STM_TIM234_CCMR2_OC4M_PWM_MODE_1 << STM_TIM234_CCMR2_OC4M) |
158 (0 << STM_TIM234_CCMR2_OC4PE) |
159 (0 << STM_TIM234_CCMR2_OC4FE) |
160 (STM_TIM234_CCMR2_CC4S_OUTPUT << STM_TIM234_CCMR2_CC4S) |
162 (0 << STM_TIM234_CCMR2_OC3CE) |
163 (STM_TIM234_CCMR2_OC3M_PWM_MODE_1 << STM_TIM234_CCMR2_OC3M) |
164 (0 << STM_TIM234_CCMR2_OC3PE) |
165 (0 << STM_TIM234_CCMR2_OC3FE) |
166 (STM_TIM234_CCMR2_CC3S_OUTPUT << STM_TIM234_CCMR2_CC3S));
172 tim->cr2 = ((0 << STM_TIM234_CR2_TI1S) |
173 (STM_TIM234_CR2_MMS_RESET<< STM_TIM234_CR2_MMS) |
174 (0 << STM_TIM234_CR2_CCDS));
176 stm_afr_set(AO_PWM_0_GPIO, AO_PWM_0_PIN, STM_AFR_AF2);
177 stm_ospeedr_set(AO_PWM_0_GPIO, AO_PWM_0_PIN, STM_OSPEEDR_40MHz);
179 stm_afr_set(AO_PWM_1_GPIO, AO_PWM_1_PIN, STM_AFR_AF2);
180 stm_ospeedr_set(AO_PWM_1_GPIO, AO_PWM_1_PIN, STM_OSPEEDR_40MHz);
183 stm_afr_set(AO_PWM_2_GPIO, AO_PWM_2_PIN, STM_AFR_AF2);
184 stm_ospeedr_set(AO_PWM_2_GPIO, AO_PWM_2_PIN, STM_OSPEEDR_40MHz);
187 stm_afr_set(AO_PWM_3_GPIO, AO_PWM_3_PIN, STM_AFR_AF2);
188 stm_ospeedr_set(AO_PWM_3_GPIO, AO_PWM_3_PIN, STM_OSPEEDR_40MHz);
190 ao_cmd_register(&ao_pwm_cmds[0]);