2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 struct ao_i2c_stm_info {
23 struct stm_i2c *stm_i2c;
26 #define I2C_TIMEOUT 100
32 static uint8_t ao_i2c_state[STM_NUM_I2C];
33 static uint16_t ao_i2c_addr[STM_NUM_I2C];
34 uint8_t ao_i2c_mutex[STM_NUM_I2C];
36 #define AO_STM_I2C_CR1 ((0 << STM_I2C_CR1_SWRST) | \
37 (0 << STM_I2C_CR1_ALERT) | \
38 (0 << STM_I2C_CR1_PEC) | \
39 (0 << STM_I2C_CR1_POS) | \
40 (0 << STM_I2C_CR1_ACK) | \
41 (0 << STM_I2C_CR1_STOP) | \
42 (0 << STM_I2C_CR1_START) | \
43 (0 << STM_I2C_CR1_NOSTRETCH) | \
44 (0 << STM_I2C_CR1_ENGC) | \
45 (0 << STM_I2C_CR1_ENPEC) | \
46 (0 << STM_I2C_CR1_ENARP) | \
47 (0 << STM_I2C_CR1_SMBTYPE) | \
48 (0 << STM_I2C_CR1_SMBUS) | \
49 (1 << STM_I2C_CR1_PE))
51 #define AO_STM_I2C_CR2 ((0 << STM_I2C_CR2_LAST) | \
52 (0 << STM_I2C_CR2_DMAEN) | \
53 (0 << STM_I2C_CR2_ITBUFEN) | \
54 (0 << STM_I2C_CR2_ITEVTEN) | \
55 (0 << STM_I2C_CR2_ITERREN) | \
56 (STM_I2C_CR2_FREQ_16_MHZ << STM_I2C_CR2_FREQ))
58 static const struct ao_i2c_stm_info ao_i2c_stm_info[STM_NUM_I2C] = {
60 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_TX),
61 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_RX),
65 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_TX),
66 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_RX),
71 static uint8_t *ao_i2c_recv_data[STM_NUM_I2C];
72 static uint16_t ao_i2c_recv_len[STM_NUM_I2C];
73 static uint16_t ev_count;
76 ao_i2c_ev_isr(uint8_t index)
78 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
83 if (sr1 & (1 << STM_I2C_SR1_SB))
84 stm_i2c->dr = ao_i2c_addr[index];
85 if (sr1 & (1 << STM_I2C_SR1_ADDR)) {
86 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
87 ao_i2c_state[index] = I2C_RUNNING;
88 ao_wakeup(&ao_i2c_state[index]);
90 if (sr1 & (1 << STM_I2C_SR1_BTF)) {
91 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
92 ao_wakeup(&ao_i2c_state[index]);
94 if (sr1 & (1 << STM_I2C_SR1_RXNE)) {
95 if (ao_i2c_recv_len[index]) {
96 *(ao_i2c_recv_data[index]++) = stm_i2c->dr;
97 if (!--ao_i2c_recv_len[index])
98 ao_wakeup(&ao_i2c_recv_len[index]);
103 void stm_i2c1_ev_isr(void) { ao_i2c_ev_isr(0); }
104 void stm_i2c2_ev_isr(void) { ao_i2c_ev_isr(1); }
107 ao_i2c_er_isr(uint8_t index)
109 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
113 if (sr1 & (1 << STM_I2C_SR1_AF)) {
114 ao_i2c_state[index] = I2C_ERROR;
115 stm_i2c->sr1 = sr1 & ~(1 << STM_I2C_SR1_AF);
116 ao_wakeup(&ao_i2c_state[index]);
120 void stm_i2c1_er_isr(void) { ao_i2c_er_isr(0); }
121 void stm_i2c2_er_isr(void) { ao_i2c_er_isr(1); }
124 ao_i2c_get(uint8_t index)
126 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
127 ao_mutex_get(&ao_i2c_mutex[index]);
134 ao_i2c_put(uint8_t index)
136 ao_mutex_put(&ao_i2c_mutex[index]);
141 #define DBG(x...) printf(x)
146 static inline uint32_t in_sr1(char *where, struct stm_i2c *stm_i2c) {
147 uint32_t sr1 = stm_i2c->sr1;
148 DBG("%s: sr1: %x\n", where, sr1); flush();
152 static inline uint32_t in_sr2(char *where, struct stm_i2c *stm_i2c) {
153 uint32_t sr2 = stm_i2c->sr2;
154 DBG("%s: sr2: %x\n", where, sr2); flush();
158 static inline void out_cr1(char *where, struct stm_i2c *stm_i2c, uint32_t cr1) {
159 DBG("%s: cr1: %x\n", where, cr1); flush();
163 static inline uint32_t in_cr1(char *where, struct stm_i2c *stm_i2c) {
164 uint32_t cr1 = stm_i2c->cr1;
165 DBG("%s: cr1: %x\n", where, cr1); flush();
169 static inline void out_cr2(char *where, struct stm_i2c *stm_i2c, uint32_t cr2) {
170 DBG("%s: cr2: %x\n", where, cr2); flush();
174 static inline uint32_t in_dr(char *where, struct stm_i2c *stm_i2c) {
175 uint32_t dr = stm_i2c->dr;
176 DBG("%s: dr: %x\n", where, dr); flush();
180 static inline void out_dr(char *where, struct stm_i2c *stm_i2c, uint32_t dr) {
181 DBG("%s: dr: %x\n", where, dr); flush();
186 ao_i2c_start(uint8_t index, uint16_t addr)
188 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
192 ao_i2c_state[index] = I2C_IDLE;
193 ao_i2c_addr[index] = addr;
194 out_cr2("start", stm_i2c, AO_STM_I2C_CR2);
195 out_cr1("start", stm_i2c,
196 AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_START));
197 out_cr2("start", stm_i2c,
198 AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN));
201 while (ao_i2c_state[index] == I2C_IDLE)
202 if (ao_sleep(&ao_i2c_state[index]))
206 return ao_i2c_state[index] == I2C_RUNNING;
210 ao_i2c_wait_stop(uint8_t index)
212 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
215 for (t = 0; t < I2C_TIMEOUT; t++) {
216 if (!(in_cr1("wait stop", stm_i2c) & (1 << STM_I2C_CR1_STOP)))
220 ao_i2c_state[index] = I2C_IDLE;
224 ao_i2c_send(void *block, uint16_t len, uint8_t index, uint8_t stop)
226 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
231 uint8_t tx_dma_index = ao_i2c_stm_info[index].tx_dma_index;
233 /* Clear any pending ADDR bit */
234 in_sr2("send clear addr", stm_i2c);
235 out_cr2("send", stm_i2c, AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_DMAEN));
236 ao_dma_set_transfer(tx_dma_index,
240 (0 << STM_DMA_CCR_MEM2MEM) |
241 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
242 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
243 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
244 (1 << STM_DMA_CCR_MINC) |
245 (0 << STM_DMA_CCR_PINC) |
246 (0 << STM_DMA_CCR_CIRC) |
247 (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
249 ao_dma_start(tx_dma_index);
252 while (!ao_dma_done[tx_dma_index])
253 if (ao_sleep(&ao_dma_done[tx_dma_index])) {
254 printf ("send timeout\n");
257 ao_dma_done_transfer(tx_dma_index);
258 out_cr2("send enable isr", stm_i2c,
259 AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN));
260 while ((in_sr1("send_btf", stm_i2c) & (1 << STM_I2C_SR1_BTF)) == 0)
261 if (ao_sleep(&ao_i2c_state[index]))
263 out_cr2("send disable isr", stm_i2c, AO_STM_I2C_CR2);
266 out_cr1("stop", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
267 ao_i2c_wait_stop(index);
273 ao_i2c_recv_dma_isr(int index)
276 struct stm_i2c *stm_i2c = NULL;
278 for (i = 0; i < STM_NUM_I2C; i++)
279 if (index == ao_i2c_stm_info[i].rx_dma_index) {
280 stm_i2c = ao_i2c_stm_info[i].stm_i2c;
285 stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_LAST);
286 ao_dma_done[index] = 1;
287 ao_wakeup(&ao_dma_done[index]);
291 ao_i2c_recv(void *block, uint16_t len, uint8_t index, uint8_t stop)
293 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
301 ao_i2c_recv_data[index] = block;
302 ao_i2c_recv_len[index] = 1;
303 out_cr1("setup recv 1", stm_i2c, AO_STM_I2C_CR1);
305 /* Clear any pending ADDR bit */
306 in_sr2("clear addr", stm_i2c);
308 /* Enable interrupts to transfer the byte */
309 out_cr2("setup recv 1", stm_i2c,
311 (1 << STM_I2C_CR2_ITEVTEN) |
312 (1 << STM_I2C_CR2_ITERREN) |
313 (1 << STM_I2C_CR2_ITBUFEN));
315 out_cr1("setup recv 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
319 while (ao_i2c_recv_len[index])
320 if (ao_sleep(&ao_i2c_recv_len[index]))
323 ret = ao_i2c_recv_len[index] == 0;
326 uint8_t rx_dma_index = ao_i2c_stm_info[index].rx_dma_index;
327 ao_dma_set_transfer(rx_dma_index,
331 (0 << STM_DMA_CCR_MEM2MEM) |
332 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
333 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
334 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
335 (1 << STM_DMA_CCR_MINC) |
336 (0 << STM_DMA_CCR_PINC) |
337 (0 << STM_DMA_CCR_CIRC) |
338 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
339 out_cr1("recv > 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_ACK));
340 out_cr2("recv > 1", stm_i2c, AO_STM_I2C_CR2 |
341 (1 << STM_I2C_CR2_DMAEN) | (1 << STM_I2C_CR2_LAST));
342 /* Clear any pending ADDR bit */
343 in_sr2("clear addr", stm_i2c);
345 ao_dma_start(rx_dma_index);
348 while (!ao_dma_done[rx_dma_index])
349 if (ao_sleep(&ao_dma_done[rx_dma_index]))
353 ret = ao_dma_done[rx_dma_index];
354 ao_dma_done_transfer(rx_dma_index);
355 out_cr1("stop recv > 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
358 ao_i2c_wait_stop(index);
363 ao_i2c_channel_init(uint8_t index)
365 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
367 /* Turn I2C off while configuring */
369 stm_i2c->cr2 = AO_STM_I2C_CR2;
378 stm_i2c->ccr = ((1 << STM_I2C_CCR_FS) |
379 (0 << STM_I2C_CCR_DUTY) |
380 (20 << STM_I2C_CCR_CCR));
383 stm_i2c->cr1 = AO_STM_I2C_CR1;
389 /* All of the I2C configurations are on port B */
390 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
393 stm_afr_set(&stm_gpiob, 6, STM_AFR_AF4);
394 stm_afr_set(&stm_gpiob, 7, STM_AFR_AF4);
397 stm_afr_set(&stm_gpiob, 8, STM_AFR_AF4);
398 stm_afr_set(&stm_gpiob, 9, STM_AFR_AF4);
400 # error "No I2C_1 port configuration specified"
404 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C1EN);
405 ao_i2c_channel_init(0);
407 stm_nvic_set_enable(STM_ISR_I2C1_EV_POS);
408 stm_nvic_set_priority(STM_ISR_I2C1_EV_POS, 3);
409 stm_nvic_set_enable(STM_ISR_I2C1_ER_POS);
410 stm_nvic_set_priority(STM_ISR_I2C1_ER_POS, 3);
415 stm_afr_set(&stm_gpiob, 10, STM_AFR_AF4);
416 stm_afr_set(&stm_gpiob, 11, STM_AFR_AF4);
418 # error "No I2C_2 port configuration specified"
420 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C2EN);
421 ao_i2c_channel_init(1);
423 stm_nvic_set_enable(STM_ISR_I2C2_EV_POS);
424 stm_nvic_set_priority(STM_ISR_I2C2_EV_POS, 3);
425 stm_nvic_set_enable(STM_ISR_I2C2_ER_POS);
426 stm_nvic_set_priority(STM_ISR_I2C2_ER_POS, 3);