2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 struct ao_i2c_stm_info {
23 struct stm_i2c *stm_i2c;
26 #define I2C_TIMEOUT 100
32 static uint8_t ao_i2c_state[STM_NUM_I2C];
33 static uint16_t ao_i2c_addr[STM_NUM_I2C];
34 uint8_t ao_i2c_mutex[STM_NUM_I2C];
35 static void (*ao_i2c_callback[STM_NUM_I2C])(uint8_t index);
37 #define AO_STM_I2C_CR1 ((0 << STM_I2C_CR1_SWRST) | \
38 (0 << STM_I2C_CR1_ALERT) | \
39 (0 << STM_I2C_CR1_PEC) | \
40 (0 << STM_I2C_CR1_POS) | \
41 (0 << STM_I2C_CR1_ACK) | \
42 (0 << STM_I2C_CR1_STOP) | \
43 (0 << STM_I2C_CR1_START) | \
44 (0 << STM_I2C_CR1_NOSTRETCH) | \
45 (0 << STM_I2C_CR1_ENGC) | \
46 (0 << STM_I2C_CR1_ENPEC) | \
47 (0 << STM_I2C_CR1_ENARP) | \
48 (0 << STM_I2C_CR1_SMBTYPE) | \
49 (0 << STM_I2C_CR1_SMBUS) | \
50 (1 << STM_I2C_CR1_PE))
52 #define AO_STM_I2C_CR2 ((0 << STM_I2C_CR2_LAST) | \
53 (0 << STM_I2C_CR2_DMAEN) | \
54 (0 << STM_I2C_CR2_ITBUFEN) | \
55 (0 << STM_I2C_CR2_ITEVTEN) | \
56 (0 << STM_I2C_CR2_ITERREN) | \
57 (STM_I2C_CR2_FREQ_16_MHZ << STM_I2C_CR2_FREQ))
59 static const struct ao_i2c_stm_info ao_i2c_stm_info[STM_NUM_I2C] = {
61 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_TX),
62 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_RX),
66 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_TX),
67 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_RX),
72 static uint8_t *ao_i2c_recv_data[STM_NUM_I2C];
73 static uint16_t ao_i2c_recv_len[STM_NUM_I2C];
74 static uint16_t ev_count;
77 ao_i2c_ev_isr(uint8_t index)
79 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
84 if (sr1 & (1 << STM_I2C_SR1_SB))
85 stm_i2c->dr = ao_i2c_addr[index];
86 if (sr1 & (1 << STM_I2C_SR1_ADDR)) {
87 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
88 ao_i2c_state[index] = I2C_RUNNING;
89 ao_wakeup(&ao_i2c_state[index]);
91 if (sr1 & (1 << STM_I2C_SR1_BTF)) {
92 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
93 ao_wakeup(&ao_i2c_state[index]);
95 if (sr1 & (1 << STM_I2C_SR1_RXNE)) {
96 if (ao_i2c_recv_len[index]) {
97 *(ao_i2c_recv_data[index]++) = stm_i2c->dr;
98 if (!--ao_i2c_recv_len[index])
99 ao_wakeup(&ao_i2c_recv_len[index]);
104 void stm_i2c1_ev_isr(void) { ao_i2c_ev_isr(0); }
105 void stm_i2c2_ev_isr(void) { ao_i2c_ev_isr(1); }
108 ao_i2c_er_isr(uint8_t index)
110 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
114 if (sr1 & (1 << STM_I2C_SR1_AF)) {
115 ao_i2c_state[index] = I2C_ERROR;
116 stm_i2c->sr1 = sr1 & ~(1 << STM_I2C_SR1_AF);
117 ao_wakeup(&ao_i2c_state[index]);
121 void stm_i2c1_er_isr(void) { ao_i2c_er_isr(0); }
122 void stm_i2c2_er_isr(void) { ao_i2c_er_isr(1); }
125 ao_i2c_get(uint8_t index)
127 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
128 ao_mutex_get(&ao_i2c_mutex[index]);
135 ao_i2c_put(uint8_t index)
137 ao_mutex_put(&ao_i2c_mutex[index]);
142 #define DBG(x...) printf(x)
147 static inline uint32_t in_sr1(char *where, struct stm_i2c *stm_i2c) {
148 uint32_t sr1 = stm_i2c->sr1;
149 DBG("%s: sr1: %x\n", where, sr1); flush();
153 static inline uint32_t in_sr2(char *where, struct stm_i2c *stm_i2c) {
154 uint32_t sr2 = stm_i2c->sr2;
155 DBG("%s: sr2: %x\n", where, sr2); flush();
159 static inline void out_cr1(char *where, struct stm_i2c *stm_i2c, uint32_t cr1) {
160 DBG("%s: cr1: %x\n", where, cr1); flush();
164 static inline uint32_t in_cr1(char *where, struct stm_i2c *stm_i2c) {
165 uint32_t cr1 = stm_i2c->cr1;
166 DBG("%s: cr1: %x\n", where, cr1); flush();
170 static inline void out_cr2(char *where, struct stm_i2c *stm_i2c, uint32_t cr2) {
171 DBG("%s: cr2: %x\n", where, cr2); flush();
175 static inline uint32_t in_dr(char *where, struct stm_i2c *stm_i2c) {
176 uint32_t dr = stm_i2c->dr;
177 DBG("%s: dr: %x\n", where, dr); flush();
181 static inline void out_dr(char *where, struct stm_i2c *stm_i2c, uint32_t dr) {
182 DBG("%s: dr: %x\n", where, dr); flush();
187 ao_i2c_queue_start(uint8_t index, uint16_t addr)
189 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
193 ao_i2c_state[index] = I2C_IDLE;
194 ao_i2c_addr[index] = addr;
195 out_cr2("start", stm_i2c, AO_STM_I2C_CR2);
196 out_cr1("start", stm_i2c,
197 AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_START));
198 out_cr2("start", stm_i2c,
199 AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN));
203 ao_i2c_set_start_callback(uint8_t index, void (*callback)(uint8_t index))
209 ao_i2c_is_idle(uint8_t index)
211 return ao_i2c_state[index] == I2C_IDLE;
215 ao_i2c_start(uint8_t index, uint16_t addr)
217 ao_i2c_queue_start(index, addr);
221 while (ao_i2c_is_idle(index))
222 if (ao_sleep(&ao_i2c_state[index]))
226 return ao_i2c_state[index] == I2C_RUNNING;
230 ao_i2c_wait_stop(uint8_t index)
232 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
235 for (t = 0; t < I2C_TIMEOUT; t++) {
236 if (!(in_cr1("wait stop", stm_i2c) & (1 << STM_I2C_CR1_STOP)))
240 ao_i2c_state[index] = I2C_IDLE;
244 ao_i2c_send(void *block, uint16_t len, uint8_t index, uint8_t stop)
246 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
251 uint8_t tx_dma_index = ao_i2c_stm_info[index].tx_dma_index;
253 /* Clear any pending ADDR bit */
254 in_sr2("send clear addr", stm_i2c);
255 out_cr2("send", stm_i2c, AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_DMAEN));
256 ao_dma_set_transfer(tx_dma_index,
260 (0 << STM_DMA_CCR_MEM2MEM) |
261 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
262 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
263 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
264 (1 << STM_DMA_CCR_MINC) |
265 (0 << STM_DMA_CCR_PINC) |
266 (0 << STM_DMA_CCR_CIRC) |
267 (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
269 ao_dma_start(tx_dma_index);
272 while (!ao_dma_done[tx_dma_index])
273 if (ao_sleep(&ao_dma_done[tx_dma_index])) {
274 printf ("send timeout\n");
277 ao_dma_done_transfer(tx_dma_index);
278 out_cr2("send enable isr", stm_i2c,
279 AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN));
280 while ((in_sr1("send_btf", stm_i2c) & (1 << STM_I2C_SR1_BTF)) == 0)
281 if (ao_sleep(&ao_i2c_state[index]))
283 out_cr2("send disable isr", stm_i2c, AO_STM_I2C_CR2);
286 out_cr1("stop", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
287 ao_i2c_wait_stop(index);
293 ao_i2c_recv_dma_isr(int index)
296 struct stm_i2c *stm_i2c = NULL;
298 for (i = 0; i < STM_NUM_I2C; i++)
299 if (index == ao_i2c_stm_info[i].rx_dma_index) {
300 stm_i2c = ao_i2c_stm_info[i].stm_i2c;
305 stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_LAST);
306 ao_dma_done[index] = 1;
307 ao_wakeup(&ao_dma_done[index]);
311 ao_i2c_recv(void *block, uint16_t len, uint8_t index, uint8_t stop)
313 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
321 ao_i2c_recv_data[index] = block;
322 ao_i2c_recv_len[index] = 1;
323 out_cr1("setup recv 1", stm_i2c, AO_STM_I2C_CR1);
325 /* Clear any pending ADDR bit */
326 in_sr2("clear addr", stm_i2c);
328 /* Enable interrupts to transfer the byte */
329 out_cr2("setup recv 1", stm_i2c,
331 (1 << STM_I2C_CR2_ITEVTEN) |
332 (1 << STM_I2C_CR2_ITERREN) |
333 (1 << STM_I2C_CR2_ITBUFEN));
335 out_cr1("setup recv 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
339 while (ao_i2c_recv_len[index])
340 if (ao_sleep(&ao_i2c_recv_len[index]))
343 ret = ao_i2c_recv_len[index] == 0;
346 uint8_t rx_dma_index = ao_i2c_stm_info[index].rx_dma_index;
347 ao_dma_set_transfer(rx_dma_index,
351 (0 << STM_DMA_CCR_MEM2MEM) |
352 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
353 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
354 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
355 (1 << STM_DMA_CCR_MINC) |
356 (0 << STM_DMA_CCR_PINC) |
357 (0 << STM_DMA_CCR_CIRC) |
358 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
359 out_cr1("recv > 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_ACK));
360 out_cr2("recv > 1", stm_i2c, AO_STM_I2C_CR2 |
361 (1 << STM_I2C_CR2_DMAEN) | (1 << STM_I2C_CR2_LAST));
362 /* Clear any pending ADDR bit */
363 in_sr2("clear addr", stm_i2c);
365 ao_dma_start(rx_dma_index);
368 while (!ao_dma_done[rx_dma_index])
369 if (ao_sleep(&ao_dma_done[rx_dma_index]))
373 ret = ao_dma_done[rx_dma_index];
374 ao_dma_done_transfer(rx_dma_index);
375 out_cr1("stop recv > 1", stm_i2c, AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP));
378 ao_i2c_wait_stop(index);
383 ao_i2c_channel_init(uint8_t index)
385 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
387 /* Turn I2C off while configuring */
389 stm_i2c->cr2 = AO_STM_I2C_CR2;
398 stm_i2c->ccr = ((1 << STM_I2C_CCR_FS) |
399 (0 << STM_I2C_CCR_DUTY) |
400 (20 << STM_I2C_CCR_CCR));
403 stm_i2c->cr1 = AO_STM_I2C_CR1;
409 /* All of the I2C configurations are on port B */
410 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
413 stm_afr_set(&stm_gpiob, 6, STM_AFR_AF4);
414 stm_afr_set(&stm_gpiob, 7, STM_AFR_AF4);
417 stm_afr_set(&stm_gpiob, 8, STM_AFR_AF4);
418 stm_afr_set(&stm_gpiob, 9, STM_AFR_AF4);
420 # error "No I2C_1 port configuration specified"
424 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C1EN);
425 ao_i2c_channel_init(0);
427 stm_nvic_set_enable(STM_ISR_I2C1_EV_POS);
428 stm_nvic_set_priority(STM_ISR_I2C1_EV_POS, 3);
429 stm_nvic_set_enable(STM_ISR_I2C1_ER_POS);
430 stm_nvic_set_priority(STM_ISR_I2C1_ER_POS, 3);
435 stm_afr_set(&stm_gpiob, 10, STM_AFR_AF4);
436 stm_afr_set(&stm_gpiob, 11, STM_AFR_AF4);
438 # error "No I2C_2 port configuration specified"
440 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C2EN);
441 ao_i2c_channel_init(1);
443 stm_nvic_set_enable(STM_ISR_I2C2_EV_POS);
444 stm_nvic_set_priority(STM_ISR_I2C2_EV_POS, 3);
445 stm_nvic_set_enable(STM_ISR_I2C2_ER_POS);
446 stm_nvic_set_priority(STM_ISR_I2C2_ER_POS, 3);