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   1 /*
   2  * Copyright © 2012 Keith Packard <keithp@keithp.com>
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful, but
  10  * WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12  * General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  17  */
  18
  19 #include <ao.h>
  20
  21 struct ao_i2c_stm_info {
  22         uint8_t tx_dma_index;
  23         uint8_t rx_dma_index;
  24         struct stm_i2c  *stm_i2c;
  25 };
  26
  27 #define I2C_FAST        1
  28
  29 #define I2C_TIMEOUT     100
  30
  31 #define I2C_IDLE        0
  32 #define I2C_RUNNING     1
  33 #define I2C_ERROR       2
  34
  35 static uint8_t  ao_i2c_state[STM_NUM_I2C];
  36 static uint16_t ao_i2c_addr[STM_NUM_I2C];
  37 uint8_t         ao_i2c_mutex[STM_NUM_I2C];
  38
  39 # define I2C_HIGH_SLOW  5000    /* ns, 100kHz clock */
  40 #ifdef TELEMEGA
  41 # define I2C_HIGH_FAST  2000    /* ns, 167kHz clock */
  42 #else
  43 # define I2C_HIGH_FAST  1000    /* ns, 333kHz clock */
  44 #endif
  45
  46 # define I2C_RISE_SLOW  500     /* ns */
  47 # define I2C_RISE_FAST  100     /* ns */
  48
  49 /* Clock period in ns */
  50 #define CYCLES(period)  (((period) * (AO_PCLK1 / 1000)) / 1000000)
  51
  52 #define max(a,b)        ((a) > (b) ? (a) : (b))
  53 #define I2C_CCR_HIGH_SLOW       max(4,CYCLES(I2C_HIGH_SLOW))
  54 #define I2C_CCR_HIGH_FAST       max(4,CYCLES(I2C_HIGH_FAST))
  55 #define I2C_TRISE_SLOW          (CYCLES(I2C_RISE_SLOW) + 1)
  56 #define I2C_TRISE_FAST          (CYCLES(I2C_RISE_FAST) + 1)
  57
  58 #if I2C_FAST
  59 #define I2C_TRISE       I2C_TRISE_FAST
  60 #define I2C_CCR_HIGH    I2C_CCR_HIGH_FAST
  61 #else
  62 #define I2C_TRISE       I2C_TRISE_SLOW
  63 #define I2C_CCR_HIGH    I2C_CCR_HIGH_SLOW
  64 #endif
  65
  66 #if AO_PCLK1 == 2000000
  67 # define AO_STM_I2C_CR2_FREQ    STM_I2C_CR2_FREQ_2_MHZ
  68 #endif
  69 #if AO_PCLK1 == 4000000
  70 #  define AO_STM_I2C_CR2_FREQ   STM_I2C_CR2_FREQ_4_MHZ
  71 #endif
  72 #if AO_PCLK1 == 8000000
  73 # define AO_STM_I2C_CR2_FREQ    STM_I2C_CR2_FREQ_8_MHZ
  74 #endif
  75 #if AO_PCLK1 == 16000000
  76 # define AO_STM_I2C_CR2_FREQ    STM_I2C_CR2_FREQ_16_MHZ
  77 #endif
  78 #if AO_PCLK1 == 24000000
  79 # define AO_STM_I2C_CR2_FREQ    STM_I2C_CR2_FREQ_24_MHZ
  80 #endif
  81 #if AO_PCLK1 == 32000000
  82 # define AO_STM_I2C_CR2_FREQ    STM_I2C_CR2_FREQ_32_MHZ
  83 #endif
  84
  85 #define AO_STM_I2C_CR1 ((0 << STM_I2C_CR1_SWRST) |      \
  86                         (0 << STM_I2C_CR1_ALERT) |      \
  87                         (0 << STM_I2C_CR1_PEC) |        \
  88                         (0 << STM_I2C_CR1_POS) |        \
  89                         (0 << STM_I2C_CR1_ACK) |        \
  90                         (0 << STM_I2C_CR1_STOP) |       \
  91                         (0 << STM_I2C_CR1_START) |      \
  92                         (0 << STM_I2C_CR1_NOSTRETCH) |  \
  93                         (0 << STM_I2C_CR1_ENGC) |       \
  94                         (0 << STM_I2C_CR1_ENPEC) |      \
  95                         (0 << STM_I2C_CR1_ENARP) |      \
  96                         (0 << STM_I2C_CR1_SMBTYPE) |    \
  97                         (0 << STM_I2C_CR1_SMBUS) |      \
  98                         (1 << STM_I2C_CR1_PE))
  99
 100 #define AO_STM_I2C_CR2  ((0 << STM_I2C_CR2_LAST) |                      \
 101                          (0 << STM_I2C_CR2_DMAEN) |                     \
 102                          (0 << STM_I2C_CR2_ITBUFEN) |                   \
 103                          (0 << STM_I2C_CR2_ITEVTEN) |                   \
 104                          (0 << STM_I2C_CR2_ITERREN) |                   \
 105                          (AO_STM_I2C_CR2_FREQ << STM_I2C_CR2_FREQ))
 106
 107 static const struct ao_i2c_stm_info     ao_i2c_stm_info[STM_NUM_I2C] = {
 108         {
 109                 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_TX),
 110                 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_RX),
 111                 .stm_i2c = &stm_i2c1
 112         },
 113         {
 114                 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_TX),
 115                 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_RX),
 116                 .stm_i2c = &stm_i2c2
 117         },
 118 };
 119
 120 static uint8_t  *ao_i2c_recv_data[STM_NUM_I2C];
 121 static uint16_t ao_i2c_recv_len[STM_NUM_I2C];
 122 static uint16_t ev_count;
 123
 124 static void
 125 ao_i2c_ev_isr(uint8_t index)
 126 {
 127         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 128         uint32_t        sr1;
 129
 130         ++ev_count;
 131         sr1 = stm_i2c->sr1;
 132         if (sr1 & (1 << STM_I2C_SR1_SB))
 133                 stm_i2c->dr = ao_i2c_addr[index];
 134         if (sr1 & (1 << STM_I2C_SR1_ADDR)) {
 135                 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
 136                 ao_i2c_state[index] = I2C_RUNNING;
 137                 ao_wakeup(&ao_i2c_state[index]);
 138         }
 139         if (sr1 & (1 << STM_I2C_SR1_BTF)) {
 140                 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
 141                 ao_wakeup(&ao_i2c_state[index]);
 142         }
 143         if (sr1 & (1 << STM_I2C_SR1_RXNE)) {
 144                 if (ao_i2c_recv_len[index]) {
 145                         *(ao_i2c_recv_data[index]++) = stm_i2c->dr;
 146                         if (!--ao_i2c_recv_len[index])
 147                                 ao_wakeup(&ao_i2c_recv_len[index]);
 148                 }
 149         }
 150 }
 151
 152 void stm_i2c1_ev_isr(void) { ao_i2c_ev_isr(0); }
 153 void stm_i2c2_ev_isr(void) { ao_i2c_ev_isr(1); }
 154
 155 static void
 156 ao_i2c_er_isr(uint8_t index)
 157 {
 158         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 159         uint32_t        sr1;
 160
 161         sr1 = stm_i2c->sr1;
 162         if (sr1 & (1 << STM_I2C_SR1_AF)) {
 163                 ao_i2c_state[index] = I2C_ERROR;
 164                 stm_i2c->sr1 = sr1 & ~(1 << STM_I2C_SR1_AF);
 165                 ao_wakeup(&ao_i2c_state[index]);
 166         }
 167 }
 168
 169 void stm_i2c1_er_isr(void) { ao_i2c_er_isr(0); }
 170 void stm_i2c2_er_isr(void) { ao_i2c_er_isr(1); }
 171
 172 void
 173 ao_i2c_get(uint8_t index)
 174 {
 175         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 176         ao_mutex_get(&ao_i2c_mutex[index]);
 177
 178         stm_i2c->sr1 = 0;
 179         stm_i2c->sr2 = 0;
 180 }
 181
 182 void
 183 ao_i2c_put(uint8_t index)
 184 {
 185         ao_mutex_put(&ao_i2c_mutex[index]);
 186 }
 187
 188 uint8_t
 189 ao_i2c_start(uint8_t index, uint16_t addr)
 190 {
 191         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 192         int             t;
 193
 194         ao_i2c_state[index] = I2C_IDLE;
 195         ao_i2c_addr[index] = addr;
 196         stm_i2c->cr2 = AO_STM_I2C_CR2;
 197         stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_START);
 198         for (t = 0; t < I2C_TIMEOUT; t++) {
 199                 if (!(stm_i2c->cr1 & (1 << STM_I2C_CR1_START)))
 200                         break;
 201         }
 202         ao_arch_block_interrupts();
 203         stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN);
 204         ao_i2c_ev_isr(index);
 205         while (ao_i2c_state[index] == I2C_IDLE)
 206                 if (ao_sleep_for(&ao_i2c_state[index], AO_MS_TO_TICKS(250)))
 207                         break;
 208         ao_arch_release_interrupts();
 209         return ao_i2c_state[index] == I2C_RUNNING;
 210 }
 211
 212 static void
 213 ao_i2c_wait_stop(uint8_t index)
 214 {
 215         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 216         int     t;
 217
 218         for (t = 0; t < I2C_TIMEOUT; t++) {
 219                 if (!(stm_i2c->cr1 & (1 << STM_I2C_CR1_STOP)))
 220                         break;
 221                 ao_yield();
 222         }
 223         ao_i2c_state[index] = I2C_IDLE;
 224 }
 225
 226 static void
 227 ao_i2c_wait_addr(uint8_t index)
 228 {
 229         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 230         int     t;
 231
 232         for (t = 0; t < I2C_TIMEOUT; t++)
 233                 if (!(stm_i2c->sr1 & (1 << STM_I2C_SR1_ADDR)))
 234                         break;
 235         if (t)
 236                 printf ("wait_addr %d\n", t);
 237 }
 238
 239 uint8_t
 240 ao_i2c_send(void *block, uint16_t len, uint8_t index, uint8_t stop)
 241 {
 242         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 243         uint8_t         tx_dma_index = ao_i2c_stm_info[index].tx_dma_index;
 244
 245         /* Clear any pending ADDR bit */
 246         (void) stm_i2c->sr2;
 247         ao_i2c_wait_addr(index);
 248         stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_DMAEN);
 249         ao_dma_set_transfer(tx_dma_index,
 250                             &stm_i2c->dr,
 251                             block,
 252                             len,
 253                             (0 << STM_DMA_CCR_MEM2MEM) |
 254                             (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
 255                             (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 256                             (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 257                             (1 << STM_DMA_CCR_MINC) |
 258                             (0 << STM_DMA_CCR_PINC) |
 259                             (0 << STM_DMA_CCR_CIRC) |
 260                             (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
 261
 262         ao_dma_start(tx_dma_index);
 263         ao_arch_block_interrupts();
 264         while (!ao_dma_done[tx_dma_index])
 265                 if (ao_sleep_for(&ao_dma_done[tx_dma_index], 1 + len))
 266                         break;
 267         ao_dma_done_transfer(tx_dma_index);
 268         stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN);
 269         while ((stm_i2c->sr1 & (1 << STM_I2C_SR1_BTF)) == 0)
 270                 if (ao_sleep_for(&ao_i2c_state[index], 1 + len))
 271                         break;
 272         stm_i2c->cr2 = AO_STM_I2C_CR2;
 273         ao_arch_release_interrupts();
 274         if (stop) {
 275                 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
 276                 ao_i2c_wait_stop(index);
 277         }
 278         return TRUE;
 279 }
 280
 281 void
 282 ao_i2c_recv_dma_isr(int index)
 283 {
 284         int             i;
 285         struct stm_i2c  *stm_i2c = NULL;
 286
 287         for (i = 0; i < STM_NUM_I2C; i++)
 288                 if (index == ao_i2c_stm_info[i].rx_dma_index) {
 289                         stm_i2c = ao_i2c_stm_info[i].stm_i2c;
 290                         break;
 291                 }
 292         if (!stm_i2c)
 293                 return;
 294         stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_LAST);
 295         ao_dma_done[index] = 1;
 296         ao_wakeup(&ao_dma_done[index]);
 297 }
 298
 299 uint8_t
 300 ao_i2c_recv(void *block, uint16_t len, uint8_t index, uint8_t stop)
 301 {
 302         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 303         uint8_t         ret = TRUE;
 304
 305         if (len == 0)
 306                 return TRUE;
 307         if (len == 1) {
 308                 ao_i2c_recv_data[index] = block;
 309                 ao_i2c_recv_len[index] = 1;
 310                 stm_i2c->cr1 = AO_STM_I2C_CR1;
 311
 312                 /* Clear any pending ADDR bit */
 313                 stm_i2c->sr2;
 314                 ao_i2c_wait_addr(index);
 315
 316                 /* Enable interrupts to transfer the byte */
 317                 stm_i2c->cr2 = (AO_STM_I2C_CR2 |
 318                                 (1 << STM_I2C_CR2_ITEVTEN) |
 319                                 (1 << STM_I2C_CR2_ITERREN) |
 320                                 (1 << STM_I2C_CR2_ITBUFEN));
 321                 if (stop)
 322                         stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
 323
 324                 ao_arch_block_interrupts();
 325                 while (ao_i2c_recv_len[index])
 326                         if (ao_sleep_for(&ao_i2c_recv_len[index], 1))
 327                                 break;
 328                 ao_arch_release_interrupts();
 329                 ret = ao_i2c_recv_len[index] == 0;
 330         } else {
 331                 uint8_t         rx_dma_index = ao_i2c_stm_info[index].rx_dma_index;
 332                 ao_dma_set_transfer(rx_dma_index,
 333                                     &stm_i2c->dr,
 334                                     block,
 335                                     len,
 336                                     (0 << STM_DMA_CCR_MEM2MEM) |
 337                                     (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
 338                                     (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
 339                                     (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
 340                                     (1 << STM_DMA_CCR_MINC) |
 341                                     (0 << STM_DMA_CCR_PINC) |
 342                                     (0 << STM_DMA_CCR_CIRC) |
 343                                     (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
 344                 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_ACK);
 345                 stm_i2c->cr2 = AO_STM_I2C_CR2 |
 346                         (1 << STM_I2C_CR2_DMAEN) | (1 << STM_I2C_CR2_LAST);
 347                 /* Clear any pending ADDR bit */
 348                 (void) stm_i2c->sr2;
 349                 ao_i2c_wait_addr(index);
 350
 351                 ao_dma_start(rx_dma_index);
 352                 ao_arch_block_interrupts();
 353                 while (!ao_dma_done[rx_dma_index])
 354                         if (ao_sleep_for(&ao_dma_done[rx_dma_index], len))
 355                                 break;
 356                 ao_arch_release_interrupts();
 357                 ret = ao_dma_done[rx_dma_index];
 358                 ao_dma_done_transfer(rx_dma_index);
 359                 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
 360         }
 361         if (stop)
 362                 ao_i2c_wait_stop(index);
 363         return ret;
 364 }
 365
 366 void
 367 ao_i2c_channel_init(uint8_t index)
 368 {
 369         struct stm_i2c  *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
 370         int i;
 371
 372         /* Turn I2C off while configuring */
 373         stm_i2c->cr1 = (1 << STM_I2C_CR1_SWRST);
 374         for (i = 0; i < 100; i++)
 375                 asm("nop");
 376         stm_i2c->cr1 = 0;
 377         stm_i2c->cr2 = AO_STM_I2C_CR2;
 378
 379         (void) stm_i2c->sr1;
 380         (void) stm_i2c->sr2;
 381         (void) stm_i2c->dr;
 382
 383         stm_i2c->sr1 = 0;
 384         stm_i2c->sr2 = 0;
 385
 386         stm_i2c->ccr = ((I2C_FAST << STM_I2C_CCR_FS) |
 387                         (0 << STM_I2C_CCR_DUTY) |
 388                         (I2C_CCR_HIGH << STM_I2C_CCR_CCR));
 389
 390         stm_i2c->trise = I2C_TRISE;
 391
 392         stm_i2c->cr1 = AO_STM_I2C_CR1;
 393 }
 394
 395 static inline void
 396 i2c_pin_set(struct stm_gpio *gpio, int pin)
 397 {
 398         stm_afr_set(gpio, pin, STM_AFR_AF4);
 399         stm_ospeedr_set(gpio, pin, STM_OSPEEDR_400kHz);
 400         stm_pupdr_set(gpio, pin, STM_PUPDR_PULL_UP);
 401 }
 402
 403 void
 404 ao_i2c_init(void)
 405 {
 406         /* All of the I2C configurations are on port B */
 407         stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
 408 #if HAS_I2C_1
 409 # if I2C_1_PB6_PB7
 410         i2c_pin_set(&stm_gpiob, 6);
 411         i2c_pin_set(&stm_gpiob, 7);
 412 # else
 413 #  if I2C_1_PB8_PB9
 414         i2c_pin_set(&stm_gpiob, 8);
 415         i2c_pin_set(&stm_gpiob, 9);
 416 #  else
 417 #   error "No I2C_1 port configuration specified"
 418 #  endif
 419 # endif
 420
 421         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C1EN);
 422         ao_i2c_channel_init(0);
 423
 424         stm_nvic_set_enable(STM_ISR_I2C1_EV_POS);
 425         stm_nvic_set_priority(STM_ISR_I2C1_EV_POS, AO_STM_NVIC_MED_PRIORITY);
 426         stm_nvic_set_enable(STM_ISR_I2C1_ER_POS);
 427         stm_nvic_set_priority(STM_ISR_I2C1_ER_POS, AO_STM_NVIC_MED_PRIORITY);
 428 #endif
 429
 430 #if HAS_I2C_2
 431 # if I2C_2_PB10_PB11
 432         i2c_pin_set(&stm_gpiob, 10);
 433         i2c_pin_set(&stm_gpiob, 11);
 434 # else
 435 #  error "No I2C_2 port configuration specified"
 436 # endif
 437         stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C2EN);
 438         ao_i2c_channel_init(1);
 439
 440         stm_nvic_set_enable(STM_ISR_I2C2_EV_POS);
 441         stm_nvic_set_priority(STM_ISR_I2C2_EV_POS, AO_STM_NVIC_MED_PRIORITY);
 442         stm_nvic_set_enable(STM_ISR_I2C2_ER_POS);
 443         stm_nvic_set_priority(STM_ISR_I2C2_ER_POS, AO_STM_NVIC_MED_PRIORITY);
 444 #endif
 445 }