2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 struct ao_i2c_stm_info {
23 struct stm_i2c *stm_i2c;
28 #define I2C_TIMEOUT 100
34 static uint8_t ao_i2c_state[STM_NUM_I2C];
35 static uint16_t ao_i2c_addr[STM_NUM_I2C];
36 uint8_t ao_i2c_mutex[STM_NUM_I2C];
38 # define I2C_HIGH_SLOW 5000 /* ns, 100kHz clock */
40 # define I2C_HIGH_FAST 2000 /* ns, 167kHz clock */
42 # define I2C_HIGH_FAST 1000 /* ns, 333kHz clock */
45 # define I2C_RISE_SLOW 500 /* ns */
46 # define I2C_RISE_FAST 100 /* ns */
48 /* Clock period in ns */
49 #define CYCLES(period) (((period) * (AO_PCLK1 / 1000)) / 1000000)
51 #define max(a,b) ((a) > (b) ? (a) : (b))
52 #define I2C_CCR_HIGH_SLOW max(4,CYCLES(I2C_HIGH_SLOW))
53 #define I2C_CCR_HIGH_FAST max(4,CYCLES(I2C_HIGH_FAST))
54 #define I2C_TRISE_SLOW (CYCLES(I2C_RISE_SLOW) + 1)
55 #define I2C_TRISE_FAST (CYCLES(I2C_RISE_FAST) + 1)
58 #define I2C_TRISE I2C_TRISE_FAST
59 #define I2C_CCR_HIGH I2C_CCR_HIGH_FAST
61 #define I2C_TRISE I2C_TRISE_SLOW
62 #define I2C_CCR_HIGH I2C_CCR_HIGH_SLOW
65 #if AO_PCLK1 == 2000000
66 # define AO_STM_I2C_CR2_FREQ STM_I2C_CR2_FREQ_2_MHZ
68 #if AO_PCLK1 == 4000000
69 # define AO_STM_I2C_CR2_FREQ STM_I2C_CR2_FREQ_4_MHZ
71 #if AO_PCLK1 == 8000000
72 # define AO_STM_I2C_CR2_FREQ STM_I2C_CR2_FREQ_8_MHZ
74 #if AO_PCLK1 == 16000000
75 # define AO_STM_I2C_CR2_FREQ STM_I2C_CR2_FREQ_16_MHZ
77 #if AO_PCLK1 == 32000000
78 # define AO_STM_I2C_CR2_FREQ STM_I2C_CR2_FREQ_32_MHZ
81 #define AO_STM_I2C_CR1 ((0 << STM_I2C_CR1_SWRST) | \
82 (0 << STM_I2C_CR1_ALERT) | \
83 (0 << STM_I2C_CR1_PEC) | \
84 (0 << STM_I2C_CR1_POS) | \
85 (0 << STM_I2C_CR1_ACK) | \
86 (0 << STM_I2C_CR1_STOP) | \
87 (0 << STM_I2C_CR1_START) | \
88 (0 << STM_I2C_CR1_NOSTRETCH) | \
89 (0 << STM_I2C_CR1_ENGC) | \
90 (0 << STM_I2C_CR1_ENPEC) | \
91 (0 << STM_I2C_CR1_ENARP) | \
92 (0 << STM_I2C_CR1_SMBTYPE) | \
93 (0 << STM_I2C_CR1_SMBUS) | \
94 (1 << STM_I2C_CR1_PE))
96 #define AO_STM_I2C_CR2 ((0 << STM_I2C_CR2_LAST) | \
97 (0 << STM_I2C_CR2_DMAEN) | \
98 (0 << STM_I2C_CR2_ITBUFEN) | \
99 (0 << STM_I2C_CR2_ITEVTEN) | \
100 (0 << STM_I2C_CR2_ITERREN) | \
101 (AO_STM_I2C_CR2_FREQ << STM_I2C_CR2_FREQ))
103 static const struct ao_i2c_stm_info ao_i2c_stm_info[STM_NUM_I2C] = {
105 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_TX),
106 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_RX),
110 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_TX),
111 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_RX),
116 static uint8_t *ao_i2c_recv_data[STM_NUM_I2C];
117 static uint16_t ao_i2c_recv_len[STM_NUM_I2C];
118 static uint16_t ev_count;
121 ao_i2c_ev_isr(uint8_t index)
123 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
128 if (sr1 & (1 << STM_I2C_SR1_SB))
129 stm_i2c->dr = ao_i2c_addr[index];
130 if (sr1 & (1 << STM_I2C_SR1_ADDR)) {
131 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
132 ao_i2c_state[index] = I2C_RUNNING;
133 ao_wakeup(&ao_i2c_state[index]);
135 if (sr1 & (1 << STM_I2C_SR1_BTF)) {
136 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_ITEVTEN);
137 ao_wakeup(&ao_i2c_state[index]);
139 if (sr1 & (1 << STM_I2C_SR1_RXNE)) {
140 if (ao_i2c_recv_len[index]) {
141 *(ao_i2c_recv_data[index]++) = stm_i2c->dr;
142 if (!--ao_i2c_recv_len[index])
143 ao_wakeup(&ao_i2c_recv_len[index]);
148 void stm_i2c1_ev_isr(void) { ao_i2c_ev_isr(0); }
149 void stm_i2c2_ev_isr(void) { ao_i2c_ev_isr(1); }
152 ao_i2c_er_isr(uint8_t index)
154 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
158 if (sr1 & (1 << STM_I2C_SR1_AF)) {
159 ao_i2c_state[index] = I2C_ERROR;
160 stm_i2c->sr1 = sr1 & ~(1 << STM_I2C_SR1_AF);
161 ao_wakeup(&ao_i2c_state[index]);
165 void stm_i2c1_er_isr(void) { ao_i2c_er_isr(0); }
166 void stm_i2c2_er_isr(void) { ao_i2c_er_isr(1); }
169 ao_i2c_get(uint8_t index)
171 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
172 ao_mutex_get(&ao_i2c_mutex[index]);
179 ao_i2c_put(uint8_t index)
181 ao_mutex_put(&ao_i2c_mutex[index]);
185 ao_i2c_start(uint8_t index, uint16_t addr)
187 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
190 ao_i2c_state[index] = I2C_IDLE;
191 ao_i2c_addr[index] = addr;
192 stm_i2c->cr2 = AO_STM_I2C_CR2;
193 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_START);
194 for (t = 0; t < I2C_TIMEOUT; t++) {
195 if (!(stm_i2c->cr1 & (1 << STM_I2C_CR1_START)))
198 ao_arch_block_interrupts();
199 stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN);
200 ao_i2c_ev_isr(index);
201 while (ao_i2c_state[index] == I2C_IDLE)
202 if (ao_sleep_for(&ao_i2c_state[index], AO_MS_TO_TICKS(250)))
204 ao_arch_release_interrupts();
205 return ao_i2c_state[index] == I2C_RUNNING;
209 ao_i2c_wait_stop(uint8_t index)
211 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
214 for (t = 0; t < I2C_TIMEOUT; t++) {
215 if (!(stm_i2c->cr1 & (1 << STM_I2C_CR1_STOP)))
219 ao_i2c_state[index] = I2C_IDLE;
223 ao_i2c_wait_addr(uint8_t index)
225 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
228 for (t = 0; t < I2C_TIMEOUT; t++)
229 if (!(stm_i2c->sr1 & (1 << STM_I2C_SR1_ADDR)))
232 printf ("wait_addr %d\n", t);
236 ao_i2c_send(void *block, uint16_t len, uint8_t index, uint8_t stop)
238 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
239 uint8_t tx_dma_index = ao_i2c_stm_info[index].tx_dma_index;
241 /* Clear any pending ADDR bit */
243 ao_i2c_wait_addr(index);
244 stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_DMAEN);
245 ao_dma_set_transfer(tx_dma_index,
249 (0 << STM_DMA_CCR_MEM2MEM) |
250 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
251 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
252 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
253 (1 << STM_DMA_CCR_MINC) |
254 (0 << STM_DMA_CCR_PINC) |
255 (0 << STM_DMA_CCR_CIRC) |
256 (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
258 ao_dma_start(tx_dma_index);
259 ao_arch_block_interrupts();
260 while (!ao_dma_done[tx_dma_index])
261 if (ao_sleep_for(&ao_dma_done[tx_dma_index], 1 + len))
263 ao_dma_done_transfer(tx_dma_index);
264 stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN);
265 while ((stm_i2c->sr1 & (1 << STM_I2C_SR1_BTF)) == 0)
266 if (ao_sleep_for(&ao_i2c_state[index], 1 + len))
268 stm_i2c->cr2 = AO_STM_I2C_CR2;
269 ao_arch_release_interrupts();
271 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
272 ao_i2c_wait_stop(index);
278 ao_i2c_recv_dma_isr(int index)
281 struct stm_i2c *stm_i2c = NULL;
283 for (i = 0; i < STM_NUM_I2C; i++)
284 if (index == ao_i2c_stm_info[i].rx_dma_index) {
285 stm_i2c = ao_i2c_stm_info[i].stm_i2c;
290 stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_LAST);
291 ao_dma_done[index] = 1;
292 ao_wakeup(&ao_dma_done[index]);
296 ao_i2c_recv(void *block, uint16_t len, uint8_t index, uint8_t stop)
298 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
304 ao_i2c_recv_data[index] = block;
305 ao_i2c_recv_len[index] = 1;
306 stm_i2c->cr1 = AO_STM_I2C_CR1;
308 /* Clear any pending ADDR bit */
310 ao_i2c_wait_addr(index);
312 /* Enable interrupts to transfer the byte */
313 stm_i2c->cr2 = (AO_STM_I2C_CR2 |
314 (1 << STM_I2C_CR2_ITEVTEN) |
315 (1 << STM_I2C_CR2_ITERREN) |
316 (1 << STM_I2C_CR2_ITBUFEN));
318 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
320 ao_arch_block_interrupts();
321 while (ao_i2c_recv_len[index])
322 if (ao_sleep_for(&ao_i2c_recv_len[index], 1))
324 ao_arch_release_interrupts();
325 ret = ao_i2c_recv_len[index] == 0;
327 uint8_t rx_dma_index = ao_i2c_stm_info[index].rx_dma_index;
328 ao_dma_set_transfer(rx_dma_index,
332 (0 << STM_DMA_CCR_MEM2MEM) |
333 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
334 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
335 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
336 (1 << STM_DMA_CCR_MINC) |
337 (0 << STM_DMA_CCR_PINC) |
338 (0 << STM_DMA_CCR_CIRC) |
339 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
340 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_ACK);
341 stm_i2c->cr2 = AO_STM_I2C_CR2 |
342 (1 << STM_I2C_CR2_DMAEN) | (1 << STM_I2C_CR2_LAST);
343 /* Clear any pending ADDR bit */
345 ao_i2c_wait_addr(index);
347 ao_dma_start(rx_dma_index);
348 ao_arch_block_interrupts();
349 while (!ao_dma_done[rx_dma_index])
350 if (ao_sleep_for(&ao_dma_done[rx_dma_index], len))
352 ao_arch_release_interrupts();
353 ret = ao_dma_done[rx_dma_index];
354 ao_dma_done_transfer(rx_dma_index);
355 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
358 ao_i2c_wait_stop(index);
363 ao_i2c_channel_init(uint8_t index)
365 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
368 /* Turn I2C off while configuring */
369 stm_i2c->cr1 = (1 << STM_I2C_CR1_SWRST);
370 for (i = 0; i < 100; i++)
373 stm_i2c->cr2 = AO_STM_I2C_CR2;
382 stm_i2c->ccr = ((I2C_FAST << STM_I2C_CCR_FS) |
383 (0 << STM_I2C_CCR_DUTY) |
384 (I2C_CCR_HIGH << STM_I2C_CCR_CCR));
386 stm_i2c->trise = I2C_TRISE;
388 stm_i2c->cr1 = AO_STM_I2C_CR1;
392 i2c_pin_set(struct stm_gpio *gpio, int pin)
394 stm_afr_set(gpio, pin, STM_AFR_AF4);
395 stm_ospeedr_set(gpio, pin, STM_OSPEEDR_400kHz);
396 stm_pupdr_set(gpio, pin, STM_PUPDR_PULL_UP);
402 /* All of the I2C configurations are on port B */
403 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
406 i2c_pin_set(&stm_gpiob, 6);
407 i2c_pin_set(&stm_gpiob, 7);
410 i2c_pin_set(&stm_gpiob, 8);
411 i2c_pin_set(&stm_gpiob, 9);
413 # error "No I2C_1 port configuration specified"
417 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C1EN);
418 ao_i2c_channel_init(0);
420 stm_nvic_set_enable(STM_ISR_I2C1_EV_POS);
421 stm_nvic_set_priority(STM_ISR_I2C1_EV_POS, AO_STM_NVIC_MED_PRIORITY);
422 stm_nvic_set_enable(STM_ISR_I2C1_ER_POS);
423 stm_nvic_set_priority(STM_ISR_I2C1_ER_POS, AO_STM_NVIC_MED_PRIORITY);
428 i2c_pin_set(&stm_gpiob, 10);
429 i2c_pin_set(&stm_gpiob, 11);
431 # error "No I2C_2 port configuration specified"
433 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C2EN);
434 ao_i2c_channel_init(1);
436 stm_nvic_set_enable(STM_ISR_I2C2_EV_POS);
437 stm_nvic_set_priority(STM_ISR_I2C2_EV_POS, AO_STM_NVIC_MED_PRIORITY);
438 stm_nvic_set_enable(STM_ISR_I2C2_ER_POS);
439 stm_nvic_set_priority(STM_ISR_I2C2_ER_POS, AO_STM_NVIC_MED_PRIORITY);