2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
20 struct ao_i2c_stm_info {
23 struct stm_i2c *stm_i2c;
30 static uint8_t ao_i2c_state[STM_NUM_I2C];
31 static uint16_t ao_i2c_addr[STM_NUM_I2C];
32 uint8_t ao_i2c_mutex[STM_NUM_I2C];
34 #define AO_STM_I2C_CR1 ((0 << STM_I2C_CR1_SWRST) | \
35 (0 << STM_I2C_CR1_ALERT) | \
36 (0 << STM_I2C_CR1_PEC) | \
37 (0 << STM_I2C_CR1_POS) | \
38 (0 << STM_I2C_CR1_ACK) | \
39 (0 << STM_I2C_CR1_STOP) | \
40 (0 << STM_I2C_CR1_START) | \
41 (0 << STM_I2C_CR1_NOSTRETCH) | \
42 (0 << STM_I2C_CR1_ENGC) | \
43 (0 << STM_I2C_CR1_ENPEC) | \
44 (0 << STM_I2C_CR1_ENARP) | \
45 (0 << STM_I2C_CR1_SMBTYPE) | \
46 (0 << STM_I2C_CR1_SMBUS) | \
47 (1 << STM_I2C_CR1_PE))
49 #define AO_STM_I2C_CR2 ((0 << STM_I2C_CR2_LAST) | \
50 (1 << STM_I2C_CR2_DMAEN) | \
51 (0 << STM_I2C_CR2_ITBUFEN) | \
52 (0 << STM_I2C_CR2_ITEVTEN) | \
53 (0 << STM_I2C_CR2_ITERREN) | \
54 (STM_I2C_CR2_FREQ_16_MHZ << STM_I2C_CR2_FREQ))
56 static const struct ao_i2c_stm_info ao_i2c_stm_info[STM_NUM_I2C] = {
58 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_TX),
59 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C1_RX),
63 .tx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_TX),
64 .rx_dma_index = STM_DMA_INDEX(STM_DMA_CHANNEL_I2C2_RX),
70 ao_i2c_ev_isr(uint8_t index)
72 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
76 if (sr1 & (1 << STM_I2C_SR1_SB))
77 stm_i2c->dr = ao_i2c_addr[index];
78 if (sr1 & (1 << STM_I2C_SR1_ADDR)) {
80 ao_i2c_state[index] = I2C_RUNNING;
81 ao_wakeup(&ao_i2c_state[index]);
85 void stm_i2c1_ev_isr(void) { ao_i2c_ev_isr(0); }
86 void stm_i2c2_ev_isr(void) { ao_i2c_ev_isr(1); }
89 ao_i2c_er_isr(uint8_t index)
91 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
95 if (sr1 & (1 << STM_I2C_SR1_AF)) {
96 ao_i2c_state[index] = I2C_ERROR;
97 stm_i2c->sr1 = sr1 & ~(1 << STM_I2C_SR1_AF);
98 ao_wakeup(&ao_i2c_state[index]);
102 void stm_i2c1_er_isr(void) { ao_i2c_er_isr(0); }
103 void stm_i2c2_er_isr(void) { ao_i2c_er_isr(1); }
106 ao_i2c_get(uint8_t index)
108 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
109 ao_mutex_get(&ao_i2c_mutex[index]);
116 ao_i2c_put(uint8_t index)
118 ao_mutex_put(&ao_i2c_mutex[index]);
122 ao_i2c_start(uint8_t index, uint16_t addr)
124 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
126 ao_i2c_state[index] = I2C_IDLE;
127 ao_i2c_addr[index] = addr;
128 stm_i2c->cr2 = AO_STM_I2C_CR2 | (1 << STM_I2C_CR2_ITEVTEN) | (1 << STM_I2C_CR2_ITERREN);
129 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_START);
131 while (ao_i2c_state[index] == I2C_IDLE)
132 ao_sleep(&ao_i2c_state[index]);
134 return ao_i2c_state[index] == I2C_RUNNING;
138 ao_i2c_stop(uint8_t index)
140 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
142 ao_i2c_state[index] = I2C_IDLE;
143 stm_i2c->cr1 = AO_STM_I2C_CR1 | (1 << STM_I2C_CR1_STOP);
147 ao_i2c_send(void *block, uint16_t len, uint8_t index)
149 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
150 uint8_t tx_dma_index = ao_i2c_stm_info[index].tx_dma_index;
152 stm_i2c->cr2 &= ~(1 << STM_I2C_CR2_LAST);
153 ao_dma_set_transfer(tx_dma_index,
157 (0 << STM_DMA_CCR_MEM2MEM) |
158 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
159 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
160 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
161 (1 << STM_DMA_CCR_MINC) |
162 (0 << STM_DMA_CCR_PINC) |
163 (0 << STM_DMA_CCR_CIRC) |
164 (STM_DMA_CCR_DIR_MEM_TO_PER << STM_DMA_CCR_DIR));
166 ao_dma_start(tx_dma_index);
168 while (!ao_dma_done[tx_dma_index])
169 ao_sleep(&ao_dma_done[tx_dma_index]);
171 ao_dma_done_transfer(tx_dma_index);
175 ao_i2c_recv(void *block, uint16_t len, uint8_t index)
177 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
178 uint8_t rx_dma_index = ao_i2c_stm_info[index].rx_dma_index;
180 stm_i2c->cr2 |= (1 << STM_I2C_CR2_LAST);
181 ao_dma_set_transfer(rx_dma_index,
185 (0 << STM_DMA_CCR_MEM2MEM) |
186 (STM_DMA_CCR_PL_MEDIUM << STM_DMA_CCR_PL) |
187 (STM_DMA_CCR_MSIZE_8 << STM_DMA_CCR_MSIZE) |
188 (STM_DMA_CCR_PSIZE_8 << STM_DMA_CCR_PSIZE) |
189 (1 << STM_DMA_CCR_MINC) |
190 (0 << STM_DMA_CCR_PINC) |
191 (0 << STM_DMA_CCR_CIRC) |
192 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
194 ao_dma_start(rx_dma_index);
196 while (!ao_dma_done[rx_dma_index])
197 ao_sleep(&ao_dma_done[rx_dma_index]);
199 ao_dma_done_transfer(rx_dma_index);
203 ao_i2c_channel_init(uint8_t index)
205 struct stm_i2c *stm_i2c = ao_i2c_stm_info[index].stm_i2c;
207 /* Turn I2C off while configuring */
209 stm_i2c->cr2 = AO_STM_I2C_CR2;
218 stm_i2c->ccr = ((1 << STM_I2C_CCR_FS) |
219 (0 << STM_I2C_CCR_DUTY) |
220 (20 << STM_I2C_CCR_CCR));
222 stm_i2c->cr1 = AO_STM_I2C_CR1;
228 /* All of the I2C configurations are on port B */
229 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN);
232 stm_afr_set(&stm_gpiob, 6, STM_AFR_AF4);
233 stm_afr_set(&stm_gpiob, 7, STM_AFR_AF4);
236 stm_afr_set(&stm_gpiob, 8, STM_AFR_AF4);
237 stm_afr_set(&stm_gpiob, 9, STM_AFR_AF4);
239 # error "No I2C_1 port configuration specified"
243 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C1EN);
244 ao_i2c_channel_init(0);
246 stm_nvic_set_enable(STM_ISR_I2C1_EV_POS);
247 stm_nvic_set_priority(STM_ISR_I2C1_EV_POS, 3);
248 stm_nvic_set_enable(STM_ISR_I2C1_ER_POS);
249 stm_nvic_set_priority(STM_ISR_I2C1_ER_POS, 3);
254 stm_afr_set(&stm_gpiob, 10, STM_AFR_AF4);
255 stm_afr_set(&stm_gpiob, 11, STM_AFR_AF4);
257 # error "No I2C_2 port configuration specified"
259 stm_rcc.apb1enr |= (1 << STM_RCC_APB1ENR_I2C2EN);
260 ao_i2c_channel_init(1);
262 stm_nvic_set_enable(STM_ISR_I2C2_EV_POS);
263 stm_nvic_set_priority(STM_ISR_I2C2_EV_POS, 3);
264 stm_nvic_set_enable(STM_ISR_I2C2_ER_POS);
265 stm_nvic_set_priority(STM_ISR_I2C2_ER_POS, 3);