2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #ifndef _AO_ARCH_FUNCS_H_
20 #define _AO_ARCH_FUNCS_H_
25 /* PCLK is set to 16MHz (HCLK 32MHz, APB prescaler 2) */
27 //#define AO_SPI_SPEED_8MHz STM_SPI_CR1_BR_PCLK_2 /* too fast to use safely */
28 #define _AO_SPI_SPEED_4MHz STM_SPI_CR1_BR_PCLK_4
29 #define _AO_SPI_SPEED_2MHz STM_SPI_CR1_BR_PCLK_8
30 #define _AO_SPI_SPEED_1MHz STM_SPI_CR1_BR_PCLK_16
31 #define _AO_SPI_SPEED_500kHz STM_SPI_CR1_BR_PCLK_32
32 #define _AO_SPI_SPEED_250kHz STM_SPI_CR1_BR_PCLK_64
33 #define _AO_SPI_SPEED_125kHz STM_SPI_CR1_BR_PCLK_128
34 #define _AO_SPI_SPEED_62500Hz STM_SPI_CR1_BR_PCLK_256
36 static inline uint32_t
37 ao_spi_speed(uint32_t hz)
39 if (hz >= 4000000) return _AO_SPI_SPEED_4MHz;
40 if (hz >= 2000000) return _AO_SPI_SPEED_2MHz;
41 if (hz >= 1000000) return _AO_SPI_SPEED_1MHz;
42 if (hz >= 500000) return _AO_SPI_SPEED_500kHz;
43 if (hz >= 250000) return _AO_SPI_SPEED_250kHz;
44 if (hz >= 125000) return _AO_SPI_SPEED_125kHz;
45 return _AO_SPI_SPEED_62500Hz;
48 #define AO_SPI_CPOL_BIT 4
49 #define AO_SPI_CPHA_BIT 5
51 #define AO_SPI_CONFIG_1 0x00
52 #define AO_SPI_1_CONFIG_PA5_PA6_PA7 AO_SPI_CONFIG_1
53 #define AO_SPI_2_CONFIG_PB13_PB14_PB15 AO_SPI_CONFIG_1
55 #define AO_SPI_CONFIG_2 0x04
56 #define AO_SPI_1_CONFIG_PB3_PB4_PB5 AO_SPI_CONFIG_2
57 #define AO_SPI_2_CONFIG_PD1_PD3_PD4 AO_SPI_CONFIG_2
59 #define AO_SPI_CONFIG_3 0x08
60 #define AO_SPI_1_CONFIG_PE13_PE14_PE15 AO_SPI_CONFIG_3
62 #define AO_SPI_CONFIG_NONE 0x0c
64 #define AO_SPI_INDEX_MASK 0x01
65 #define AO_SPI_CONFIG_MASK 0x0c
67 #define AO_SPI_1_PA5_PA6_PA7 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA5_PA6_PA7)
68 #define AO_SPI_1_PB3_PB4_PB5 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PB3_PB4_PB5)
69 #define AO_SPI_1_PE13_PE14_PE15 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PE13_PE14_PE15)
71 #define AO_SPI_2_PB13_PB14_PB15 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PB13_PB14_PB15)
72 #define AO_SPI_2_PD1_PD3_PD4 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PD1_PD3_PD4)
74 #define AO_SPI_INDEX(id) ((id) & AO_SPI_INDEX_MASK)
75 #define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
76 #define AO_SPI_PIN_CONFIG(id) ((id) & (AO_SPI_INDEX_MASK | AO_SPI_CONFIG_MASK))
77 #define AO_SPI_CPOL(id) ((uint32_t) (((id) >> AO_SPI_CPOL_BIT) & 1))
78 #define AO_SPI_CPHA(id) ((uint32_t) (((id) >> AO_SPI_CPHA_BIT) & 1))
80 #define AO_SPI_MAKE_MODE(pol,pha) (((pol) << AO_SPI_CPOL_BIT) | ((pha) << AO_SPI_CPHA_BIT))
81 #define AO_SPI_MODE_0 AO_SPI_MAKE_MODE(0,0)
82 #define AO_SPI_MODE_1 AO_SPI_MAKE_MODE(0,1)
83 #define AO_SPI_MODE_2 AO_SPI_MAKE_MODE(1,0)
84 #define AO_SPI_MODE_3 AO_SPI_MAKE_MODE(1,1)
87 ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id);
90 ao_spi_get(uint8_t spi_index, uint32_t speed);
93 ao_spi_put(uint8_t spi_index);
96 ao_spi_send(const void *block, uint16_t len, uint8_t spi_index);
99 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
102 ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index);
105 ao_spi_start_bytes(uint8_t spi_index);
108 ao_spi_stop_bytes(uint8_t spi_index);
111 ao_spi_send_byte(uint8_t byte, uint8_t spi_index)
113 struct stm_spi *stm_spi;
115 switch (AO_SPI_INDEX(spi_index)) {
124 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
127 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
132 static inline uint8_t
133 ao_spi_recv_byte(uint8_t spi_index)
135 struct stm_spi *stm_spi;
137 switch (AO_SPI_INDEX(spi_index)) {
146 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
149 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
151 return (uint8_t) stm_spi->dr;
155 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
158 ao_spi_duplex(const void *out, void *in, uint16_t len, uint8_t spi_index);
163 #define ao_spi_set_cs(reg,mask) ((reg)->bsrr = ((uint32_t) (mask)) << 16)
164 #define ao_spi_clr_cs(reg,mask) ((reg)->bsrr = (mask))
166 #define ao_spi_get_mask(reg,mask,bus, speed) do { \
167 ao_spi_get(bus, speed); \
168 ao_spi_set_cs(reg,mask); \
171 static inline uint8_t
172 ao_spi_try_get_mask(struct stm_gpio *reg, uint16_t mask, uint8_t bus, uint32_t speed, uint8_t task_id)
174 if (!ao_spi_try_get(bus, speed, task_id))
176 ao_spi_set_cs(reg, mask);
180 #define ao_spi_put_mask(reg,mask,bus) do { \
181 ao_spi_clr_cs(reg,mask); \
185 #define ao_spi_get_bit(reg,bit,bus,speed) ao_spi_get_mask(reg,1<<(bit),bus,speed)
186 #define ao_spi_put_bit(reg,bit,bus) ao_spi_put_mask(reg,1<<(bit),bus)
188 #define ao_enable_port(port) do { \
189 if ((port) == &stm_gpioa) \
190 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN); \
191 else if ((port) == &stm_gpiob) \
192 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN); \
193 else if ((port) == &stm_gpioc) \
194 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOCEN); \
195 else if ((port) == &stm_gpiod) \
196 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIODEN); \
197 else if ((port) == &stm_gpioe) \
198 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOEEN); \
201 #define ao_disable_port(port) do { \
202 if ((port) == &stm_gpioa) \
203 stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIOAEN); \
204 else if ((port) == &stm_gpiob) \
205 stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIOBEN); \
206 else if ((port) == &stm_gpioc) \
207 stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIOCEN); \
208 else if ((port) == &stm_gpiod) \
209 stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIODEN); \
210 else if ((port) == &stm_gpioe) \
211 stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIOEEN); \
215 #define ao_gpio_set(port, bit, v) stm_gpio_set(port, bit, v)
217 #define ao_gpio_get(port, bit) stm_gpio_get(port, bit)
219 #define ao_gpio_set_bits(port, bits) stm_gpio_set_bits(port, bits)
221 #define ao_gpio_set_mask(port, bits, mask) stm_gpio_set_mask(port, bits, mask)
223 #define ao_gpio_clr_bits(port, bits) stm_gpio_clr_bits(port, bits);
225 #define ao_gpio_get_all(port) stm_gpio_get_all(port)
227 #define ao_enable_output(port,bit,v) do { \
228 ao_enable_port(port); \
229 ao_gpio_set(port, bit, v); \
230 stm_moder_set(port, bit, STM_MODER_OUTPUT);\
233 #define ao_enable_output_mask(port,bits,mask) do { \
234 ao_enable_port(port); \
235 ao_gpio_set_mask(port, bits, mask); \
236 ao_set_output_mask(port, mask); \
239 #define AO_OUTPUT_PUSH_PULL STM_OTYPER_PUSH_PULL
240 #define AO_OUTPUT_OPEN_DRAIN STM_OTYPER_OPEN_DRAIN
242 #define ao_gpio_set_output_mode(port,pin,mode) \
243 stm_otyper_set(port, pin, mode)
245 #define ao_gpio_set_mode(port,bit,mode) do { \
246 if (mode == AO_EXTI_MODE_PULL_UP) \
247 stm_pupdr_set(port, bit, STM_PUPDR_PULL_UP); \
248 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
249 stm_pupdr_set(port, bit, STM_PUPDR_PULL_DOWN); \
251 stm_pupdr_set(port, bit, STM_PUPDR_NONE); \
254 #define ao_gpio_set_mode_mask(port,mask,mode) do { \
255 if (mode == AO_EXTI_MODE_PULL_UP) \
256 stm_pupdr_set_mask(port, mask, STM_PUPDR_PULL_UP); \
257 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
258 stm_pupdr_set_mask(port, mask, STM_PUPDR_PULL_DOWN); \
260 stm_pupdr_set_mask(port, mask, STM_PUPDR_NONE); \
263 #define ao_set_input(port, bit) do { \
264 stm_moder_set(port, bit, STM_MODER_INPUT); \
267 #define ao_set_output(port, bit, v) do { \
268 ao_gpio_set(port, bit, v); \
269 stm_moder_set(port, bit, STM_MODER_OUTPUT); \
272 #define ao_set_output_mask(port, mask) do { \
273 stm_moder_set_mask(port, mask, STM_MODER_OUTPUT); \
276 #define ao_set_input_mask(port, mask) do { \
277 stm_moder_set_mask(port, mask, STM_MODER_INPUT); \
280 #define ao_enable_input(port,bit,mode) do { \
281 ao_enable_port(port); \
282 ao_set_input(port, bit); \
283 ao_gpio_set_mode(port, bit, mode); \
286 #define ao_enable_input_mask(port,mask,mode) do { \
287 ao_enable_port(port); \
288 ao_gpio_set_mode_mask(port, mask, mode); \
289 ao_set_input_mask(port, mask); \
292 #define _ao_enable_cs(port, bit) do { \
293 stm_gpio_set((port), bit, 1); \
294 stm_moder_set((port), bit, STM_MODER_OUTPUT); \
297 #define ao_enable_cs(port,bit) do { \
298 ao_enable_port(port); \
299 _ao_enable_cs(port, bit); \
302 #define ao_spi_init_cs(port, mask) do { \
303 ao_enable_port(port); \
304 if ((mask) & 0x0001) _ao_enable_cs(port, 0); \
305 if ((mask) & 0x0002) _ao_enable_cs(port, 1); \
306 if ((mask) & 0x0004) _ao_enable_cs(port, 2); \
307 if ((mask) & 0x0008) _ao_enable_cs(port, 3); \
308 if ((mask) & 0x0010) _ao_enable_cs(port, 4); \
309 if ((mask) & 0x0020) _ao_enable_cs(port, 5); \
310 if ((mask) & 0x0040) _ao_enable_cs(port, 6); \
311 if ((mask) & 0x0080) _ao_enable_cs(port, 7); \
312 if ((mask) & 0x0100) _ao_enable_cs(port, 8); \
313 if ((mask) & 0x0200) _ao_enable_cs(port, 9); \
314 if ((mask) & 0x0400) _ao_enable_cs(port, 10);\
315 if ((mask) & 0x0800) _ao_enable_cs(port, 11);\
316 if ((mask) & 0x1000) _ao_enable_cs(port, 12);\
317 if ((mask) & 0x2000) _ao_enable_cs(port, 13);\
318 if ((mask) & 0x4000) _ao_enable_cs(port, 14);\
319 if ((mask) & 0x8000) _ao_enable_cs(port, 15);\
325 extern uint8_t ao_dma_done[STM_NUM_DMA];
328 ao_dma_set_transfer(uint8_t index,
329 volatile void *peripheral,
335 ao_dma_set_isr(uint8_t index, void (*isr)(int index));
338 ao_dma_start(uint8_t index);
341 ao_dma_done_transfer(uint8_t index);
344 ao_dma_alloc(uint8_t index);
352 ao_i2c_get(uint8_t i2c_index);
355 ao_i2c_start(uint8_t i2c_index, uint16_t address);
358 ao_i2c_put(uint8_t i2c_index);
361 ao_i2c_send(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
364 ao_i2c_recv(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
369 #if USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_SW_FLOW || USE_SERIAL_3_SW_FLOW
370 #define HAS_SERIAL_SW_FLOW 1
372 #define HAS_SERIAL_SW_FLOW 0
375 #if USE_SERIAL_1_FLOW && !USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_FLOW && !USE_SERIAL_2_SW_FLOW || USE_SERIAL_3_FLOW && !USE_SERIAL_3_SW_FLOW
376 #define HAS_SERIAL_HW_FLOW 1
378 #define HAS_SERIAL_HW_FLOW 0
381 /* ao_serial_stm.c */
382 struct ao_stm_usart {
383 struct ao_fifo rx_fifo;
384 struct ao_fifo tx_fifo;
385 struct stm_usart *reg;
388 #if HAS_SERIAL_SW_FLOW
389 /* RTS - 0 if we have FIFO space, 1 if not
390 * CTS - 0 if we can send, 0 if not
392 struct stm_gpio *gpio_rts;
393 struct stm_gpio *gpio_cts;
401 ao_debug_out(char c);
404 extern struct ao_stm_usart ao_stm_usart1;
408 extern struct ao_stm_usart ao_stm_usart2;
412 extern struct ao_stm_usart ao_stm_usart3;
415 #define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
417 typedef uint32_t ao_arch_irq_t;
420 ao_arch_block_interrupts(void) {
421 #ifdef AO_NONMASK_INTERRUPTS
422 asm("msr basepri,%0" : : "r" (AO_STM_NVIC_BASEPRI_MASK));
429 ao_arch_release_interrupts(void) {
430 #ifdef AO_NONMASK_INTERRUPTS
431 asm("msr basepri,%0" : : "r" (0x0));
437 static inline uint32_t
438 ao_arch_irqsave(void) {
440 #ifdef AO_NONMASK_INTERRUPTS
441 asm("mrs %0,basepri" : "=r" (val));
443 asm("mrs %0,primask" : "=r" (val));
445 ao_arch_block_interrupts();
450 ao_arch_irqrestore(uint32_t basepri) {
451 #ifdef AO_NONMASK_INTERRUPTS
452 asm("msr basepri,%0" : : "r" (basepri));
454 asm("msr primask,%0" : : "r" (basepri));
459 ao_arch_memory_barrier(void) {
460 asm volatile("" ::: "memory");
464 ao_arch_irq_check(void) {
465 #ifdef AO_NONMASK_INTERRUPTS
467 asm("mrs %0,basepri" : "=r" (basepri));
469 ao_panic(AO_PANIC_IRQ);
472 asm("mrs %0,primask" : "=r" (primask));
473 if ((primask & 1) == 0)
474 ao_panic(AO_PANIC_IRQ);
480 ao_arch_init_stack(struct ao_task *task, uint32_t *sp, void *start)
482 uint32_t a = (uint32_t) start;
485 /* Return address (goes into LR) */
488 /* Clear register values r0-r12 */
496 /* BASEPRI with interrupts enabled */
502 static inline void ao_arch_save_regs(void) {
503 /* Save general registers */
504 asm("push {r0-r12,lr}\n");
510 #ifdef AO_NONMASK_INTERRUPTS
512 asm("mrs r0,basepri");
515 asm("mrs r0,primask");
520 static inline void ao_arch_save_stack(void) {
522 asm("mov %0,sp" : "=&r" (sp) );
523 ao_cur_task->sp32 = (sp);
526 static inline void ao_arch_restore_stack(void) {
528 asm("mov sp, %0" : : "r" (ao_cur_task->sp32) );
530 #ifdef AO_NONMASK_INTERRUPTS
531 /* Restore BASEPRI */
533 asm("msr basepri,r0");
535 /* Restore PRIMASK */
537 asm("msr primask,r0");
542 asm("msr apsr_nczvq,r0");
544 /* Restore general registers */
545 asm("pop {r0-r12,lr}\n");
547 /* Return to calling function */
551 #ifndef HAS_SAMPLE_PROFILE
552 #define HAS_SAMPLE_PROFILE 0
556 #define HAS_ARCH_VALIDATE_CUR_STACK 1
559 ao_validate_cur_stack(void)
563 asm("mrs %0,psp" : "=&r" (psp));
565 (psp <= ao_cur_task->stack8 ||
566 psp >= ao_cur_task->stack8 + AO_STACK_SIZE))
567 ao_panic(AO_PANIC_STACK);
571 #if !HAS_SAMPLE_PROFILE
572 #define HAS_ARCH_START_SCHEDULER 1
574 static inline void ao_arch_start_scheduler(void) {
578 asm("mrs %0,msp" : "=&r" (sp));
579 asm("msr psp,%0" : : "r" (sp));
580 asm("mrs %0,control" : "=r" (control));
582 asm("msr control,%0" : : "r" (control));
587 #define ao_arch_isr_stack()
592 ao_arch_wait_interrupt(void) {
593 #ifdef AO_NONMASK_INTERRUPTS
595 "dsb\n" /* Serialize data */
596 "isb\n" /* Serialize instructions */
597 "cpsid i\n" /* Block all interrupts */
598 "msr basepri,%0\n" /* Allow all interrupts through basepri */
599 "wfi\n" /* Wait for an interrupt */
600 "cpsie i\n" /* Allow all interrupts */
601 "msr basepri,%1\n" /* Block interrupts through basepri */
602 : : "r" (0), "r" (AO_STM_NVIC_BASEPRI_MASK));
605 ao_arch_release_interrupts();
606 ao_arch_block_interrupts();
610 #define ao_arch_critical(b) do { \
611 uint32_t __mask = ao_arch_irqsave(); \
612 do { b } while (0); \
613 ao_arch_irqrestore(__mask); \
618 #endif /* _AO_ARCH_FUNCS_H_ */