2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #ifndef _AO_ARCH_FUNCS_H_
20 #define _AO_ARCH_FUNCS_H_
25 /* PCLK is set to 16MHz (HCLK 32MHz, APB prescaler 2) */
27 //#define AO_SPI_SPEED_8MHz STM_SPI_CR1_BR_PCLK_2 /* too fast to use safely */
28 #define _AO_SPI_SPEED_4MHz STM_SPI_CR1_BR_PCLK_4
29 #define _AO_SPI_SPEED_2MHz STM_SPI_CR1_BR_PCLK_8
30 #define _AO_SPI_SPEED_1MHz STM_SPI_CR1_BR_PCLK_16
31 #define _AO_SPI_SPEED_500kHz STM_SPI_CR1_BR_PCLK_32
32 #define _AO_SPI_SPEED_250kHz STM_SPI_CR1_BR_PCLK_64
33 #define _AO_SPI_SPEED_125kHz STM_SPI_CR1_BR_PCLK_128
34 #define _AO_SPI_SPEED_62500Hz STM_SPI_CR1_BR_PCLK_256
36 static inline uint32_t
37 ao_spi_speed(uint32_t hz)
39 if (hz >= 4000000) return _AO_SPI_SPEED_4MHz;
40 if (hz >= 2000000) return _AO_SPI_SPEED_2MHz;
41 if (hz >= 1000000) return _AO_SPI_SPEED_1MHz;
42 if (hz >= 500000) return _AO_SPI_SPEED_500kHz;
43 if (hz >= 250000) return _AO_SPI_SPEED_250kHz;
44 if (hz >= 125000) return _AO_SPI_SPEED_125kHz;
45 return _AO_SPI_SPEED_62500Hz;
48 #define AO_SPI_CPOL_BIT 4
49 #define AO_SPI_CPHA_BIT 5
51 #define AO_SPI_CONFIG_1 0x00
52 #define AO_SPI_1_CONFIG_PA5_PA6_PA7 AO_SPI_CONFIG_1
53 #define AO_SPI_2_CONFIG_PB13_PB14_PB15 AO_SPI_CONFIG_1
55 #define AO_SPI_CONFIG_2 0x04
56 #define AO_SPI_1_CONFIG_PB3_PB4_PB5 AO_SPI_CONFIG_2
57 #define AO_SPI_2_CONFIG_PD1_PD3_PD4 AO_SPI_CONFIG_2
59 #define AO_SPI_CONFIG_3 0x08
60 #define AO_SPI_1_CONFIG_PE13_PE14_PE15 AO_SPI_CONFIG_3
62 #define AO_SPI_CONFIG_NONE 0x0c
64 #define AO_SPI_INDEX_MASK 0x01
65 #define AO_SPI_CONFIG_MASK 0x0c
67 #define AO_SPI_1_PA5_PA6_PA7 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA5_PA6_PA7)
68 #define AO_SPI_1_PB3_PB4_PB5 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PB3_PB4_PB5)
69 #define AO_SPI_1_PE13_PE14_PE15 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PE13_PE14_PE15)
71 #define AO_SPI_2_PB13_PB14_PB15 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PB13_PB14_PB15)
72 #define AO_SPI_2_PD1_PD3_PD4 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PD1_PD3_PD4)
74 #define AO_SPI_INDEX(id) ((id) & AO_SPI_INDEX_MASK)
75 #define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
76 #define AO_SPI_PIN_CONFIG(id) ((id) & (AO_SPI_INDEX_MASK | AO_SPI_CONFIG_MASK))
77 #define AO_SPI_CPOL(id) ((uint32_t) (((id) >> AO_SPI_CPOL_BIT) & 1))
78 #define AO_SPI_CPHA(id) ((uint32_t) (((id) >> AO_SPI_CPHA_BIT) & 1))
80 #define AO_SPI_MAKE_MODE(pol,pha) (((pol) << AO_SPI_CPOL_BIT) | ((pha) << AO_SPI_CPHA_BIT))
81 #define AO_SPI_MODE_0 AO_SPI_MAKE_MODE(0,0)
82 #define AO_SPI_MODE_1 AO_SPI_MAKE_MODE(0,1)
83 #define AO_SPI_MODE_2 AO_SPI_MAKE_MODE(1,0)
84 #define AO_SPI_MODE_3 AO_SPI_MAKE_MODE(1,1)
87 ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id);
90 ao_spi_get(uint8_t spi_index, uint32_t speed);
93 ao_spi_put(uint8_t spi_index);
96 ao_spi_put_pins(uint8_t spi_index);
99 ao_spi_send(const void *block, uint16_t len, uint8_t spi_index);
102 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
105 ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index);
108 ao_spi_start_bytes(uint8_t spi_index);
111 ao_spi_stop_bytes(uint8_t spi_index);
114 ao_spi_send_byte(uint8_t byte, uint8_t spi_index)
116 struct stm_spi *stm_spi;
118 switch (AO_SPI_INDEX(spi_index)) {
127 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
130 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
135 static inline uint8_t
136 ao_spi_recv_byte(uint8_t spi_index)
138 struct stm_spi *stm_spi;
140 switch (AO_SPI_INDEX(spi_index)) {
149 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
152 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
154 return (uint8_t) stm_spi->dr;
158 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
161 ao_spi_duplex(const void *out, void *in, uint16_t len, uint8_t spi_index);
166 #define ao_spi_set_cs(reg,mask) ((reg)->bsrr = ((uint32_t) (mask)) << 16)
167 #define ao_spi_clr_cs(reg,mask) ((reg)->bsrr = (mask))
169 #define ao_spi_get_mask(reg,mask,bus, speed) do { \
170 ao_spi_get(bus, speed); \
171 ao_spi_set_cs(reg,mask); \
174 static inline uint8_t
175 ao_spi_try_get_mask(struct stm_gpio *reg, uint16_t mask, uint8_t bus, uint32_t speed, uint8_t task_id)
177 if (!ao_spi_try_get(bus, speed, task_id))
179 ao_spi_set_cs(reg, mask);
183 #define ao_spi_put_mask(reg,mask,bus) do { \
184 ao_spi_clr_cs(reg,mask); \
188 #define ao_spi_get_bit(reg,bit,bus,speed) ao_spi_get_mask(reg,1<<(bit),bus,speed)
189 #define ao_spi_put_bit(reg,bit,bus) ao_spi_put_mask(reg,1<<(bit),bus)
191 #define ao_enable_port(port) do { \
192 if ((port) == &stm_gpioa) \
193 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN); \
194 else if ((port) == &stm_gpiob) \
195 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN); \
196 else if ((port) == &stm_gpioc) \
197 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOCEN); \
198 else if ((port) == &stm_gpiod) \
199 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIODEN); \
200 else if ((port) == &stm_gpioe) \
201 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOEEN); \
204 #define ao_disable_port(port) do { \
205 if ((port) == &stm_gpioa) \
206 stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIOAEN); \
207 else if ((port) == &stm_gpiob) \
208 stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIOBEN); \
209 else if ((port) == &stm_gpioc) \
210 stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIOCEN); \
211 else if ((port) == &stm_gpiod) \
212 stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIODEN); \
213 else if ((port) == &stm_gpioe) \
214 stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIOEEN); \
218 #define ao_gpio_set(port, bit, v) stm_gpio_set(port, bit, v)
220 #define ao_gpio_get(port, bit) stm_gpio_get(port, bit)
222 #define ao_gpio_set_bits(port, bits) stm_gpio_set_bits(port, bits)
224 #define ao_gpio_set_mask(port, bits, mask) stm_gpio_set_mask(port, bits, mask)
226 #define ao_gpio_clr_bits(port, bits) stm_gpio_clr_bits(port, bits);
228 #define ao_gpio_get_all(port) stm_gpio_get_all(port)
230 #define ao_enable_output(port,bit,v) do { \
231 ao_enable_port(port); \
232 ao_gpio_set(port, bit, v); \
233 stm_moder_set(port, bit, STM_MODER_OUTPUT);\
236 #define ao_enable_output_mask(port,bits,mask) do { \
237 ao_enable_port(port); \
238 ao_gpio_set_mask(port, bits, mask); \
239 ao_set_output_mask(port, mask); \
242 #define AO_OUTPUT_PUSH_PULL STM_OTYPER_PUSH_PULL
243 #define AO_OUTPUT_OPEN_DRAIN STM_OTYPER_OPEN_DRAIN
245 #define ao_gpio_set_output_mode(port,pin,mode) \
246 stm_otyper_set(port, pin, mode)
248 #define ao_gpio_set_mode(port,bit,mode) do { \
249 if (mode == AO_EXTI_MODE_PULL_UP) \
250 stm_pupdr_set(port, bit, STM_PUPDR_PULL_UP); \
251 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
252 stm_pupdr_set(port, bit, STM_PUPDR_PULL_DOWN); \
254 stm_pupdr_set(port, bit, STM_PUPDR_NONE); \
257 #define ao_gpio_set_mode_mask(port,mask,mode) do { \
258 if (mode == AO_EXTI_MODE_PULL_UP) \
259 stm_pupdr_set_mask(port, mask, STM_PUPDR_PULL_UP); \
260 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
261 stm_pupdr_set_mask(port, mask, STM_PUPDR_PULL_DOWN); \
263 stm_pupdr_set_mask(port, mask, STM_PUPDR_NONE); \
266 #define ao_set_input(port, bit) do { \
267 stm_moder_set(port, bit, STM_MODER_INPUT); \
270 #define ao_set_output(port, bit, v) do { \
271 ao_gpio_set(port, bit, v); \
272 stm_moder_set(port, bit, STM_MODER_OUTPUT); \
275 #define ao_set_output_mask(port, mask) do { \
276 stm_moder_set_mask(port, mask, STM_MODER_OUTPUT); \
279 #define ao_set_input_mask(port, mask) do { \
280 stm_moder_set_mask(port, mask, STM_MODER_INPUT); \
283 #define ao_enable_input(port,bit,mode) do { \
284 ao_enable_port(port); \
285 ao_set_input(port, bit); \
286 ao_gpio_set_mode(port, bit, mode); \
289 #define ao_enable_input_mask(port,mask,mode) do { \
290 ao_enable_port(port); \
291 ao_gpio_set_mode_mask(port, mask, mode); \
292 ao_set_input_mask(port, mask); \
295 #define _ao_enable_cs(port, bit) do { \
296 stm_gpio_set((port), bit, 1); \
297 stm_moder_set((port), bit, STM_MODER_OUTPUT); \
300 #define ao_enable_cs(port,bit) do { \
301 ao_enable_port(port); \
302 _ao_enable_cs(port, bit); \
305 #define ao_spi_init_cs(port, mask) do { \
306 ao_enable_port(port); \
307 if ((mask) & 0x0001) _ao_enable_cs(port, 0); \
308 if ((mask) & 0x0002) _ao_enable_cs(port, 1); \
309 if ((mask) & 0x0004) _ao_enable_cs(port, 2); \
310 if ((mask) & 0x0008) _ao_enable_cs(port, 3); \
311 if ((mask) & 0x0010) _ao_enable_cs(port, 4); \
312 if ((mask) & 0x0020) _ao_enable_cs(port, 5); \
313 if ((mask) & 0x0040) _ao_enable_cs(port, 6); \
314 if ((mask) & 0x0080) _ao_enable_cs(port, 7); \
315 if ((mask) & 0x0100) _ao_enable_cs(port, 8); \
316 if ((mask) & 0x0200) _ao_enable_cs(port, 9); \
317 if ((mask) & 0x0400) _ao_enable_cs(port, 10);\
318 if ((mask) & 0x0800) _ao_enable_cs(port, 11);\
319 if ((mask) & 0x1000) _ao_enable_cs(port, 12);\
320 if ((mask) & 0x2000) _ao_enable_cs(port, 13);\
321 if ((mask) & 0x4000) _ao_enable_cs(port, 14);\
322 if ((mask) & 0x8000) _ao_enable_cs(port, 15);\
328 extern uint8_t ao_dma_done[STM_NUM_DMA];
331 ao_dma_set_transfer(uint8_t index,
332 volatile void *peripheral,
338 ao_dma_set_isr(uint8_t index, void (*isr)(int index));
341 ao_dma_start(uint8_t index);
344 ao_dma_done_transfer(uint8_t index);
347 ao_dma_alloc(uint8_t index);
355 ao_i2c_get(uint8_t i2c_index);
358 ao_i2c_start(uint8_t i2c_index, uint16_t address);
361 ao_i2c_put(uint8_t i2c_index);
364 ao_i2c_send(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
367 ao_i2c_recv(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
372 #if USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_SW_FLOW || USE_SERIAL_3_SW_FLOW
373 #define HAS_SERIAL_SW_FLOW 1
375 #define HAS_SERIAL_SW_FLOW 0
378 #if USE_SERIAL_1_FLOW && !USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_FLOW && !USE_SERIAL_2_SW_FLOW || USE_SERIAL_3_FLOW && !USE_SERIAL_3_SW_FLOW
379 #define HAS_SERIAL_HW_FLOW 1
381 #define HAS_SERIAL_HW_FLOW 0
384 /* ao_serial_stm.c */
385 struct ao_stm_usart {
386 struct ao_fifo rx_fifo;
387 struct ao_fifo tx_fifo;
388 struct stm_usart *reg;
391 #if HAS_SERIAL_SW_FLOW
392 /* RTS - 0 if we have FIFO space, 1 if not
393 * CTS - 0 if we can send, 0 if not
395 struct stm_gpio *gpio_rts;
396 struct stm_gpio *gpio_cts;
404 ao_debug_out(char c);
407 extern struct ao_stm_usart ao_stm_usart1;
411 extern struct ao_stm_usart ao_stm_usart2;
415 extern struct ao_stm_usart ao_stm_usart3;
418 #define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
420 typedef uint32_t ao_arch_irq_t;
423 ao_arch_block_interrupts(void) {
424 #ifdef AO_NONMASK_INTERRUPTS
425 asm("msr basepri,%0" : : "r" (AO_STM_NVIC_BASEPRI_MASK));
432 ao_arch_release_interrupts(void) {
433 #ifdef AO_NONMASK_INTERRUPTS
434 asm("msr basepri,%0" : : "r" (0x0));
440 static inline uint32_t
441 ao_arch_irqsave(void) {
443 #ifdef AO_NONMASK_INTERRUPTS
444 asm("mrs %0,basepri" : "=r" (val));
446 asm("mrs %0,primask" : "=r" (val));
448 ao_arch_block_interrupts();
453 ao_arch_irqrestore(uint32_t basepri) {
454 #ifdef AO_NONMASK_INTERRUPTS
455 asm("msr basepri,%0" : : "r" (basepri));
457 asm("msr primask,%0" : : "r" (basepri));
462 ao_arch_memory_barrier(void) {
463 asm volatile("" ::: "memory");
467 ao_arch_irq_check(void) {
468 #ifdef AO_NONMASK_INTERRUPTS
470 asm("mrs %0,basepri" : "=r" (basepri));
472 ao_panic(AO_PANIC_IRQ);
475 asm("mrs %0,primask" : "=r" (primask));
476 if ((primask & 1) == 0)
477 ao_panic(AO_PANIC_IRQ);
483 ao_arch_init_stack(struct ao_task *task, uint32_t *sp, void *start)
485 uint32_t a = (uint32_t) start;
488 /* Return address (goes into LR) */
491 /* Clear register values r0-r12 */
499 /* BASEPRI with interrupts enabled */
505 static inline void ao_arch_save_regs(void) {
506 /* Save general registers */
507 asm("push {r0-r12,lr}\n");
513 #ifdef AO_NONMASK_INTERRUPTS
515 asm("mrs r0,basepri");
518 asm("mrs r0,primask");
523 static inline void ao_arch_save_stack(void) {
525 asm("mov %0,sp" : "=&r" (sp) );
526 ao_cur_task->sp32 = (sp);
529 static inline void ao_arch_restore_stack(void) {
531 asm("mov sp, %0" : : "r" (ao_cur_task->sp32) );
533 #ifdef AO_NONMASK_INTERRUPTS
534 /* Restore BASEPRI */
536 asm("msr basepri,r0");
538 /* Restore PRIMASK */
540 asm("msr primask,r0");
545 asm("msr apsr_nczvq,r0");
547 /* Restore general registers */
548 asm("pop {r0-r12,lr}\n");
550 /* Return to calling function */
554 #ifndef HAS_SAMPLE_PROFILE
555 #define HAS_SAMPLE_PROFILE 0
559 #define HAS_ARCH_VALIDATE_CUR_STACK 1
562 ao_validate_cur_stack(void)
566 asm("mrs %0,psp" : "=&r" (psp));
568 (psp <= ao_cur_task->stack8 ||
569 psp >= ao_cur_task->stack8 + AO_STACK_SIZE))
570 ao_panic(AO_PANIC_STACK);
574 #if !HAS_SAMPLE_PROFILE
575 #define HAS_ARCH_START_SCHEDULER 1
577 static inline void ao_arch_start_scheduler(void) {
581 asm("mrs %0,msp" : "=&r" (sp));
582 asm("msr psp,%0" : : "r" (sp));
583 asm("mrs %0,control" : "=r" (control));
585 asm("msr control,%0" : : "r" (control));
590 #define ao_arch_isr_stack()
595 ao_arch_wait_interrupt(void) {
596 #ifdef AO_NONMASK_INTERRUPTS
598 "dsb\n" /* Serialize data */
599 "isb\n" /* Serialize instructions */
600 "cpsid i\n" /* Block all interrupts */
601 "msr basepri,%0\n" /* Allow all interrupts through basepri */
602 "wfi\n" /* Wait for an interrupt */
603 "cpsie i\n" /* Allow all interrupts */
604 "msr basepri,%1\n" /* Block interrupts through basepri */
605 : : "r" (0), "r" (AO_STM_NVIC_BASEPRI_MASK));
608 ao_arch_release_interrupts();
609 ao_arch_block_interrupts();
613 #define ao_arch_critical(b) do { \
614 uint32_t __mask = ao_arch_irqsave(); \
615 do { b } while (0); \
616 ao_arch_irqrestore(__mask); \
621 #endif /* _AO_ARCH_FUNCS_H_ */