2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
18 #ifndef _AO_ARCH_FUNCS_H_
19 #define _AO_ARCH_FUNCS_H_
24 /* PCLK is set to 16MHz (HCLK 32MHz, APB prescaler 2) */
26 #define AO_SPI_SPEED_8MHz STM_SPI_CR1_BR_PCLK_2
27 #define AO_SPI_SPEED_4MHz STM_SPI_CR1_BR_PCLK_4
28 #define AO_SPI_SPEED_2MHz STM_SPI_CR1_BR_PCLK_8
29 #define AO_SPI_SPEED_1MHz STM_SPI_CR1_BR_PCLK_16
30 #define AO_SPI_SPEED_500kHz STM_SPI_CR1_BR_PCLK_32
31 #define AO_SPI_SPEED_250kHz STM_SPI_CR1_BR_PCLK_64
32 #define AO_SPI_SPEED_125kHz STM_SPI_CR1_BR_PCLK_128
33 #define AO_SPI_SPEED_62500Hz STM_SPI_CR1_BR_PCLK_256
35 #define AO_SPI_SPEED_FAST AO_SPI_SPEED_8MHz
37 /* Companion bus wants something no faster than 200kHz */
39 #define AO_SPI_SPEED_200kHz AO_SPI_SPEED_125kHz
41 #define AO_SPI_CONFIG_1 0x00
42 #define AO_SPI_1_CONFIG_PA5_PA6_PA7 AO_SPI_CONFIG_1
43 #define AO_SPI_2_CONFIG_PB13_PB14_PB15 AO_SPI_CONFIG_1
45 #define AO_SPI_CONFIG_2 0x04
46 #define AO_SPI_1_CONFIG_PB3_PB4_PB5 AO_SPI_CONFIG_2
47 #define AO_SPI_2_CONFIG_PD1_PD3_PD4 AO_SPI_CONFIG_2
49 #define AO_SPI_CONFIG_3 0x08
50 #define AO_SPI_1_CONFIG_PE13_PE14_PE15 AO_SPI_CONFIG_3
52 #define AO_SPI_CONFIG_NONE 0x0c
54 #define AO_SPI_INDEX_MASK 0x01
55 #define AO_SPI_CONFIG_MASK 0x0c
57 #define AO_SPI_1_PA5_PA6_PA7 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA5_PA6_PA7)
58 #define AO_SPI_1_PB3_PB4_PB5 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PB3_PB4_PB5)
59 #define AO_SPI_1_PE13_PE14_PE15 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PE13_PE14_PE15)
61 #define AO_SPI_2_PB13_PB14_PB15 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PB13_PB14_PB15)
62 #define AO_SPI_2_PD1_PD3_PD4 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PD1_PD3_PD4)
64 #define AO_SPI_INDEX(id) ((id) & AO_SPI_INDEX_MASK)
65 #define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
68 ao_spi_get(uint8_t spi_index, uint32_t speed);
71 ao_spi_put(uint8_t spi_index);
74 ao_spi_send(void *block, uint16_t len, uint8_t spi_index);
77 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
80 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
83 ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index);
85 extern uint16_t ao_spi_speed[STM_NUM_SPI];
90 #define ao_spi_set_cs(reg,mask) ((reg)->bsrr = ((uint32_t) (mask)) << 16)
91 #define ao_spi_clr_cs(reg,mask) ((reg)->bsrr = (mask))
93 #define ao_spi_get_mask(reg,mask,bus, speed) do { \
94 ao_spi_get(bus, speed); \
95 ao_spi_set_cs(reg,mask); \
98 #define ao_spi_put_mask(reg,mask,bus) do { \
99 ao_spi_clr_cs(reg,mask); \
103 #define ao_spi_get_bit(reg,bit,pin,bus,speed) ao_spi_get_mask(reg,(1<<bit),bus,speed)
104 #define ao_spi_put_bit(reg,bit,pin,bus) ao_spi_put_mask(reg,(1<<bit),bus)
106 #define ao_enable_port(port) do { \
107 if ((port) == &stm_gpioa) \
108 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN); \
109 else if ((port) == &stm_gpiob) \
110 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN); \
111 else if ((port) == &stm_gpioc) \
112 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOCEN); \
113 else if ((port) == &stm_gpiod) \
114 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIODEN); \
115 else if ((port) == &stm_gpioe) \
116 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOEEN); \
119 #define ao_disable_port(port) do { \
120 if ((port) == &stm_gpioa) \
121 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOAEN); \
122 else if ((port) == &stm_gpiob) \
123 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOBEN); \
124 else if ((port) == &stm_gpioc) \
125 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOCEN); \
126 else if ((port) == &stm_gpiod) \
127 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIODEN); \
128 else if ((port) == &stm_gpioe) \
129 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOEEN); \
133 #define ao_gpio_set(port, bit, pin, v) stm_gpio_set(port, bit, v)
135 #define ao_gpio_get(port, bit, pin) stm_gpio_get(port, bit)
137 #define ao_enable_output(port,bit,pin,v) do { \
138 ao_enable_port(port); \
139 ao_gpio_set(port, bit, pin, v); \
140 stm_moder_set(port, bit, STM_MODER_OUTPUT);\
143 #define ao_gpio_set_mode(port,bit,mode) do { \
144 if (mode == AO_EXTI_MODE_PULL_UP) \
145 stm_pupdr_set(port, bit, STM_PUPDR_PULL_UP); \
146 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
147 stm_pupdr_set(port, bit, STM_PUPDR_PULL_DOWN); \
149 stm_pupdr_set(port, bit, STM_PUPDR_NONE); \
152 #define ao_enable_input(port,bit,mode) do { \
153 ao_enable_port(port); \
154 stm_moder_set(port, bit, STM_MODER_INPUT); \
155 ao_gpio_set_mode(port, bit, mode); \
158 #define ao_enable_cs(port,bit) do { \
159 stm_gpio_set((port), bit, 1); \
160 stm_moder_set((port), bit, STM_MODER_OUTPUT); \
163 #define ao_spi_init_cs(port, mask) do { \
164 ao_enable_port(port); \
165 if ((mask) & 0x0001) ao_enable_cs(port, 0); \
166 if ((mask) & 0x0002) ao_enable_cs(port, 1); \
167 if ((mask) & 0x0004) ao_enable_cs(port, 2); \
168 if ((mask) & 0x0008) ao_enable_cs(port, 3); \
169 if ((mask) & 0x0010) ao_enable_cs(port, 4); \
170 if ((mask) & 0x0020) ao_enable_cs(port, 5); \
171 if ((mask) & 0x0040) ao_enable_cs(port, 6); \
172 if ((mask) & 0x0080) ao_enable_cs(port, 7); \
173 if ((mask) & 0x0100) ao_enable_cs(port, 8); \
174 if ((mask) & 0x0200) ao_enable_cs(port, 9); \
175 if ((mask) & 0x0400) ao_enable_cs(port, 10);\
176 if ((mask) & 0x0800) ao_enable_cs(port, 11);\
177 if ((mask) & 0x1000) ao_enable_cs(port, 12);\
178 if ((mask) & 0x2000) ao_enable_cs(port, 13);\
179 if ((mask) & 0x4000) ao_enable_cs(port, 14);\
180 if ((mask) & 0x8000) ao_enable_cs(port, 15);\
186 extern uint8_t ao_dma_done[STM_NUM_DMA];
189 ao_dma_set_transfer(uint8_t index,
190 volatile void *peripheral,
196 ao_dma_set_isr(uint8_t index, void (*isr)(int index));
199 ao_dma_start(uint8_t index);
202 ao_dma_done_transfer(uint8_t index);
205 ao_dma_abort(uint8_t index);
208 ao_dma_alloc(uint8_t index);
216 ao_i2c_get(uint8_t i2c_index);
219 ao_i2c_start(uint8_t i2c_index, uint16_t address);
222 ao_i2c_put(uint8_t i2c_index);
225 ao_i2c_send(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
228 ao_i2c_recv(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
233 /* ao_serial_stm.c */
234 struct ao_stm_usart {
235 struct ao_fifo rx_fifo;
236 struct ao_fifo tx_fifo;
237 struct stm_usart *reg;
242 extern struct ao_stm_usart ao_stm_usart1;
246 extern struct ao_stm_usart ao_stm_usart2;
250 extern struct ao_stm_usart ao_stm_usart3;
253 #define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
255 static inline uint32_t
256 ao_arch_irqsave(void) {
258 asm("mrs %0,primask" : "=&r" (primask));
259 ao_arch_block_interrupts();
264 ao_arch_irqrestore(uint32_t primask) {
265 asm("msr primask,%0" : : "r" (primask));
269 ao_arch_memory_barrier() {
270 asm volatile("" ::: "memory");
275 ao_arch_init_stack(struct ao_task *task, void *start)
277 uint32_t *sp = (uint32_t *) (task->stack + AO_STACK_SIZE);
278 uint32_t a = (uint32_t) start;
281 /* Return address (goes into LR) */
284 /* Clear register values r0-r12 */
292 /* PRIMASK with interrupts enabled */
298 static inline void ao_arch_save_regs(void) {
299 /* Save general registers */
300 asm("push {r0-r12,lr}\n");
307 asm("mrs r0,primask");
311 static inline void ao_arch_save_stack(void) {
313 asm("mov %0,sp" : "=&r" (sp) );
314 ao_cur_task->sp = (sp);
315 if ((uint8_t *) sp < &ao_cur_task->stack[0])
316 ao_panic (AO_PANIC_STACK);
319 static inline void ao_arch_restore_stack(void) {
321 sp = (uint32_t) ao_cur_task->sp;
324 asm("mov sp, %0" : : "r" (sp) );
326 /* Restore PRIMASK */
328 asm("msr primask,r0");
334 /* Restore general registers */
335 asm("pop {r0-r12,lr}\n");
337 /* Return to calling function */
341 #define HAS_ARCH_START_SCHEDULER 1
343 static inline void ao_arch_start_scheduler(void) {
347 asm("mrs %0,msp" : "=&r" (sp));
348 asm("msr psp,%0" : : "r" (sp));
349 asm("mrs %0,control" : "=&r" (control));
351 asm("msr control,%0" : : "r" (control));
354 #define ao_arch_isr_stack()
358 #define ao_arch_wait_interrupt() do { \
359 asm(".global ao_idle_loc\n\twfi\nao_idle_loc:"); \
360 ao_arch_release_interrupts(); \
361 ao_arch_block_interrupts(); \
364 #define ao_arch_critical(b) do { \
365 ao_arch_block_interrupts(); \
366 do { b } while (0); \
367 ao_arch_release_interrupts(); \
370 #endif /* _AO_ARCH_FUNCS_H_ */