2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #ifndef _AO_ARCH_FUNCS_H_
20 #define _AO_ARCH_FUNCS_H_
25 /* PCLK is set to 16MHz (HCLK 32MHz, APB prescaler 2) */
27 #define AO_SPI_SPEED_8MHz STM_SPI_CR1_BR_PCLK_2
28 #define AO_SPI_SPEED_4MHz STM_SPI_CR1_BR_PCLK_4
29 #define AO_SPI_SPEED_2MHz STM_SPI_CR1_BR_PCLK_8
30 #define AO_SPI_SPEED_1MHz STM_SPI_CR1_BR_PCLK_16
31 #define AO_SPI_SPEED_500kHz STM_SPI_CR1_BR_PCLK_32
32 #define AO_SPI_SPEED_250kHz STM_SPI_CR1_BR_PCLK_64
33 #define AO_SPI_SPEED_125kHz STM_SPI_CR1_BR_PCLK_128
34 #define AO_SPI_SPEED_62500Hz STM_SPI_CR1_BR_PCLK_256
36 #define AO_SPI_SPEED_FAST AO_SPI_SPEED_8MHz
38 /* Companion bus wants something no faster than 200kHz */
40 #define AO_SPI_SPEED_200kHz AO_SPI_SPEED_125kHz
42 #define AO_SPI_CONFIG_1 0x00
43 #define AO_SPI_1_CONFIG_PA5_PA6_PA7 AO_SPI_CONFIG_1
44 #define AO_SPI_2_CONFIG_PB13_PB14_PB15 AO_SPI_CONFIG_1
46 #define AO_SPI_CONFIG_2 0x04
47 #define AO_SPI_1_CONFIG_PB3_PB4_PB5 AO_SPI_CONFIG_2
48 #define AO_SPI_2_CONFIG_PD1_PD3_PD4 AO_SPI_CONFIG_2
50 #define AO_SPI_CONFIG_3 0x08
51 #define AO_SPI_1_CONFIG_PE13_PE14_PE15 AO_SPI_CONFIG_3
53 #define AO_SPI_CONFIG_NONE 0x0c
55 #define AO_SPI_INDEX_MASK 0x01
56 #define AO_SPI_CONFIG_MASK 0x0c
58 #define AO_SPI_1_PA5_PA6_PA7 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA5_PA6_PA7)
59 #define AO_SPI_1_PB3_PB4_PB5 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PB3_PB4_PB5)
60 #define AO_SPI_1_PE13_PE14_PE15 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PE13_PE14_PE15)
62 #define AO_SPI_2_PB13_PB14_PB15 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PB13_PB14_PB15)
63 #define AO_SPI_2_PD1_PD3_PD4 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PD1_PD3_PD4)
65 #define AO_SPI_INDEX(id) ((id) & AO_SPI_INDEX_MASK)
66 #define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
69 ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id);
72 ao_spi_get(uint8_t spi_index, uint32_t speed);
75 ao_spi_put(uint8_t spi_index);
78 ao_spi_send(const void *block, uint16_t len, uint8_t spi_index);
81 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
84 ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index);
87 ao_spi_start_bytes(uint8_t spi_index);
90 ao_spi_stop_bytes(uint8_t spi_index);
93 ao_spi_send_byte(uint8_t byte, uint8_t spi_index)
95 struct stm_spi *stm_spi;
97 switch (AO_SPI_INDEX(spi_index)) {
106 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
109 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
114 static inline uint8_t
115 ao_spi_recv_byte(uint8_t spi_index)
117 struct stm_spi *stm_spi;
119 switch (AO_SPI_INDEX(spi_index)) {
128 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
131 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
137 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
140 ao_spi_duplex(const void *out, void *in, uint16_t len, uint8_t spi_index);
142 extern uint16_t ao_spi_speed[STM_NUM_SPI];
147 #define ao_spi_set_cs(reg,mask) ((reg)->bsrr = ((uint32_t) (mask)) << 16)
148 #define ao_spi_clr_cs(reg,mask) ((reg)->bsrr = (mask))
150 #define ao_spi_get_mask(reg,mask,bus, speed) do { \
151 ao_spi_get(bus, speed); \
152 ao_spi_set_cs(reg,mask); \
155 static inline uint8_t
156 ao_spi_try_get_mask(struct stm_gpio *reg, uint16_t mask, uint8_t bus, uint32_t speed, uint8_t task_id)
158 if (!ao_spi_try_get(bus, speed, task_id))
160 ao_spi_set_cs(reg, mask);
164 #define ao_spi_put_mask(reg,mask,bus) do { \
165 ao_spi_clr_cs(reg,mask); \
169 #define ao_spi_get_bit(reg,bit,pin,bus,speed) ao_spi_get_mask(reg,(1<<bit),bus,speed)
170 #define ao_spi_put_bit(reg,bit,pin,bus) ao_spi_put_mask(reg,(1<<bit),bus)
172 #define ao_enable_port(port) do { \
173 if ((port) == &stm_gpioa) \
174 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN); \
175 else if ((port) == &stm_gpiob) \
176 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN); \
177 else if ((port) == &stm_gpioc) \
178 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOCEN); \
179 else if ((port) == &stm_gpiod) \
180 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIODEN); \
181 else if ((port) == &stm_gpioe) \
182 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOEEN); \
185 #define ao_disable_port(port) do { \
186 if ((port) == &stm_gpioa) \
187 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOAEN); \
188 else if ((port) == &stm_gpiob) \
189 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOBEN); \
190 else if ((port) == &stm_gpioc) \
191 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOCEN); \
192 else if ((port) == &stm_gpiod) \
193 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIODEN); \
194 else if ((port) == &stm_gpioe) \
195 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOEEN); \
199 #define ao_gpio_set(port, bit, pin, v) stm_gpio_set(port, bit, v)
201 #define ao_gpio_get(port, bit, pin) stm_gpio_get(port, bit)
203 #define ao_gpio_set_bits(port, bits) stm_gpio_set_bits(port, bits)
205 #define ao_gpio_set_mask(port, bits, mask) stm_gpio_set_mask(port, bits, mask)
207 #define ao_gpio_clr_bits(port, bits) stm_gpio_clr_bits(port, bits);
209 #define ao_gpio_get_all(port) stm_gpio_get_all(port)
211 #define ao_enable_output(port,bit,pin,v) do { \
212 ao_enable_port(port); \
213 ao_gpio_set(port, bit, pin, v); \
214 stm_moder_set(port, bit, STM_MODER_OUTPUT);\
217 #define ao_enable_output_mask(port,bits,mask) do { \
218 ao_enable_port(port); \
219 ao_gpio_set_mask(port, bits, mask); \
220 ao_set_output_mask(port, mask); \
223 #define AO_OUTPUT_PUSH_PULL STM_OTYPER_PUSH_PULL
224 #define AO_OUTPUT_OPEN_DRAIN STM_OTYPER_OPEN_DRAIN
226 #define ao_gpio_set_output_mode(port,bit,pin,mode) \
227 stm_otyper_set(port, pin, mode)
229 #define ao_gpio_set_mode(port,bit,mode) do { \
230 if (mode == AO_EXTI_MODE_PULL_UP) \
231 stm_pupdr_set(port, bit, STM_PUPDR_PULL_UP); \
232 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
233 stm_pupdr_set(port, bit, STM_PUPDR_PULL_DOWN); \
235 stm_pupdr_set(port, bit, STM_PUPDR_NONE); \
238 #define ao_gpio_set_mode_mask(port,mask,mode) do { \
239 if (mode == AO_EXTI_MODE_PULL_UP) \
240 stm_pupdr_set_mask(port, mask, STM_PUPDR_PULL_UP); \
241 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
242 stm_pupdr_set_mask(port, mask, STM_PUPDR_PULL_DOWN); \
244 stm_pupdr_set_mask(port, mask, STM_PUPDR_NONE); \
247 #define ao_set_input(port, bit) do { \
248 stm_moder_set(port, bit, STM_MODER_INPUT); \
251 #define ao_set_output(port, bit, pin, v) do { \
252 ao_gpio_set(port, bit, pin, v); \
253 stm_moder_set(port, bit, STM_MODER_OUTPUT); \
256 #define ao_set_output_mask(port, mask) do { \
257 stm_moder_set_mask(port, mask, STM_MODER_OUTPUT); \
260 #define ao_set_input_mask(port, mask) do { \
261 stm_moder_set_mask(port, mask, STM_MODER_INPUT); \
264 #define ao_enable_input(port,bit,mode) do { \
265 ao_enable_port(port); \
266 ao_set_input(port, bit); \
267 ao_gpio_set_mode(port, bit, mode); \
270 #define ao_enable_input_mask(port,mask,mode) do { \
271 ao_enable_port(port); \
272 ao_gpio_set_mode_mask(port, mask, mode); \
273 ao_set_input_mask(port, mask); \
276 #define _ao_enable_cs(port, bit) do { \
277 stm_gpio_set((port), bit, 1); \
278 stm_moder_set((port), bit, STM_MODER_OUTPUT); \
281 #define ao_enable_cs(port,bit) do { \
282 ao_enable_port(port); \
283 _ao_enable_cs(port, bit); \
286 #define ao_spi_init_cs(port, mask) do { \
287 ao_enable_port(port); \
288 if ((mask) & 0x0001) _ao_enable_cs(port, 0); \
289 if ((mask) & 0x0002) _ao_enable_cs(port, 1); \
290 if ((mask) & 0x0004) _ao_enable_cs(port, 2); \
291 if ((mask) & 0x0008) _ao_enable_cs(port, 3); \
292 if ((mask) & 0x0010) _ao_enable_cs(port, 4); \
293 if ((mask) & 0x0020) _ao_enable_cs(port, 5); \
294 if ((mask) & 0x0040) _ao_enable_cs(port, 6); \
295 if ((mask) & 0x0080) _ao_enable_cs(port, 7); \
296 if ((mask) & 0x0100) _ao_enable_cs(port, 8); \
297 if ((mask) & 0x0200) _ao_enable_cs(port, 9); \
298 if ((mask) & 0x0400) _ao_enable_cs(port, 10);\
299 if ((mask) & 0x0800) _ao_enable_cs(port, 11);\
300 if ((mask) & 0x1000) _ao_enable_cs(port, 12);\
301 if ((mask) & 0x2000) _ao_enable_cs(port, 13);\
302 if ((mask) & 0x4000) _ao_enable_cs(port, 14);\
303 if ((mask) & 0x8000) _ao_enable_cs(port, 15);\
309 extern uint8_t ao_dma_done[STM_NUM_DMA];
312 ao_dma_set_transfer(uint8_t index,
313 volatile void *peripheral,
319 ao_dma_set_isr(uint8_t index, void (*isr)(int index));
322 ao_dma_start(uint8_t index);
325 ao_dma_done_transfer(uint8_t index);
328 ao_dma_alloc(uint8_t index);
336 ao_i2c_get(uint8_t i2c_index);
339 ao_i2c_start(uint8_t i2c_index, uint16_t address);
342 ao_i2c_put(uint8_t i2c_index);
345 ao_i2c_send(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
348 ao_i2c_recv(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
353 #if USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_SW_FLOW || USE_SERIAL_3_SW_FLOW
354 #define HAS_SERIAL_SW_FLOW 1
356 #define HAS_SERIAL_SW_FLOW 0
359 #if USE_SERIAL_1_FLOW && !USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_FLOW && !USE_SERIAL_2_SW_FLOW || USE_SERIAL_3_FLOW && !USE_SERIAL_3_SW_FLOW
360 #define HAS_SERIAL_HW_FLOW 1
362 #define HAS_SERIAL_HW_FLOW 0
365 /* ao_serial_stm.c */
366 struct ao_stm_usart {
367 struct ao_fifo rx_fifo;
368 struct ao_fifo tx_fifo;
369 struct stm_usart *reg;
372 #if HAS_SERIAL_SW_FLOW
373 /* RTS - 0 if we have FIFO space, 1 if not
374 * CTS - 0 if we can send, 0 if not
376 struct stm_gpio *gpio_rts;
377 struct stm_gpio *gpio_cts;
385 extern struct ao_stm_usart ao_stm_usart1;
389 extern struct ao_stm_usart ao_stm_usart2;
393 extern struct ao_stm_usart ao_stm_usart3;
396 #define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
398 typedef uint32_t ao_arch_irq_t;
401 ao_arch_block_interrupts(void) {
402 #ifdef AO_NONMASK_INTERRUPTS
403 asm("msr basepri,%0" : : "r" (AO_STM_NVIC_BASEPRI_MASK));
410 ao_arch_release_interrupts(void) {
411 #ifdef AO_NONMASK_INTERRUPTS
412 asm("msr basepri,%0" : : "r" (0x0));
418 static inline uint32_t
419 ao_arch_irqsave(void) {
421 #ifdef AO_NONMASK_INTERRUPTS
422 asm("mrs %0,basepri" : "=r" (val));
424 asm("mrs %0,primask" : "=r" (val));
426 ao_arch_block_interrupts();
431 ao_arch_irqrestore(uint32_t basepri) {
432 #ifdef AO_NONMASK_INTERRUPTS
433 asm("msr basepri,%0" : : "r" (basepri));
435 asm("msr primask,%0" : : "r" (basepri));
440 ao_arch_memory_barrier() {
441 asm volatile("" ::: "memory");
445 ao_arch_irq_check(void) {
446 #ifdef AO_NONMASK_INTERRUPTS
448 asm("mrs %0,basepri" : "=r" (basepri));
450 ao_panic(AO_PANIC_IRQ);
453 asm("mrs %0,primask" : "=r" (primask));
454 if ((primask & 1) == 0)
455 ao_panic(AO_PANIC_IRQ);
461 ao_arch_init_stack(struct ao_task *task, void *start)
463 uint32_t *sp = (uint32_t *) ((void*) task->stack + AO_STACK_SIZE);
464 uint32_t a = (uint32_t) start;
467 /* Return address (goes into LR) */
470 /* Clear register values r0-r12 */
478 /* BASEPRI with interrupts enabled */
484 static inline void ao_arch_save_regs(void) {
485 /* Save general registers */
486 asm("push {r0-r12,lr}\n");
492 #ifdef AO_NONMASK_INTERRUPTS
494 asm("mrs r0,basepri");
497 asm("mrs r0,primask");
502 static inline void ao_arch_save_stack(void) {
504 asm("mov %0,sp" : "=&r" (sp) );
505 ao_cur_task->sp = (sp);
508 static inline void ao_arch_restore_stack(void) {
510 asm("mov sp, %0" : : "r" (ao_cur_task->sp) );
512 #ifdef AO_NONMASK_INTERRUPTS
513 /* Restore BASEPRI */
515 asm("msr basepri,r0");
517 /* Restore PRIMASK */
519 asm("msr primask,r0");
524 asm("msr apsr_nczvq,r0");
526 /* Restore general registers */
527 asm("pop {r0-r12,lr}\n");
529 /* Return to calling function */
533 #ifndef HAS_SAMPLE_PROFILE
534 #define HAS_SAMPLE_PROFILE 0
538 #define HAS_ARCH_VALIDATE_CUR_STACK 1
541 ao_validate_cur_stack(void)
545 asm("mrs %0,psp" : "=&r" (psp));
547 psp <= ao_cur_task->stack &&
548 psp >= ao_cur_task->stack - 256)
549 ao_panic(AO_PANIC_STACK);
553 #if !HAS_SAMPLE_PROFILE
554 #define HAS_ARCH_START_SCHEDULER 1
556 static inline void ao_arch_start_scheduler(void) {
560 asm("mrs %0,msp" : "=&r" (sp));
561 asm("msr psp,%0" : : "r" (sp));
562 asm("mrs %0,control" : "=r" (control));
564 asm("msr control,%0" : : "r" (control));
569 #define ao_arch_isr_stack()
574 ao_arch_wait_interrupt(void) {
575 #ifdef AO_NONMASK_INTERRUPTS
577 "dsb\n" /* Serialize data */
578 "isb\n" /* Serialize instructions */
579 "cpsid i\n" /* Block all interrupts */
580 "msr basepri,%0\n" /* Allow all interrupts through basepri */
581 "wfi\n" /* Wait for an interrupt */
582 "cpsie i\n" /* Allow all interrupts */
583 "msr basepri,%1\n" /* Block interrupts through basepri */
584 : : "r" (0), "r" (AO_STM_NVIC_BASEPRI_MASK));
587 ao_arch_release_interrupts();
588 ao_arch_block_interrupts();
592 #define ao_arch_critical(b) do { \
593 uint32_t __mask = ao_arch_irqsave(); \
594 do { b } while (0); \
595 ao_arch_irqrestore(__mask); \
598 #endif /* _AO_ARCH_FUNCS_H_ */