2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
18 #ifndef _AO_ARCH_FUNCS_H_
19 #define _AO_ARCH_FUNCS_H_
24 /* PCLK is set to 16MHz (HCLK 32MHz, APB prescaler 2) */
26 #define AO_SPI_SPEED_8MHz STM_SPI_CR1_BR_PCLK_2
27 #define AO_SPI_SPEED_4MHz STM_SPI_CR1_BR_PCLK_4
28 #define AO_SPI_SPEED_2MHz STM_SPI_CR1_BR_PCLK_8
29 #define AO_SPI_SPEED_1MHz STM_SPI_CR1_BR_PCLK_16
30 #define AO_SPI_SPEED_500kHz STM_SPI_CR1_BR_PCLK_32
31 #define AO_SPI_SPEED_250kHz STM_SPI_CR1_BR_PCLK_64
32 #define AO_SPI_SPEED_125kHz STM_SPI_CR1_BR_PCLK_128
33 #define AO_SPI_SPEED_62500Hz STM_SPI_CR1_BR_PCLK_256
35 #define AO_SPI_SPEED_FAST AO_SPI_SPEED_8MHz
37 /* Companion bus wants something no faster than 200kHz */
39 #define AO_SPI_SPEED_200kHz AO_SPI_SPEED_125kHz
41 #define AO_SPI_CONFIG_1 0x00
42 #define AO_SPI_1_CONFIG_PA5_PA6_PA7 AO_SPI_CONFIG_1
43 #define AO_SPI_2_CONFIG_PB13_PB14_PB15 AO_SPI_CONFIG_1
45 #define AO_SPI_CONFIG_2 0x04
46 #define AO_SPI_1_CONFIG_PB3_PB4_PB5 AO_SPI_CONFIG_2
47 #define AO_SPI_2_CONFIG_PD1_PD3_PD4 AO_SPI_CONFIG_2
49 #define AO_SPI_CONFIG_3 0x08
50 #define AO_SPI_1_CONFIG_PE13_PE14_PE15 AO_SPI_CONFIG_3
52 #define AO_SPI_CONFIG_NONE 0x0c
54 #define AO_SPI_INDEX_MASK 0x01
55 #define AO_SPI_CONFIG_MASK 0x0c
57 #define AO_SPI_1_PA5_PA6_PA7 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA5_PA6_PA7)
58 #define AO_SPI_1_PB3_PB4_PB5 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PB3_PB4_PB5)
59 #define AO_SPI_1_PE13_PE14_PE15 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PE13_PE14_PE15)
61 #define AO_SPI_2_PB13_PB14_PB15 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PB13_PB14_PB15)
62 #define AO_SPI_2_PD1_PD3_PD4 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PD1_PD3_PD4)
64 #define AO_SPI_INDEX(id) ((id) & AO_SPI_INDEX_MASK)
65 #define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
68 ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id);
71 ao_spi_get(uint8_t spi_index, uint32_t speed);
74 ao_spi_put(uint8_t spi_index);
77 ao_spi_send(const void *block, uint16_t len, uint8_t spi_index);
80 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
83 ao_spi_send_sync(void *block, uint16_t len, uint8_t spi_index);
86 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
89 ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index);
91 extern uint16_t ao_spi_speed[STM_NUM_SPI];
96 #define ao_spi_set_cs(reg,mask) ((reg)->bsrr = ((uint32_t) (mask)) << 16)
97 #define ao_spi_clr_cs(reg,mask) ((reg)->bsrr = (mask))
99 #define ao_spi_get_mask(reg,mask,bus, speed) do { \
100 ao_spi_get(bus, speed); \
101 ao_spi_set_cs(reg,mask); \
104 static inline uint8_t
105 ao_spi_try_get_mask(struct stm_gpio *reg, uint16_t mask, uint8_t bus, uint32_t speed, uint8_t task_id)
107 if (!ao_spi_try_get(bus, speed, task_id))
109 ao_spi_set_cs(reg, mask);
113 #define ao_spi_put_mask(reg,mask,bus) do { \
114 ao_spi_clr_cs(reg,mask); \
118 #define ao_spi_get_bit(reg,bit,pin,bus,speed) ao_spi_get_mask(reg,(1<<bit),bus,speed)
119 #define ao_spi_put_bit(reg,bit,pin,bus) ao_spi_put_mask(reg,(1<<bit),bus)
121 #define ao_enable_port(port) do { \
122 if ((port) == &stm_gpioa) \
123 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN); \
124 else if ((port) == &stm_gpiob) \
125 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN); \
126 else if ((port) == &stm_gpioc) \
127 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOCEN); \
128 else if ((port) == &stm_gpiod) \
129 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIODEN); \
130 else if ((port) == &stm_gpioe) \
131 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOEEN); \
134 #define ao_disable_port(port) do { \
135 if ((port) == &stm_gpioa) \
136 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOAEN); \
137 else if ((port) == &stm_gpiob) \
138 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOBEN); \
139 else if ((port) == &stm_gpioc) \
140 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOCEN); \
141 else if ((port) == &stm_gpiod) \
142 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIODEN); \
143 else if ((port) == &stm_gpioe) \
144 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOEEN); \
148 #define ao_gpio_set(port, bit, pin, v) stm_gpio_set(port, bit, v)
150 #define ao_gpio_get(port, bit, pin) stm_gpio_get(port, bit)
152 #define ao_enable_output(port,bit,pin,v) do { \
153 ao_enable_port(port); \
154 ao_gpio_set(port, bit, pin, v); \
155 stm_moder_set(port, bit, STM_MODER_OUTPUT);\
158 #define ao_gpio_set_mode(port,bit,mode) do { \
159 if (mode == AO_EXTI_MODE_PULL_UP) \
160 stm_pupdr_set(port, bit, STM_PUPDR_PULL_UP); \
161 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
162 stm_pupdr_set(port, bit, STM_PUPDR_PULL_DOWN); \
164 stm_pupdr_set(port, bit, STM_PUPDR_NONE); \
167 #define ao_enable_input(port,bit,mode) do { \
168 ao_enable_port(port); \
169 stm_moder_set(port, bit, STM_MODER_INPUT); \
170 ao_gpio_set_mode(port, bit, mode); \
173 #define ao_enable_cs(port,bit) do { \
174 stm_gpio_set((port), bit, 1); \
175 stm_moder_set((port), bit, STM_MODER_OUTPUT); \
178 #define ao_spi_init_cs(port, mask) do { \
179 ao_enable_port(port); \
180 if ((mask) & 0x0001) ao_enable_cs(port, 0); \
181 if ((mask) & 0x0002) ao_enable_cs(port, 1); \
182 if ((mask) & 0x0004) ao_enable_cs(port, 2); \
183 if ((mask) & 0x0008) ao_enable_cs(port, 3); \
184 if ((mask) & 0x0010) ao_enable_cs(port, 4); \
185 if ((mask) & 0x0020) ao_enable_cs(port, 5); \
186 if ((mask) & 0x0040) ao_enable_cs(port, 6); \
187 if ((mask) & 0x0080) ao_enable_cs(port, 7); \
188 if ((mask) & 0x0100) ao_enable_cs(port, 8); \
189 if ((mask) & 0x0200) ao_enable_cs(port, 9); \
190 if ((mask) & 0x0400) ao_enable_cs(port, 10);\
191 if ((mask) & 0x0800) ao_enable_cs(port, 11);\
192 if ((mask) & 0x1000) ao_enable_cs(port, 12);\
193 if ((mask) & 0x2000) ao_enable_cs(port, 13);\
194 if ((mask) & 0x4000) ao_enable_cs(port, 14);\
195 if ((mask) & 0x8000) ao_enable_cs(port, 15);\
201 extern uint8_t ao_dma_done[STM_NUM_DMA];
204 ao_dma_set_transfer(uint8_t index,
205 volatile void *peripheral,
211 ao_dma_set_isr(uint8_t index, void (*isr)(int index));
214 ao_dma_start(uint8_t index);
217 ao_dma_done_transfer(uint8_t index);
220 ao_dma_abort(uint8_t index);
223 ao_dma_alloc(uint8_t index);
231 ao_i2c_get(uint8_t i2c_index);
234 ao_i2c_start(uint8_t i2c_index, uint16_t address);
237 ao_i2c_put(uint8_t i2c_index);
240 ao_i2c_send(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
243 ao_i2c_recv(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
248 /* ao_serial_stm.c */
249 struct ao_stm_usart {
250 struct ao_fifo rx_fifo;
251 struct ao_fifo tx_fifo;
252 struct stm_usart *reg;
257 extern struct ao_stm_usart ao_stm_usart1;
261 extern struct ao_stm_usart ao_stm_usart2;
265 extern struct ao_stm_usart ao_stm_usart3;
268 #define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
270 typedef uint32_t ao_arch_irq_t;
272 static inline uint32_t
273 ao_arch_irqsave(void) {
275 asm("mrs %0,primask" : "=&r" (primask));
276 ao_arch_block_interrupts();
281 ao_arch_irqrestore(uint32_t primask) {
282 asm("msr primask,%0" : : "r" (primask));
286 ao_arch_memory_barrier() {
287 asm volatile("" ::: "memory");
292 ao_arch_init_stack(struct ao_task *task, void *start)
294 uint32_t *sp = (uint32_t *) (task->stack + AO_STACK_SIZE);
295 uint32_t a = (uint32_t) start;
298 /* Return address (goes into LR) */
301 /* Clear register values r0-r12 */
309 /* PRIMASK with interrupts enabled */
315 static inline void ao_arch_save_regs(void) {
316 /* Save general registers */
317 asm("push {r0-r12,lr}\n");
324 asm("mrs r0,primask");
328 static inline void ao_arch_save_stack(void) {
330 asm("mov %0,sp" : "=&r" (sp) );
331 ao_cur_task->sp = (sp);
332 if ((uint8_t *) sp < &ao_cur_task->stack[0])
333 ao_panic (AO_PANIC_STACK);
336 static inline void ao_arch_restore_stack(void) {
338 sp = (uint32_t) ao_cur_task->sp;
341 asm("mov sp, %0" : : "r" (sp) );
343 /* Restore PRIMASK */
345 asm("msr primask,r0");
349 asm("msr apsr_nczvq,r0");
351 /* Restore general registers */
352 asm("pop {r0-r12,lr}\n");
354 /* Return to calling function */
358 #ifndef HAS_SAMPLE_PROFILE
359 #define HAS_SAMPLE_PROFILE 0
362 #if !HAS_SAMPLE_PROFILE
363 #define HAS_ARCH_START_SCHEDULER 1
365 static inline void ao_arch_start_scheduler(void) {
369 asm("mrs %0,msp" : "=&r" (sp));
370 asm("msr psp,%0" : : "r" (sp));
371 asm("mrs %0,control" : "=&r" (control));
373 asm("msr control,%0" : : "r" (control));
378 #define ao_arch_isr_stack()
382 #define ao_arch_wait_interrupt() do { \
384 ao_arch_release_interrupts(); \
385 asm(".global ao_idle_loc\nao_idle_loc:"); \
386 ao_arch_block_interrupts(); \
389 #define ao_arch_critical(b) do { \
390 uint32_t __mask = ao_arch_irqsave(); \
391 do { b } while (0); \
392 ao_arch_irqrestore(__mask); \
395 #endif /* _AO_ARCH_FUNCS_H_ */