2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
18 #ifndef _AO_ARCH_FUNCS_H_
19 #define _AO_ARCH_FUNCS_H_
24 /* PCLK is set to 16MHz (HCLK 32MHz, APB prescaler 2) */
26 #define AO_SPI_SPEED_8MHz STM_SPI_CR1_BR_PCLK_2
27 #define AO_SPI_SPEED_4MHz STM_SPI_CR1_BR_PCLK_4
28 #define AO_SPI_SPEED_2MHz STM_SPI_CR1_BR_PCLK_8
29 #define AO_SPI_SPEED_1MHz STM_SPI_CR1_BR_PCLK_16
30 #define AO_SPI_SPEED_500kHz STM_SPI_CR1_BR_PCLK_32
31 #define AO_SPI_SPEED_250kHz STM_SPI_CR1_BR_PCLK_64
32 #define AO_SPI_SPEED_125kHz STM_SPI_CR1_BR_PCLK_128
33 #define AO_SPI_SPEED_62500Hz STM_SPI_CR1_BR_PCLK_256
35 #define AO_SPI_SPEED_FAST AO_SPI_SPEED_8MHz
37 /* Companion bus wants something no faster than 200kHz */
39 #define AO_SPI_SPEED_200kHz AO_SPI_SPEED_125kHz
41 #define AO_SPI_CONFIG_1 0x00
42 #define AO_SPI_1_CONFIG_PA5_PA6_PA7 AO_SPI_CONFIG_1
43 #define AO_SPI_2_CONFIG_PB13_PB14_PB15 AO_SPI_CONFIG_1
45 #define AO_SPI_CONFIG_2 0x04
46 #define AO_SPI_1_CONFIG_PB3_PB4_PB5 AO_SPI_CONFIG_2
47 #define AO_SPI_2_CONFIG_PD1_PD3_PD4 AO_SPI_CONFIG_2
49 #define AO_SPI_CONFIG_3 0x08
50 #define AO_SPI_1_CONFIG_PE13_PE14_PE15 AO_SPI_CONFIG_3
52 #define AO_SPI_CONFIG_NONE 0x0c
54 #define AO_SPI_INDEX_MASK 0x01
55 #define AO_SPI_CONFIG_MASK 0x0c
57 #define AO_SPI_1_PA5_PA6_PA7 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA5_PA6_PA7)
58 #define AO_SPI_1_PB3_PB4_PB5 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PB3_PB4_PB5)
59 #define AO_SPI_1_PE13_PE14_PE15 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PE13_PE14_PE15)
61 #define AO_SPI_2_PB13_PB14_PB15 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PB13_PB14_PB15)
62 #define AO_SPI_2_PD1_PD3_PD4 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PD1_PD3_PD4)
64 #define AO_SPI_INDEX(id) ((id) & AO_SPI_INDEX_MASK)
65 #define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
68 ao_spi_get(uint8_t spi_index, uint32_t speed);
71 ao_spi_put(uint8_t spi_index);
74 ao_spi_send(void *block, uint16_t len, uint8_t spi_index);
77 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
80 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
83 ao_spi_duplex(void *out, void *in, uint16_t len, uint8_t spi_index);
85 extern uint16_t ao_spi_speed[STM_NUM_SPI];
90 #define ao_spi_get_mask(reg,mask,bus, speed) do { \
91 ao_spi_get(bus, speed); \
92 (reg)->bsrr = ((uint32_t) mask) << 16; \
95 #define ao_spi_put_mask(reg,mask,bus) do { \
100 #define ao_spi_get_bit(reg,bit,pin,bus,speed) ao_spi_get_mask(reg,(1<<bit),bus,speed)
101 #define ao_spi_put_bit(reg,bit,pin,bus) ao_spi_put_mask(reg,(1<<bit),bus)
103 #define ao_enable_port(port) do { \
104 if ((port) == &stm_gpioa) \
105 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN); \
106 else if ((port) == &stm_gpiob) \
107 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN); \
108 else if ((port) == &stm_gpioc) \
109 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOCEN); \
110 else if ((port) == &stm_gpiod) \
111 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIODEN); \
112 else if ((port) == &stm_gpioe) \
113 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOEEN); \
116 #define ao_disable_port(port) do { \
117 if ((port) == &stm_gpioa) \
118 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOAEN); \
119 else if ((port) == &stm_gpiob) \
120 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOBEN); \
121 else if ((port) == &stm_gpioc) \
122 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOCEN); \
123 else if ((port) == &stm_gpiod) \
124 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIODEN); \
125 else if ((port) == &stm_gpioe) \
126 stm_rcc.ahbenr &= ~(1 << STM_RCC_AHBENR_GPIOEEN); \
130 #define ao_gpio_set(port, bit, pin, v) stm_gpio_set(port, bit, v)
132 #define ao_gpio_get(port, bit, pin) stm_gpio_get(port, bit)
134 #define ao_enable_output(port,bit,pin,v) do { \
135 ao_enable_port(port); \
136 ao_gpio_set(port, bit, pin, v); \
137 stm_moder_set(port, bit, STM_MODER_OUTPUT);\
140 #define ao_gpio_set_mode(port,bit,mode) do { \
141 if (mode == AO_EXTI_MODE_PULL_UP) \
142 stm_pupdr_set(port, bit, STM_PUPDR_PULL_UP); \
143 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
144 stm_pupdr_set(port, bit, STM_PUPDR_PULL_DOWN); \
146 stm_pupdr_set(port, bit, STM_PUPDR_NONE); \
149 #define ao_enable_input(port,bit,mode) do { \
150 ao_enable_port(port); \
151 stm_moder_set(port, bit, STM_MODER_INPUT); \
152 ao_gpio_set_mode(port, bit, mode); \
155 #define ao_enable_cs(port,bit) do { \
156 stm_gpio_set((port), bit, 1); \
157 stm_moder_set((port), bit, STM_MODER_OUTPUT); \
160 #define ao_spi_init_cs(port, mask) do { \
161 ao_enable_port(port); \
162 if ((mask) & 0x0001) ao_enable_cs(port, 0); \
163 if ((mask) & 0x0002) ao_enable_cs(port, 1); \
164 if ((mask) & 0x0004) ao_enable_cs(port, 2); \
165 if ((mask) & 0x0008) ao_enable_cs(port, 3); \
166 if ((mask) & 0x0010) ao_enable_cs(port, 4); \
167 if ((mask) & 0x0020) ao_enable_cs(port, 5); \
168 if ((mask) & 0x0040) ao_enable_cs(port, 6); \
169 if ((mask) & 0x0080) ao_enable_cs(port, 7); \
170 if ((mask) & 0x0100) ao_enable_cs(port, 8); \
171 if ((mask) & 0x0200) ao_enable_cs(port, 9); \
172 if ((mask) & 0x0400) ao_enable_cs(port, 10);\
173 if ((mask) & 0x0800) ao_enable_cs(port, 11);\
174 if ((mask) & 0x1000) ao_enable_cs(port, 12);\
175 if ((mask) & 0x2000) ao_enable_cs(port, 13);\
176 if ((mask) & 0x4000) ao_enable_cs(port, 14);\
177 if ((mask) & 0x8000) ao_enable_cs(port, 15);\
183 extern uint8_t ao_dma_done[STM_NUM_DMA];
186 ao_dma_set_transfer(uint8_t index,
187 volatile void *peripheral,
193 ao_dma_set_isr(uint8_t index, void (*isr)(int index));
196 ao_dma_start(uint8_t index);
199 ao_dma_done_transfer(uint8_t index);
202 ao_dma_abort(uint8_t index);
205 ao_dma_alloc(uint8_t index);
213 ao_i2c_get(uint8_t i2c_index);
216 ao_i2c_start(uint8_t i2c_index, uint16_t address);
219 ao_i2c_put(uint8_t i2c_index);
222 ao_i2c_send(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
225 ao_i2c_recv(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
230 /* ao_serial_stm.c */
231 struct ao_stm_usart {
232 struct ao_fifo rx_fifo;
233 struct ao_fifo tx_fifo;
234 struct stm_usart *reg;
239 extern struct ao_stm_usart ao_stm_usart1;
243 extern struct ao_stm_usart ao_stm_usart2;
247 extern struct ao_stm_usart ao_stm_usart3;
250 #define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
252 static inline uint32_t
253 ao_arch_irqsave(void) {
255 asm("mrs %0,primask" : "=&r" (primask));
256 ao_arch_block_interrupts();
261 ao_arch_irqrestore(uint32_t primask) {
262 asm("msr primask,%0" : : "r" (primask));
266 ao_arch_memory_barrier() {
267 asm volatile("" ::: "memory");
272 ao_arch_init_stack(struct ao_task *task, void *start)
274 uint32_t *sp = (uint32_t *) (task->stack + AO_STACK_SIZE);
275 uint32_t a = (uint32_t) start;
278 /* Return address (goes into LR) */
281 /* Clear register values r0-r12 */
289 /* PRIMASK with interrupts enabled */
295 static inline void ao_arch_save_regs(void) {
296 /* Save general registers */
297 asm("push {r0-r12,lr}\n");
304 asm("mrs r0,primask");
308 static inline void ao_arch_save_stack(void) {
310 asm("mov %0,sp" : "=&r" (sp) );
311 ao_cur_task->sp = (sp);
312 if ((uint8_t *) sp < &ao_cur_task->stack[0])
313 ao_panic (AO_PANIC_STACK);
316 static inline void ao_arch_restore_stack(void) {
318 sp = (uint32_t) ao_cur_task->sp;
321 asm("mov sp, %0" : : "r" (sp) );
323 /* Restore PRIMASK */
325 asm("msr primask,r0");
331 /* Restore general registers */
332 asm("pop {r0-r12,lr}\n");
334 /* Return to calling function */
338 #define HAS_ARCH_START_SCHEDULER 1
340 static inline void ao_arch_start_scheduler(void) {
344 asm("mrs %0,msp" : "=&r" (sp));
345 asm("msr psp,%0" : : "r" (sp));
346 asm("mrs %0,control" : "=&r" (control));
348 asm("msr control,%0" : : "r" (control));
351 #define ao_arch_isr_stack()
355 #define ao_arch_wait_interrupt() do { \
356 asm(".global ao_idle_loc\n\twfi\nao_idle_loc:"); \
357 ao_arch_release_interrupts(); \
358 ao_arch_block_interrupts(); \
361 #define ao_arch_critical(b) do { \
362 ao_arch_block_interrupts(); \
363 do { b } while (0); \
364 ao_arch_release_interrupts(); \
367 #endif /* _AO_ARCH_FUNCS_H_ */