2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
19 #ifndef _AO_ARCH_FUNCS_H_
20 #define _AO_ARCH_FUNCS_H_
25 /* PCLK is set to 16MHz (HCLK 32MHz, APB prescaler 2) */
27 //#define AO_SPI_SPEED_8MHz STM_SPI_CR1_BR_PCLK_2 /* too fast to use safely */
28 #define _AO_SPI_SPEED_4MHz STM_SPI_CR1_BR_PCLK_4
29 #define _AO_SPI_SPEED_2MHz STM_SPI_CR1_BR_PCLK_8
30 #define _AO_SPI_SPEED_1MHz STM_SPI_CR1_BR_PCLK_16
31 #define _AO_SPI_SPEED_500kHz STM_SPI_CR1_BR_PCLK_32
32 #define _AO_SPI_SPEED_250kHz STM_SPI_CR1_BR_PCLK_64
33 #define _AO_SPI_SPEED_125kHz STM_SPI_CR1_BR_PCLK_128
34 #define _AO_SPI_SPEED_62500Hz STM_SPI_CR1_BR_PCLK_256
36 static inline uint32_t
37 ao_spi_speed(int index, uint32_t hz)
40 if (hz >= 4000000) return _AO_SPI_SPEED_4MHz;
41 if (hz >= 2000000) return _AO_SPI_SPEED_2MHz;
42 if (hz >= 1000000) return _AO_SPI_SPEED_1MHz;
43 if (hz >= 500000) return _AO_SPI_SPEED_500kHz;
44 if (hz >= 250000) return _AO_SPI_SPEED_250kHz;
45 if (hz >= 125000) return _AO_SPI_SPEED_125kHz;
46 return _AO_SPI_SPEED_62500Hz;
49 #define AO_SPI_CPOL_BIT 4
50 #define AO_SPI_CPHA_BIT 5
52 #define AO_SPI_CONFIG_1 0x00
53 #define AO_SPI_1_CONFIG_PA5_PA6_PA7 AO_SPI_CONFIG_1
54 #define AO_SPI_2_CONFIG_PB13_PB14_PB15 AO_SPI_CONFIG_1
56 #define AO_SPI_CONFIG_2 0x04
57 #define AO_SPI_1_CONFIG_PB3_PB4_PB5 AO_SPI_CONFIG_2
58 #define AO_SPI_2_CONFIG_PD1_PD3_PD4 AO_SPI_CONFIG_2
60 #define AO_SPI_CONFIG_3 0x08
61 #define AO_SPI_1_CONFIG_PE13_PE14_PE15 AO_SPI_CONFIG_3
63 #define AO_SPI_CONFIG_NONE 0x0c
65 #define AO_SPI_INDEX_MASK 0x01
66 #define AO_SPI_CONFIG_MASK 0x0c
68 #define AO_SPI_1_PA5_PA6_PA7 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PA5_PA6_PA7)
69 #define AO_SPI_1_PB3_PB4_PB5 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PB3_PB4_PB5)
70 #define AO_SPI_1_PE13_PE14_PE15 (STM_SPI_INDEX(1) | AO_SPI_1_CONFIG_PE13_PE14_PE15)
72 #define AO_SPI_2_PB13_PB14_PB15 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PB13_PB14_PB15)
73 #define AO_SPI_2_PD1_PD3_PD4 (STM_SPI_INDEX(2) | AO_SPI_2_CONFIG_PD1_PD3_PD4)
75 #define AO_SPI_INDEX(id) ((id) & AO_SPI_INDEX_MASK)
76 #define AO_SPI_CONFIG(id) ((id) & AO_SPI_CONFIG_MASK)
77 #define AO_SPI_PIN_CONFIG(id) ((id) & (AO_SPI_INDEX_MASK | AO_SPI_CONFIG_MASK))
78 #define AO_SPI_CPOL(id) ((uint32_t) (((id) >> AO_SPI_CPOL_BIT) & 1))
79 #define AO_SPI_CPHA(id) ((uint32_t) (((id) >> AO_SPI_CPHA_BIT) & 1))
81 #define AO_SPI_MAKE_MODE(pol,pha) (((pol) << AO_SPI_CPOL_BIT) | ((pha) << AO_SPI_CPHA_BIT))
82 #define AO_SPI_MODE_0 AO_SPI_MAKE_MODE(0,0)
83 #define AO_SPI_MODE_1 AO_SPI_MAKE_MODE(0,1)
84 #define AO_SPI_MODE_2 AO_SPI_MAKE_MODE(1,0)
85 #define AO_SPI_MODE_3 AO_SPI_MAKE_MODE(1,1)
88 ao_spi_try_get(uint8_t spi_index, uint32_t speed, uint8_t task_id);
91 ao_spi_get(uint8_t spi_index, uint32_t speed);
94 ao_spi_put(uint8_t spi_index);
97 ao_spi_put_pins(uint8_t spi_index);
100 ao_spi_send(const void *block, uint16_t len, uint8_t spi_index);
103 ao_spi_send_fixed(uint8_t value, uint16_t len, uint8_t spi_index);
106 ao_spi_send_sync(const void *block, uint16_t len, uint8_t spi_index);
109 ao_spi_start_bytes(uint8_t spi_index);
112 ao_spi_stop_bytes(uint8_t spi_index);
115 ao_spi_send_byte(uint8_t byte, uint8_t spi_index)
117 struct stm_spi *stm_spi;
119 switch (AO_SPI_INDEX(spi_index)) {
128 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
131 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
136 static inline uint8_t
137 ao_spi_recv_byte(uint8_t spi_index)
139 struct stm_spi *stm_spi;
141 switch (AO_SPI_INDEX(spi_index)) {
150 while (!(stm_spi->sr & (1 << STM_SPI_SR_TXE)))
153 while (!(stm_spi->sr & (1 << STM_SPI_SR_RXNE)))
155 return (uint8_t) stm_spi->dr;
159 ao_spi_recv(void *block, uint16_t len, uint8_t spi_index);
162 ao_spi_duplex(const void *out, void *in, uint16_t len, uint8_t spi_index);
167 #define ao_spi_set_cs(reg,mask) ((reg)->bsrr = ((uint32_t) (mask)) << 16)
168 #define ao_spi_clr_cs(reg,mask) ((reg)->bsrr = (mask))
170 #define ao_spi_get_mask(reg,mask,bus, speed) do { \
171 ao_spi_get(bus, speed); \
172 ao_spi_set_cs(reg,mask); \
175 static inline uint8_t
176 ao_spi_try_get_mask(struct stm_gpio *reg, uint16_t mask, uint8_t bus, uint32_t speed, uint8_t task_id)
178 if (!ao_spi_try_get(bus, speed, task_id))
180 ao_spi_set_cs(reg, mask);
184 #define ao_spi_put_mask(reg,mask,bus) do { \
185 ao_spi_clr_cs(reg,mask); \
189 #define ao_spi_get_bit(reg,bit,bus,speed) ao_spi_get_mask(reg,1<<(bit),bus,speed)
190 #define ao_spi_put_bit(reg,bit,bus) ao_spi_put_mask(reg,1<<(bit),bus)
192 #define ao_enable_port(port) do { \
193 if ((port) == &stm_gpioa) \
194 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOAEN); \
195 else if ((port) == &stm_gpiob) \
196 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOBEN); \
197 else if ((port) == &stm_gpioc) \
198 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOCEN); \
199 else if ((port) == &stm_gpiod) \
200 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIODEN); \
201 else if ((port) == &stm_gpioe) \
202 stm_rcc.ahbenr |= (1 << STM_RCC_AHBENR_GPIOEEN); \
205 #define ao_disable_port(port) do { \
206 if ((port) == &stm_gpioa) \
207 stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIOAEN); \
208 else if ((port) == &stm_gpiob) \
209 stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIOBEN); \
210 else if ((port) == &stm_gpioc) \
211 stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIOCEN); \
212 else if ((port) == &stm_gpiod) \
213 stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIODEN); \
214 else if ((port) == &stm_gpioe) \
215 stm_rcc.ahbenr &= ~(1UL << STM_RCC_AHBENR_GPIOEEN); \
219 #define ao_gpio_set(port, bit, v) stm_gpio_set(port, bit, v)
221 #define ao_gpio_get(port, bit) stm_gpio_get(port, bit)
223 #define ao_gpio_set_bits(port, bits) stm_gpio_set_bits(port, bits)
225 #define ao_gpio_set_mask(port, bits, mask) stm_gpio_set_mask(port, bits, mask)
227 #define ao_gpio_clr_bits(port, bits) stm_gpio_clr_bits(port, bits);
229 #define ao_gpio_get_all(port) stm_gpio_get_all(port)
231 #define ao_enable_output(port,bit,v) do { \
232 ao_enable_port(port); \
233 ao_gpio_set(port, bit, v); \
234 stm_moder_set(port, bit, STM_MODER_OUTPUT);\
237 #define ao_enable_output_mask(port,bits,mask) do { \
238 ao_enable_port(port); \
239 ao_gpio_set_mask(port, bits, mask); \
240 ao_set_output_mask(port, mask); \
243 #define AO_OUTPUT_PUSH_PULL STM_OTYPER_PUSH_PULL
244 #define AO_OUTPUT_OPEN_DRAIN STM_OTYPER_OPEN_DRAIN
246 #define ao_gpio_set_output_mode(port,pin,mode) \
247 stm_otyper_set(port, pin, mode)
249 #define ao_gpio_set_mode(port,bit,mode) do { \
250 if (mode == AO_EXTI_MODE_PULL_UP) \
251 stm_pupdr_set(port, bit, STM_PUPDR_PULL_UP); \
252 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
253 stm_pupdr_set(port, bit, STM_PUPDR_PULL_DOWN); \
255 stm_pupdr_set(port, bit, STM_PUPDR_NONE); \
258 #define ao_gpio_set_mode_mask(port,mask,mode) do { \
259 if (mode == AO_EXTI_MODE_PULL_UP) \
260 stm_pupdr_set_mask(port, mask, STM_PUPDR_PULL_UP); \
261 else if (mode == AO_EXTI_MODE_PULL_DOWN) \
262 stm_pupdr_set_mask(port, mask, STM_PUPDR_PULL_DOWN); \
264 stm_pupdr_set_mask(port, mask, STM_PUPDR_NONE); \
267 #define ao_set_input(port, bit) do { \
268 stm_moder_set(port, bit, STM_MODER_INPUT); \
271 #define ao_set_output(port, bit, v) do { \
272 ao_gpio_set(port, bit, v); \
273 stm_moder_set(port, bit, STM_MODER_OUTPUT); \
276 #define ao_set_output_mask(port, mask) do { \
277 stm_moder_set_mask(port, mask, STM_MODER_OUTPUT); \
280 #define ao_set_input_mask(port, mask) do { \
281 stm_moder_set_mask(port, mask, STM_MODER_INPUT); \
284 #define ao_enable_input(port,bit,mode) do { \
285 ao_enable_port(port); \
286 ao_set_input(port, bit); \
287 ao_gpio_set_mode(port, bit, mode); \
290 #define ao_enable_input_mask(port,mask,mode) do { \
291 ao_enable_port(port); \
292 ao_gpio_set_mode_mask(port, mask, mode); \
293 ao_set_input_mask(port, mask); \
296 #define _ao_enable_cs(port, bit) do { \
297 stm_gpio_set((port), bit, 1); \
298 stm_moder_set((port), bit, STM_MODER_OUTPUT); \
301 #define ao_enable_cs(port,bit) do { \
302 ao_enable_port(port); \
303 _ao_enable_cs(port, bit); \
306 #define ao_spi_init_cs(port, mask) do { \
307 ao_enable_port(port); \
308 if ((mask) & 0x0001) _ao_enable_cs(port, 0); \
309 if ((mask) & 0x0002) _ao_enable_cs(port, 1); \
310 if ((mask) & 0x0004) _ao_enable_cs(port, 2); \
311 if ((mask) & 0x0008) _ao_enable_cs(port, 3); \
312 if ((mask) & 0x0010) _ao_enable_cs(port, 4); \
313 if ((mask) & 0x0020) _ao_enable_cs(port, 5); \
314 if ((mask) & 0x0040) _ao_enable_cs(port, 6); \
315 if ((mask) & 0x0080) _ao_enable_cs(port, 7); \
316 if ((mask) & 0x0100) _ao_enable_cs(port, 8); \
317 if ((mask) & 0x0200) _ao_enable_cs(port, 9); \
318 if ((mask) & 0x0400) _ao_enable_cs(port, 10);\
319 if ((mask) & 0x0800) _ao_enable_cs(port, 11);\
320 if ((mask) & 0x1000) _ao_enable_cs(port, 12);\
321 if ((mask) & 0x2000) _ao_enable_cs(port, 13);\
322 if ((mask) & 0x4000) _ao_enable_cs(port, 14);\
323 if ((mask) & 0x8000) _ao_enable_cs(port, 15);\
329 extern uint8_t ao_dma_done[STM_NUM_DMA];
332 ao_dma_set_transfer(uint8_t index,
333 volatile void *peripheral,
339 ao_dma_set_isr(uint8_t index, void (*isr)(int index));
342 ao_dma_start(uint8_t index);
345 ao_dma_done_transfer(uint8_t index);
348 ao_dma_alloc(uint8_t index);
356 ao_i2c_get(uint8_t i2c_index);
359 ao_i2c_start(uint8_t i2c_index, uint16_t address);
362 ao_i2c_put(uint8_t i2c_index);
365 ao_i2c_send(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
368 ao_i2c_recv(void *block, uint16_t len, uint8_t i2c_index, uint8_t stop);
373 #if USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_SW_FLOW || USE_SERIAL_3_SW_FLOW
374 #define HAS_SERIAL_SW_FLOW 1
376 #define HAS_SERIAL_SW_FLOW 0
379 #if USE_SERIAL_1_FLOW && !USE_SERIAL_1_SW_FLOW || USE_SERIAL_2_FLOW && !USE_SERIAL_2_SW_FLOW || USE_SERIAL_3_FLOW && !USE_SERIAL_3_SW_FLOW
380 #define HAS_SERIAL_HW_FLOW 1
382 #define HAS_SERIAL_HW_FLOW 0
385 /* ao_serial_stm.c */
386 struct ao_stm_usart {
387 struct ao_fifo rx_fifo;
388 struct ao_fifo tx_fifo;
389 struct stm_usart *reg;
392 #if HAS_SERIAL_SW_FLOW
393 /* RTS - 0 if we have FIFO space, 1 if not
394 * CTS - 0 if we can send, 0 if not
396 struct stm_gpio *gpio_rts;
397 struct stm_gpio *gpio_cts;
405 ao_debug_out(char c);
408 extern struct ao_stm_usart ao_stm_usart1;
412 extern struct ao_stm_usart ao_stm_usart2;
416 extern struct ao_stm_usart ao_stm_usart3;
419 #define ARM_PUSH32(stack, val) (*(--(stack)) = (val))
421 typedef uint32_t ao_arch_irq_t;
424 ao_arch_block_interrupts(void) {
425 #ifdef AO_NONMASK_INTERRUPTS
426 asm("msr basepri,%0" : : "r" (AO_STM_NVIC_BASEPRI_MASK));
433 ao_arch_release_interrupts(void) {
434 #ifdef AO_NONMASK_INTERRUPTS
435 asm("msr basepri,%0" : : "r" (0x0));
441 static inline uint32_t
442 ao_arch_irqsave(void) {
444 #ifdef AO_NONMASK_INTERRUPTS
445 asm("mrs %0,basepri" : "=r" (val));
447 asm("mrs %0,primask" : "=r" (val));
449 ao_arch_block_interrupts();
454 ao_arch_irqrestore(uint32_t basepri) {
455 #ifdef AO_NONMASK_INTERRUPTS
456 asm("msr basepri,%0" : : "r" (basepri));
458 asm("msr primask,%0" : : "r" (basepri));
463 ao_arch_memory_barrier(void) {
464 asm volatile("" ::: "memory");
468 ao_arch_irq_check(void) {
469 #ifdef AO_NONMASK_INTERRUPTS
471 asm("mrs %0,basepri" : "=r" (basepri));
473 ao_panic(AO_PANIC_IRQ);
476 asm("mrs %0,primask" : "=r" (primask));
477 if ((primask & 1) == 0)
478 ao_panic(AO_PANIC_IRQ);
484 ao_arch_init_stack(struct ao_task *task, uint32_t *sp, void *start)
486 uint32_t a = (uint32_t) start;
489 /* Return address (goes into LR) */
492 /* Clear register values r0-r12 */
500 /* BASEPRI with interrupts enabled */
506 static inline void ao_arch_save_regs(void) {
507 /* Save general registers */
508 asm("push {r0-r12,lr}\n");
514 #ifdef AO_NONMASK_INTERRUPTS
516 asm("mrs r0,basepri");
519 asm("mrs r0,primask");
524 static inline void ao_arch_save_stack(void) {
526 asm("mov %0,sp" : "=&r" (sp) );
527 ao_cur_task->sp32 = (sp);
530 static inline void ao_arch_restore_stack(void) {
532 asm("mov sp, %0" : : "r" (ao_cur_task->sp32) );
534 #ifdef AO_NONMASK_INTERRUPTS
535 /* Restore BASEPRI */
537 asm("msr basepri,r0");
539 /* Restore PRIMASK */
541 asm("msr primask,r0");
546 asm("msr apsr_nczvq,r0");
548 /* Restore general registers */
549 asm("pop {r0-r12,lr}\n");
551 /* Return to calling function */
555 #ifndef HAS_SAMPLE_PROFILE
556 #define HAS_SAMPLE_PROFILE 0
560 #define HAS_ARCH_VALIDATE_CUR_STACK 1
563 ao_validate_cur_stack(void)
567 asm("mrs %0,psp" : "=&r" (psp));
569 (psp <= ao_cur_task->stack8 ||
570 psp >= ao_cur_task->stack8 + AO_STACK_SIZE))
571 ao_panic(AO_PANIC_STACK);
575 #if !HAS_SAMPLE_PROFILE
576 #define HAS_ARCH_START_SCHEDULER 1
578 static inline void ao_arch_start_scheduler(void) {
582 asm("mrs %0,msp" : "=&r" (sp));
583 asm("msr psp,%0" : : "r" (sp));
584 asm("mrs %0,control" : "=r" (control));
586 asm("msr control,%0" : : "r" (control));
591 #define ao_arch_isr_stack()
596 ao_arch_wait_interrupt(void) {
597 #ifdef AO_NONMASK_INTERRUPTS
599 "dsb\n" /* Serialize data */
600 "isb\n" /* Serialize instructions */
601 "cpsid i\n" /* Block all interrupts */
602 "msr basepri,%0\n" /* Allow all interrupts through basepri */
603 "wfi\n" /* Wait for an interrupt */
604 "cpsie i\n" /* Allow all interrupts */
605 "msr basepri,%1\n" /* Block interrupts through basepri */
606 : : "r" (0), "r" (AO_STM_NVIC_BASEPRI_MASK));
609 ao_arch_release_interrupts();
610 ao_arch_block_interrupts();
614 #define ao_arch_critical(b) do { \
615 uint32_t __mask = ao_arch_irqsave(); \
616 do { b } while (0); \
617 ao_arch_irqrestore(__mask); \
622 #endif /* _AO_ARCH_FUNCS_H_ */