2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
22 static uint8_t ao_adc_ready;
24 #define AO_ADC_CR2_VAL ((0 << STM_ADC_CR2_SWSTART) | \
25 (STM_ADC_CR2_EXTEN_DISABLE << STM_ADC_CR2_EXTEN) | \
26 (0 << STM_ADC_CR2_EXTSEL) | \
27 (0 << STM_ADC_CR2_JWSTART) | \
28 (STM_ADC_CR2_JEXTEN_DISABLE << STM_ADC_CR2_JEXTEN) | \
29 (0 << STM_ADC_CR2_JEXTSEL) | \
30 (0 << STM_ADC_CR2_ALIGN) | \
31 (0 << STM_ADC_CR2_EOCS) | \
32 (1 << STM_ADC_CR2_DDS) | \
33 (1 << STM_ADC_CR2_DMA) | \
34 (STM_ADC_CR2_DELS_UNTIL_READ << STM_ADC_CR2_DELS) | \
35 (0 << STM_ADC_CR2_CONT) | \
36 (1 << STM_ADC_CR2_ADON))
39 * Callback from DMA ISR
41 * Mark time in ring, shut down DMA engine
43 static void ao_adc_done(int index)
46 AO_DATA_PRESENT(AO_DATA_ADC);
47 ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
48 if (ao_data_present == AO_DATA_ALL) {
50 ao_data_ring[ao_data_head].ms5607_raw = ao_ms5607_current;
53 ao_data_ring[ao_data_head].mma655x = ao_mma655x_current;
56 ao_data_ring[ao_data_head].hmc5883 = ao_hmc5883_current;
59 ao_data_ring[ao_data_head].mpu6000 = ao_mpu6000_current;
61 ao_data_ring[ao_data_head].tick = ao_tick_count;
62 ao_data_head = ao_data_ring_next(ao_data_head);
63 ao_wakeup((void *) &ao_data_head);
69 * Start the ADC sequence using the DMA engine
78 ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
80 (void *) (&ao_data_ring[ao_data_head].adc),
82 (0 << STM_DMA_CCR_MEM2MEM) |
83 (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
84 (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
85 (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
86 (1 << STM_DMA_CCR_MINC) |
87 (0 << STM_DMA_CCR_PINC) |
88 (0 << STM_DMA_CCR_CIRC) |
89 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
90 ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
91 ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
93 stm_adc.cr2 = AO_ADC_CR2_VAL | (1 << STM_ADC_CR2_SWSTART);
97 * Fetch a copy of the most recent ADC data
100 ao_adc_get(__xdata struct ao_adc *packet)
103 uint8_t i = ao_data_ring_prev(ao_sample_data);
105 uint8_t i = ao_data_ring_prev(ao_data_head);
107 memcpy(packet, (void *) &ao_data_ring[i].adc, sizeof (struct ao_adc));
110 #ifdef AO_ADC_SQ1_NAME
111 static const char *ao_adc_name[AO_NUM_ADC] = {
113 #ifdef AO_ADC_SQ2_NAME
116 #ifdef AO_ADC_SQ3_NAME
119 #ifdef AO_ADC_SQ4_NAME
122 #ifdef AO_ADC_SQ5_NAME
125 #ifdef AO_ADC_SQ6_NAME
128 #ifdef AO_ADC_SQ7_NAME
131 #ifdef AO_ADC_SQ8_NAME
134 #ifdef AO_ADC_SQ9_NAME
137 #ifdef AO_ADC_SQ10_NAME
140 #ifdef AO_ADC_SQ11_NAME
143 #ifdef AO_ADC_SQ12_NAME
146 #ifdef AO_ADC_SQ13_NAME
149 #ifdef AO_ADC_SQ14_NAME
152 #ifdef AO_ADC_SQ15_NAME
155 #ifdef AO_ADC_SQ16_NAME
158 #ifdef AO_ADC_SQ17_NAME
161 #ifdef AO_ADC_SQ18_NAME
164 #ifdef AO_ADC_SQ19_NAME
167 #ifdef AO_ADC_SQ20_NAME
170 #ifdef AO_ADC_SQ21_NAME
171 #error "too many ADC names"
177 ao_adc_dump(void) __reentrant
179 struct ao_data packet;
185 ao_data_get(&packet);
187 AO_ADC_DUMP(&packet);
189 printf("tick: %5u", packet.tick);
190 d = (int16_t *) (&packet.adc);
191 for (i = 0; i < AO_NUM_ADC; i++) {
192 #ifdef AO_ADC_SQ1_NAME
194 printf (" %s: %5d", ao_adc_name[i], d[i]);
197 printf (" %2d: %5d", i, d[i]);
203 __code struct ao_cmds ao_adc_cmds[] = {
204 { ao_adc_dump, "a\0Display current ADC values" },
211 #ifdef AO_ADC_PIN0_PORT
212 stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
215 #ifdef AO_ADC_PIN0_PORT
216 stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
218 #ifdef AO_ADC_PIN1_PORT
219 stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
221 #ifdef AO_ADC_PIN2_PORT
222 stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
224 #ifdef AO_ADC_PIN3_PORT
225 stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
227 #ifdef AO_ADC_PIN4_PORT
228 stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
230 #ifdef AO_ADC_PIN5_PORT
231 stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
233 #ifdef AO_ADC_PIN6_PORT
234 stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
236 #ifdef AO_ADC_PIN7_PORT
237 stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
239 #ifdef AO_ADC_PIN8_PORT
240 stm_moder_set(AO_ADC_PIN8_PORT, AO_ADC_PIN8_PIN, STM_MODER_ANALOG);
242 #ifdef AO_ADC_PIN9_PORT
243 stm_moder_set(AO_ADC_PIN9_PORT, AO_ADC_PIN9_PIN, STM_MODER_ANALOG);
245 #ifdef AO_ADC_PIN10_PORT
246 stm_moder_set(AO_ADC_PIN10_PORT, AO_ADC_PIN10_PIN, STM_MODER_ANALOG);
248 #ifdef AO_ADC_PIN11_PORT
249 stm_moder_set(AO_ADC_PIN11_PORT, AO_ADC_PIN11_PIN, STM_MODER_ANALOG);
251 #ifdef AO_ADC_PIN12_PORT
252 stm_moder_set(AO_ADC_PIN12_PORT, AO_ADC_PIN12_PIN, STM_MODER_ANALOG);
254 #ifdef AO_ADC_PIN13_PORT
255 stm_moder_set(AO_ADC_PIN13_PORT, AO_ADC_PIN13_PIN, STM_MODER_ANALOG);
257 #ifdef AO_ADC_PIN14_PORT
258 stm_moder_set(AO_ADC_PIN14_PORT, AO_ADC_PIN14_PIN, STM_MODER_ANALOG);
260 #ifdef AO_ADC_PIN15_PORT
261 stm_moder_set(AO_ADC_PIN15_PORT, AO_ADC_PIN15_PIN, STM_MODER_ANALOG);
263 #ifdef AO_ADC_PIN16_PORT
264 stm_moder_set(AO_ADC_PIN16_PORT, AO_ADC_PIN16_PIN, STM_MODER_ANALOG);
266 #ifdef AO_ADC_PIN17_PORT
267 stm_moder_set(AO_ADC_PIN17_PORT, AO_ADC_PIN17_PIN, STM_MODER_ANALOG);
269 #ifdef AO_ADC_PIN18_PORT
270 stm_moder_set(AO_ADC_PIN18_PORT, AO_ADC_PIN18_PIN, STM_MODER_ANALOG);
272 #ifdef AO_ADC_PIN19_PORT
273 stm_moder_set(AO_ADC_PIN19_PORT, AO_ADC_PIN19_PIN, STM_MODER_ANALOG);
275 #ifdef AO_ADC_PIN20_PORT
276 stm_moder_set(AO_ADC_PIN20_PORT, AO_ADC_PIN20_PIN, STM_MODER_ANALOG);
278 #ifdef AO_ADC_PIN21_PORT
279 stm_moder_set(AO_ADC_PIN21_PORT, AO_ADC_PIN21_PIN, STM_MODER_ANALOG);
281 #ifdef AO_ADC_PIN22_PORT
282 stm_moder_set(AO_ADC_PIN22_PORT, AO_ADC_PIN22_PIN, STM_MODER_ANALOG);
284 #ifdef AO_ADC_PIN23_PORT
285 stm_moder_set(AO_ADC_PIN23_PORT, AO_ADC_PIN23_PIN, STM_MODER_ANALOG);
287 #ifdef AO_ADC_PIN24_PORT
288 #error "Too many ADC ports"
291 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
293 /* Turn off ADC during configuration */
296 stm_adc.cr1 = ((0 << STM_ADC_CR1_OVRIE ) |
297 (STM_ADC_CR1_RES_12 << STM_ADC_CR1_RES ) |
298 (0 << STM_ADC_CR1_AWDEN ) |
299 (0 << STM_ADC_CR1_JAWDEN ) |
300 (0 << STM_ADC_CR1_PDI ) |
301 (0 << STM_ADC_CR1_PDD ) |
302 (0 << STM_ADC_CR1_DISCNUM ) |
303 (0 << STM_ADC_CR1_JDISCEN ) |
304 (0 << STM_ADC_CR1_DISCEN ) |
305 (0 << STM_ADC_CR1_JAUTO ) |
306 (0 << STM_ADC_CR1_AWDSGL ) |
307 (1 << STM_ADC_CR1_SCAN ) |
308 (0 << STM_ADC_CR1_JEOCIE ) |
309 (0 << STM_ADC_CR1_AWDIE ) |
310 (0 << STM_ADC_CR1_EOCIE ) |
311 (0 << STM_ADC_CR1_AWDCH ));
313 /* 384 cycle sample time for everyone */
314 stm_adc.smpr1 = 0x3ffff;
315 stm_adc.smpr2 = 0x3fffffff;
316 stm_adc.smpr3 = 0x3fffffff;
318 stm_adc.sqr1 = ((AO_NUM_ADC - 1) << 20);
324 stm_adc.sqr5 |= (AO_ADC_SQ1 << 0);
327 stm_adc.sqr5 |= (AO_ADC_SQ2 << 5);
330 stm_adc.sqr5 |= (AO_ADC_SQ3 << 10);
333 stm_adc.sqr5 |= (AO_ADC_SQ4 << 15);
336 stm_adc.sqr5 |= (AO_ADC_SQ5 << 20);
339 stm_adc.sqr5 |= (AO_ADC_SQ6 << 25);
342 stm_adc.sqr4 |= (AO_ADC_SQ7 << 0);
345 stm_adc.sqr4 |= (AO_ADC_SQ8 << 5);
348 stm_adc.sqr4 |= (AO_ADC_SQ9 << 10);
351 stm_adc.sqr4 |= (AO_ADC_SQ10 << 15);
354 stm_adc.sqr4 |= (AO_ADC_SQ11 << 20);
357 stm_adc.sqr4 |= (AO_ADC_SQ12 << 25);
360 stm_adc.sqr3 |= (AO_ADC_SQ13 << 0);
363 stm_adc.sqr3 |= (AO_ADC_SQ14 << 5);
366 stm_adc.sqr3 |= (AO_ADC_SQ15 << 10);
369 stm_adc.sqr3 |= (AO_ADC_SQ16 << 15);
372 stm_adc.sqr3 |= (AO_ADC_SQ17 << 20);
375 stm_adc.sqr3 |= (AO_ADC_SQ18 << 25);
378 #error "need to finish stm_adc.sqr settings"
382 stm_adc.cr2 = AO_ADC_CR2_VAL;
384 /* Wait for ADC to be ready */
385 while (!(stm_adc.sr & (1 << STM_ADC_SR_ADONS)))
389 #error Please define HAS_ADC_TEMP
392 stm_adc.ccr = ((1 << STM_ADC_CCR_TSVREFE));
396 /* Clear any stale status bits */
399 ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
401 ao_cmd_register(&ao_adc_cmds[0]);