2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
22 static uint8_t ao_adc_ready;
24 #define AO_ADC_CR2_VAL ((0 << STM_ADC_CR2_SWSTART) | \
25 (STM_ADC_CR2_EXTEN_DISABLE << STM_ADC_CR2_EXTEN) | \
26 (0 << STM_ADC_CR2_EXTSEL) | \
27 (0 << STM_ADC_CR2_JWSTART) | \
28 (STM_ADC_CR2_JEXTEN_DISABLE << STM_ADC_CR2_JEXTEN) | \
29 (0 << STM_ADC_CR2_JEXTSEL) | \
30 (0 << STM_ADC_CR2_ALIGN) | \
31 (0 << STM_ADC_CR2_EOCS) | \
32 (1 << STM_ADC_CR2_DDS) | \
33 (1 << STM_ADC_CR2_DMA) | \
34 (STM_ADC_CR2_DELS_UNTIL_READ << STM_ADC_CR2_DELS) | \
35 (0 << STM_ADC_CR2_CONT) | \
36 (1 << STM_ADC_CR2_ADON))
39 * Callback from DMA ISR
41 * Mark time in ring, shut down DMA engine
43 static void ao_adc_done(int index)
46 AO_DATA_PRESENT(AO_DATA_ADC);
47 ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
48 ao_data_fill(ao_data_head);
53 * Start the ADC sequence using the DMA engine
62 ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
64 (void *) (&ao_data_ring[ao_data_head].adc),
66 (0 << STM_DMA_CCR_MEM2MEM) |
67 (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
68 (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
69 (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
70 (1 << STM_DMA_CCR_MINC) |
71 (0 << STM_DMA_CCR_PINC) |
72 (0 << STM_DMA_CCR_CIRC) |
73 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
74 ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
75 ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
77 stm_adc.cr2 = AO_ADC_CR2_VAL | (1 << STM_ADC_CR2_SWSTART);
80 #ifdef AO_ADC_SQ1_NAME
81 static const char *ao_adc_name[AO_NUM_ADC] = {
83 #ifdef AO_ADC_SQ2_NAME
86 #ifdef AO_ADC_SQ3_NAME
89 #ifdef AO_ADC_SQ4_NAME
92 #ifdef AO_ADC_SQ5_NAME
95 #ifdef AO_ADC_SQ6_NAME
98 #ifdef AO_ADC_SQ7_NAME
101 #ifdef AO_ADC_SQ8_NAME
104 #ifdef AO_ADC_SQ9_NAME
107 #ifdef AO_ADC_SQ10_NAME
110 #ifdef AO_ADC_SQ11_NAME
113 #ifdef AO_ADC_SQ12_NAME
116 #ifdef AO_ADC_SQ13_NAME
119 #ifdef AO_ADC_SQ14_NAME
122 #ifdef AO_ADC_SQ15_NAME
125 #ifdef AO_ADC_SQ16_NAME
128 #ifdef AO_ADC_SQ17_NAME
131 #ifdef AO_ADC_SQ18_NAME
134 #ifdef AO_ADC_SQ19_NAME
137 #ifdef AO_ADC_SQ20_NAME
140 #ifdef AO_ADC_SQ21_NAME
141 #error "too many ADC names"
149 struct ao_data packet;
155 ao_data_get(&packet);
157 AO_ADC_DUMP(&packet);
159 printf("tick: %5u", packet.tick);
160 d = (int16_t *) (&packet.adc);
161 for (i = 0; i < AO_NUM_ADC; i++) {
162 #ifdef AO_ADC_SQ1_NAME
164 printf (" %s: %5d", ao_adc_name[i], d[i]);
167 printf (" %2d: %5d", i, d[i]);
173 const struct ao_cmds ao_adc_cmds[] = {
174 { ao_adc_dump, "a\0Display current ADC values" },
181 #ifdef AO_ADC_PIN0_PORT
182 stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
185 #ifdef AO_ADC_PIN0_PORT
186 stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
188 #ifdef AO_ADC_PIN1_PORT
189 stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
191 #ifdef AO_ADC_PIN2_PORT
192 stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
194 #ifdef AO_ADC_PIN3_PORT
195 stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
197 #ifdef AO_ADC_PIN4_PORT
198 stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
200 #ifdef AO_ADC_PIN5_PORT
201 stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
203 #ifdef AO_ADC_PIN6_PORT
204 stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
206 #ifdef AO_ADC_PIN7_PORT
207 stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
209 #ifdef AO_ADC_PIN8_PORT
210 stm_moder_set(AO_ADC_PIN8_PORT, AO_ADC_PIN8_PIN, STM_MODER_ANALOG);
212 #ifdef AO_ADC_PIN9_PORT
213 stm_moder_set(AO_ADC_PIN9_PORT, AO_ADC_PIN9_PIN, STM_MODER_ANALOG);
215 #ifdef AO_ADC_PIN10_PORT
216 stm_moder_set(AO_ADC_PIN10_PORT, AO_ADC_PIN10_PIN, STM_MODER_ANALOG);
218 #ifdef AO_ADC_PIN11_PORT
219 stm_moder_set(AO_ADC_PIN11_PORT, AO_ADC_PIN11_PIN, STM_MODER_ANALOG);
221 #ifdef AO_ADC_PIN12_PORT
222 stm_moder_set(AO_ADC_PIN12_PORT, AO_ADC_PIN12_PIN, STM_MODER_ANALOG);
224 #ifdef AO_ADC_PIN13_PORT
225 stm_moder_set(AO_ADC_PIN13_PORT, AO_ADC_PIN13_PIN, STM_MODER_ANALOG);
227 #ifdef AO_ADC_PIN14_PORT
228 stm_moder_set(AO_ADC_PIN14_PORT, AO_ADC_PIN14_PIN, STM_MODER_ANALOG);
230 #ifdef AO_ADC_PIN15_PORT
231 stm_moder_set(AO_ADC_PIN15_PORT, AO_ADC_PIN15_PIN, STM_MODER_ANALOG);
233 #ifdef AO_ADC_PIN16_PORT
234 stm_moder_set(AO_ADC_PIN16_PORT, AO_ADC_PIN16_PIN, STM_MODER_ANALOG);
236 #ifdef AO_ADC_PIN17_PORT
237 stm_moder_set(AO_ADC_PIN17_PORT, AO_ADC_PIN17_PIN, STM_MODER_ANALOG);
239 #ifdef AO_ADC_PIN18_PORT
240 stm_moder_set(AO_ADC_PIN18_PORT, AO_ADC_PIN18_PIN, STM_MODER_ANALOG);
242 #ifdef AO_ADC_PIN19_PORT
243 stm_moder_set(AO_ADC_PIN19_PORT, AO_ADC_PIN19_PIN, STM_MODER_ANALOG);
245 #ifdef AO_ADC_PIN20_PORT
246 stm_moder_set(AO_ADC_PIN20_PORT, AO_ADC_PIN20_PIN, STM_MODER_ANALOG);
248 #ifdef AO_ADC_PIN21_PORT
249 stm_moder_set(AO_ADC_PIN21_PORT, AO_ADC_PIN21_PIN, STM_MODER_ANALOG);
251 #ifdef AO_ADC_PIN22_PORT
252 stm_moder_set(AO_ADC_PIN22_PORT, AO_ADC_PIN22_PIN, STM_MODER_ANALOG);
254 #ifdef AO_ADC_PIN23_PORT
255 stm_moder_set(AO_ADC_PIN23_PORT, AO_ADC_PIN23_PIN, STM_MODER_ANALOG);
257 #ifdef AO_ADC_PIN24_PORT
258 #error "Too many ADC ports"
261 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
263 /* Turn off ADC during configuration */
266 stm_adc.cr1 = ((0 << STM_ADC_CR1_OVRIE ) |
267 (STM_ADC_CR1_RES_12 << STM_ADC_CR1_RES ) |
268 (0 << STM_ADC_CR1_AWDEN ) |
269 (0 << STM_ADC_CR1_JAWDEN ) |
270 (0 << STM_ADC_CR1_PDI ) |
271 (0 << STM_ADC_CR1_PDD ) |
272 (0 << STM_ADC_CR1_DISCNUM ) |
273 (0 << STM_ADC_CR1_JDISCEN ) |
274 (0 << STM_ADC_CR1_DISCEN ) |
275 (0 << STM_ADC_CR1_JAUTO ) |
276 (0 << STM_ADC_CR1_AWDSGL ) |
277 (1 << STM_ADC_CR1_SCAN ) |
278 (0 << STM_ADC_CR1_JEOCIE ) |
279 (0 << STM_ADC_CR1_AWDIE ) |
280 (0 << STM_ADC_CR1_EOCIE ) |
281 (0 << STM_ADC_CR1_AWDCH ));
283 /* 384 cycle sample time for everyone */
284 stm_adc.smpr1 = 0x3ffff;
285 stm_adc.smpr2 = 0x3fffffff;
286 stm_adc.smpr3 = 0x3fffffff;
288 stm_adc.sqr1 = ((AO_NUM_ADC - 1) << 20);
294 stm_adc.sqr5 |= (AO_ADC_SQ1 << 0);
297 stm_adc.sqr5 |= (AO_ADC_SQ2 << 5);
300 stm_adc.sqr5 |= (AO_ADC_SQ3 << 10);
303 stm_adc.sqr5 |= (AO_ADC_SQ4 << 15);
306 stm_adc.sqr5 |= (AO_ADC_SQ5 << 20);
309 stm_adc.sqr5 |= (AO_ADC_SQ6 << 25);
312 stm_adc.sqr4 |= (AO_ADC_SQ7 << 0);
315 stm_adc.sqr4 |= (AO_ADC_SQ8 << 5);
318 stm_adc.sqr4 |= (AO_ADC_SQ9 << 10);
321 stm_adc.sqr4 |= (AO_ADC_SQ10 << 15);
324 stm_adc.sqr4 |= (AO_ADC_SQ11 << 20);
327 stm_adc.sqr4 |= (AO_ADC_SQ12 << 25);
330 stm_adc.sqr3 |= (AO_ADC_SQ13 << 0);
333 stm_adc.sqr3 |= (AO_ADC_SQ14 << 5);
336 stm_adc.sqr3 |= (AO_ADC_SQ15 << 10);
339 stm_adc.sqr3 |= (AO_ADC_SQ16 << 15);
342 stm_adc.sqr3 |= (AO_ADC_SQ17 << 20);
345 stm_adc.sqr3 |= (AO_ADC_SQ18 << 25);
348 #error "need to finish stm_adc.sqr settings"
352 stm_adc.cr2 = AO_ADC_CR2_VAL;
354 /* Wait for ADC to be ready */
355 while (!(stm_adc.sr & (1 << STM_ADC_SR_ADONS)))
359 #error Please define HAS_ADC_TEMP
362 stm_adc.ccr = ((1 << STM_ADC_CCR_TSVREFE));
366 /* Clear any stale status bits */
369 ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
371 ao_cmd_register(&ao_adc_cmds[0]);