2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 #include <ao_mpu6000.h>
24 #include <ao_ms5607.h>
27 volatile __xdata struct ao_data ao_data_ring[AO_DATA_RING];
28 volatile __data uint8_t ao_data_head;
30 static uint8_t ao_adc_ready;
32 #define AO_ADC_CR2_VAL ((0 << STM_ADC_CR2_SWSTART) | \
33 (STM_ADC_CR2_EXTEN_DISABLE << STM_ADC_CR2_EXTEN) | \
34 (0 << STM_ADC_CR2_EXTSEL) | \
35 (0 << STM_ADC_CR2_JWSTART) | \
36 (STM_ADC_CR2_JEXTEN_DISABLE << STM_ADC_CR2_JEXTEN) | \
37 (0 << STM_ADC_CR2_JEXTSEL) | \
38 (0 << STM_ADC_CR2_ALIGN) | \
39 (0 << STM_ADC_CR2_EOCS) | \
40 (1 << STM_ADC_CR2_DDS) | \
41 (1 << STM_ADC_CR2_DMA) | \
42 (STM_ADC_CR2_DELS_UNTIL_READ << STM_ADC_CR2_DELS) | \
43 (0 << STM_ADC_CR2_CONT) | \
44 (1 << STM_ADC_CR2_ADON))
47 * Callback from DMA ISR
49 * Mark time in ring, shut down DMA engine
51 static void ao_adc_done(int index)
54 ao_data_ring[ao_data_head].tick = ao_time();
56 if (!ao_mpu6000_valid)
58 ao_data_ring[ao_data_head].mpu6000 = ao_mpu6000_current;
63 ao_data_ring[ao_data_head].ms5607_raw = ao_ms5607_current;
66 if (!ao_hmc5883_valid)
68 ao_data_ring[ao_data_head].hmc5883 = ao_hmc5883_current;
71 ao_data_head = ao_data_ring_next(ao_data_head);
72 ao_wakeup((void *) &ao_data_head);
74 ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
79 * Start the ADC sequence using the DMA engine
88 ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
90 (void *) (&ao_data_ring[ao_data_head].adc),
92 (0 << STM_DMA_CCR_MEM2MEM) |
93 (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
94 (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
95 (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
96 (1 << STM_DMA_CCR_MINC) |
97 (0 << STM_DMA_CCR_PINC) |
98 (0 << STM_DMA_CCR_CIRC) |
99 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
100 ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
101 ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
103 stm_adc.cr2 = AO_ADC_CR2_VAL | (1 << STM_ADC_CR2_SWSTART);
107 * Fetch a copy of the most recent ADC data
110 ao_adc_get(__xdata struct ao_adc *packet)
113 uint8_t i = ao_data_ring_prev(ao_sample_data);
115 uint8_t i = ao_data_ring_prev(ao_data_head);
117 memcpy(packet, (void *) &ao_data_ring[i].adc, sizeof (struct ao_adc));
121 ao_data_get(__xdata struct ao_data *packet)
124 uint8_t i = ao_data_ring_prev(ao_sample_data);
126 uint8_t i = ao_data_ring_prev(ao_data_head);
128 memcpy(packet, (void *) &ao_data_ring[i], sizeof (struct ao_data));
132 ao_adc_dump(void) __reentrant
134 struct ao_data packet;
138 ao_data_get(&packet);
139 printf("tick: %5u", packet.tick);
140 d = (int16_t *) (&packet.adc);
141 for (i = 0; i < AO_NUM_ADC; i++)
142 printf (" %2d: %5d", i, d[i]);
146 __code struct ao_cmds ao_adc_cmds[] = {
147 { ao_adc_dump, "a\0Display current ADC values" },
154 #ifdef AO_ADC_PIN0_PORT
155 stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
158 #ifdef AO_ADC_PIN0_PORT
159 stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
161 #ifdef AO_ADC_PIN1_PORT
162 stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
164 #ifdef AO_ADC_PIN2_PORT
165 stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
167 #ifdef AO_ADC_PIN3_PORT
168 stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
170 #ifdef AO_ADC_PIN4_PORT
171 stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
173 #ifdef AO_ADC_PIN5_PORT
174 stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
176 #ifdef AO_ADC_PIN6_PORT
177 stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
179 #ifdef AO_ADC_PIN7_PORT
180 stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
182 #ifdef AO_ADC_PIN8_PORT
183 stm_moder_set(AO_ADC_PIN8_PORT, AO_ADC_PIN8_PIN, STM_MODER_ANALOG);
185 #ifdef AO_ADC_PIN9_PORT
186 stm_moder_set(AO_ADC_PIN9_PORT, AO_ADC_PIN9_PIN, STM_MODER_ANALOG);
188 #ifdef AO_ADC_PIN10_PORT
189 stm_moder_set(AO_ADC_PIN10_PORT, AO_ADC_PIN10_PIN, STM_MODER_ANALOG);
191 #ifdef AO_ADC_PIN11_PORT
192 stm_moder_set(AO_ADC_PIN11_PORT, AO_ADC_PIN11_PIN, STM_MODER_ANALOG);
194 #ifdef AO_ADC_PIN12_PORT
195 stm_moder_set(AO_ADC_PIN12_PORT, AO_ADC_PIN12_PIN, STM_MODER_ANALOG);
198 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
200 /* Turn off ADC during configuration */
203 stm_adc.cr1 = ((0 << STM_ADC_CR1_OVRIE ) |
204 (STM_ADC_CR1_RES_12 << STM_ADC_CR1_RES ) |
205 (0 << STM_ADC_CR1_AWDEN ) |
206 (0 << STM_ADC_CR1_JAWDEN ) |
207 (0 << STM_ADC_CR1_PDI ) |
208 (0 << STM_ADC_CR1_PDD ) |
209 (0 << STM_ADC_CR1_DISCNUM ) |
210 (0 << STM_ADC_CR1_JDISCEN ) |
211 (0 << STM_ADC_CR1_DISCEN ) |
212 (0 << STM_ADC_CR1_JAUTO ) |
213 (0 << STM_ADC_CR1_AWDSGL ) |
214 (1 << STM_ADC_CR1_SCAN ) |
215 (0 << STM_ADC_CR1_JEOCIE ) |
216 (0 << STM_ADC_CR1_AWDIE ) |
217 (0 << STM_ADC_CR1_EOCIE ) |
218 (0 << STM_ADC_CR1_AWDCH ));
220 /* 384 cycle sample time for everyone */
221 stm_adc.smpr1 = 0x3ffff;
222 stm_adc.smpr2 = 0x3fffffff;
223 stm_adc.smpr3 = 0x3fffffff;
225 stm_adc.sqr1 = ((AO_NUM_ADC - 1) << 20);
231 stm_adc.sqr5 |= (AO_ADC_SQ1 << 0);
234 stm_adc.sqr5 |= (AO_ADC_SQ2 << 5);
237 stm_adc.sqr5 |= (AO_ADC_SQ3 << 10);
240 stm_adc.sqr5 |= (AO_ADC_SQ4 << 15);
243 stm_adc.sqr5 |= (AO_ADC_SQ5 << 20);
246 stm_adc.sqr5 |= (AO_ADC_SQ6 << 25);
249 stm_adc.sqr4 |= (AO_ADC_SQ7 << 0);
252 stm_adc.sqr4 |= (AO_ADC_SQ8 << 5);
255 stm_adc.sqr4 |= (AO_ADC_SQ9 << 10);
258 stm_adc.sqr4 |= (AO_ADC_SQ10 << 15);
261 stm_adc.sqr4 |= (AO_ADC_SQ11 << 20);
264 stm_adc.sqr4 |= (AO_ADC_SQ12 << 25);
267 #error "need to finish stm_adc.sqr settings"
271 stm_adc.cr2 = AO_ADC_CR2_VAL;
273 /* Wait for ADC to be ready */
274 while (!(stm_adc.sr & (1 << STM_ADC_SR_ADONS)))
278 stm_adc.ccr = ((1 << STM_ADC_CCR_TSVREFE));
282 /* Clear any stale status bits */
285 ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
287 ao_cmd_register(&ao_adc_cmds[0]);