2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
8 * This program is distributed in the hope that it will be useful, but
9 * WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
11 * General Public License for more details.
13 * You should have received a copy of the GNU General Public License along
14 * with this program; if not, write to the Free Software Foundation, Inc.,
15 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 static uint8_t ao_adc_ready;
23 #define AO_ADC_CR2_VAL ((0 << STM_ADC_CR2_SWSTART) | \
24 (STM_ADC_CR2_EXTEN_DISABLE << STM_ADC_CR2_EXTEN) | \
25 (0 << STM_ADC_CR2_EXTSEL) | \
26 (0 << STM_ADC_CR2_JWSTART) | \
27 (STM_ADC_CR2_JEXTEN_DISABLE << STM_ADC_CR2_JEXTEN) | \
28 (0 << STM_ADC_CR2_JEXTSEL) | \
29 (0 << STM_ADC_CR2_ALIGN) | \
30 (0 << STM_ADC_CR2_EOCS) | \
31 (1 << STM_ADC_CR2_DDS) | \
32 (1 << STM_ADC_CR2_DMA) | \
33 (STM_ADC_CR2_DELS_UNTIL_READ << STM_ADC_CR2_DELS) | \
34 (0 << STM_ADC_CR2_CONT) | \
35 (1 << STM_ADC_CR2_ADON))
38 * Callback from DMA ISR
40 * Mark time in ring, shut down DMA engine
42 static void ao_adc_done(int index)
44 AO_DATA_PRESENT(AO_DATA_ADC);
45 ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
50 * Start the ADC sequence using the DMA engine
59 ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
61 (void *) (&ao_data_ring[ao_data_head].adc),
63 (0 << STM_DMA_CCR_MEM2MEM) |
64 (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
65 (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
66 (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
67 (1 << STM_DMA_CCR_MINC) |
68 (0 << STM_DMA_CCR_PINC) |
69 (0 << STM_DMA_CCR_CIRC) |
70 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
71 ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
72 ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
74 stm_adc.cr2 = AO_ADC_CR2_VAL | (1 << STM_ADC_CR2_SWSTART);
78 * Fetch a copy of the most recent ADC data
81 ao_adc_get(__xdata struct ao_adc *packet)
84 uint8_t i = ao_data_ring_prev(ao_sample_data);
86 uint8_t i = ao_data_ring_prev(ao_data_head);
88 memcpy(packet, (void *) &ao_data_ring[i].adc, sizeof (struct ao_adc));
92 ao_adc_dump(void) __reentrant
94 struct ao_data packet;
99 printf("tick: %5u", packet.tick);
100 d = (int16_t *) (&packet.adc);
101 for (i = 0; i < AO_NUM_ADC; i++)
102 printf (" %2d: %5d", i, d[i]);
106 __code struct ao_cmds ao_adc_cmds[] = {
107 { ao_adc_dump, "a\0Display current ADC values" },
114 #ifdef AO_ADC_PIN0_PORT
115 stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
118 #ifdef AO_ADC_PIN0_PORT
119 stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
121 #ifdef AO_ADC_PIN1_PORT
122 stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
124 #ifdef AO_ADC_PIN2_PORT
125 stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
127 #ifdef AO_ADC_PIN3_PORT
128 stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
130 #ifdef AO_ADC_PIN4_PORT
131 stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
133 #ifdef AO_ADC_PIN5_PORT
134 stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
136 #ifdef AO_ADC_PIN6_PORT
137 stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
139 #ifdef AO_ADC_PIN7_PORT
140 stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
142 #ifdef AO_ADC_PIN8_PORT
143 stm_moder_set(AO_ADC_PIN8_PORT, AO_ADC_PIN8_PIN, STM_MODER_ANALOG);
145 #ifdef AO_ADC_PIN9_PORT
146 stm_moder_set(AO_ADC_PIN9_PORT, AO_ADC_PIN9_PIN, STM_MODER_ANALOG);
148 #ifdef AO_ADC_PIN10_PORT
149 stm_moder_set(AO_ADC_PIN10_PORT, AO_ADC_PIN10_PIN, STM_MODER_ANALOG);
151 #ifdef AO_ADC_PIN11_PORT
152 stm_moder_set(AO_ADC_PIN11_PORT, AO_ADC_PIN11_PIN, STM_MODER_ANALOG);
154 #ifdef AO_ADC_PIN12_PORT
155 stm_moder_set(AO_ADC_PIN12_PORT, AO_ADC_PIN12_PIN, STM_MODER_ANALOG);
158 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
160 /* Turn off ADC during configuration */
163 stm_adc.cr1 = ((0 << STM_ADC_CR1_OVRIE ) |
164 (STM_ADC_CR1_RES_12 << STM_ADC_CR1_RES ) |
165 (0 << STM_ADC_CR1_AWDEN ) |
166 (0 << STM_ADC_CR1_JAWDEN ) |
167 (0 << STM_ADC_CR1_PDI ) |
168 (0 << STM_ADC_CR1_PDD ) |
169 (0 << STM_ADC_CR1_DISCNUM ) |
170 (0 << STM_ADC_CR1_JDISCEN ) |
171 (0 << STM_ADC_CR1_DISCEN ) |
172 (0 << STM_ADC_CR1_JAUTO ) |
173 (0 << STM_ADC_CR1_AWDSGL ) |
174 (1 << STM_ADC_CR1_SCAN ) |
175 (0 << STM_ADC_CR1_JEOCIE ) |
176 (0 << STM_ADC_CR1_AWDIE ) |
177 (0 << STM_ADC_CR1_EOCIE ) |
178 (0 << STM_ADC_CR1_AWDCH ));
180 /* 384 cycle sample time for everyone */
181 stm_adc.smpr1 = 0x3ffff;
182 stm_adc.smpr2 = 0x3fffffff;
183 stm_adc.smpr3 = 0x3fffffff;
185 stm_adc.sqr1 = ((AO_NUM_ADC - 1) << 20);
191 stm_adc.sqr5 |= (AO_ADC_SQ1 << 0);
194 stm_adc.sqr5 |= (AO_ADC_SQ2 << 5);
197 stm_adc.sqr5 |= (AO_ADC_SQ3 << 10);
200 stm_adc.sqr5 |= (AO_ADC_SQ4 << 15);
203 stm_adc.sqr5 |= (AO_ADC_SQ5 << 20);
206 stm_adc.sqr5 |= (AO_ADC_SQ6 << 25);
209 stm_adc.sqr4 |= (AO_ADC_SQ7 << 0);
212 stm_adc.sqr4 |= (AO_ADC_SQ8 << 5);
215 stm_adc.sqr4 |= (AO_ADC_SQ9 << 10);
218 stm_adc.sqr4 |= (AO_ADC_SQ10 << 15);
221 stm_adc.sqr4 |= (AO_ADC_SQ11 << 20);
224 stm_adc.sqr4 |= (AO_ADC_SQ12 << 25);
227 #error "need to finish stm_adc.sqr settings"
231 stm_adc.cr2 = AO_ADC_CR2_VAL;
233 /* Wait for ADC to be ready */
234 while (!(stm_adc.sr & (1 << STM_ADC_SR_ADONS)))
238 stm_adc.ccr = ((1 << STM_ADC_CCR_TSVREFE));
242 /* Clear any stale status bits */
245 ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
247 ao_cmd_register(&ao_adc_cmds[0]);