2 * Copyright © 2012 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
21 #include <ao_adc_single.h>
23 static uint8_t ao_adc_ready;
25 #define AO_ADC_CR2_VAL ((0 << STM_ADC_CR2_SWSTART) | \
26 (STM_ADC_CR2_EXTEN_DISABLE << STM_ADC_CR2_EXTEN) | \
27 (0 << STM_ADC_CR2_EXTSEL) | \
28 (0 << STM_ADC_CR2_JWSTART) | \
29 (STM_ADC_CR2_JEXTEN_DISABLE << STM_ADC_CR2_JEXTEN) | \
30 (0 << STM_ADC_CR2_JEXTSEL) | \
31 (0 << STM_ADC_CR2_ALIGN) | \
32 (0 << STM_ADC_CR2_EOCS) | \
33 (1 << STM_ADC_CR2_DDS) | \
34 (1 << STM_ADC_CR2_DMA) | \
35 (STM_ADC_CR2_DELS_UNTIL_READ << STM_ADC_CR2_DELS) | \
36 (0 << STM_ADC_CR2_CONT) | \
37 (1 << STM_ADC_CR2_ADON))
40 * Callback from DMA ISR
42 * Shut down DMA engine, signal anyone waiting
44 static void ao_adc_done(int index)
47 ao_dma_done_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
49 ao_wakeup((void *) &ao_adc_ready);
53 * Start the ADC sequence using the DMA engine
56 ao_adc_poll(struct ao_adc *packet)
60 ao_dma_set_transfer(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1),
64 (0 << STM_DMA_CCR_MEM2MEM) |
65 (STM_DMA_CCR_PL_HIGH << STM_DMA_CCR_PL) |
66 (STM_DMA_CCR_MSIZE_16 << STM_DMA_CCR_MSIZE) |
67 (STM_DMA_CCR_PSIZE_16 << STM_DMA_CCR_PSIZE) |
68 (1 << STM_DMA_CCR_MINC) |
69 (0 << STM_DMA_CCR_PINC) |
70 (0 << STM_DMA_CCR_CIRC) |
71 (STM_DMA_CCR_DIR_PER_TO_MEM << STM_DMA_CCR_DIR));
72 ao_dma_set_isr(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1), ao_adc_done);
73 ao_dma_start(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
75 stm_adc.cr2 = AO_ADC_CR2_VAL | (1 << STM_ADC_CR2_SWSTART);
79 * Fetch a copy of the most recent ADC data
82 ao_adc_single_get(struct ao_adc *packet)
85 ao_arch_block_interrupts();
87 ao_sleep(&ao_adc_ready);
88 ao_arch_release_interrupts();
95 ao_adc_single_get(&packet);
99 const struct ao_cmds ao_adc_cmds[] = {
100 { ao_adc_dump, "a\0Display current ADC values" },
105 ao_adc_single_init(void)
107 #ifdef AO_ADC_PIN0_PORT
108 stm_rcc.ahbenr |= AO_ADC_RCC_AHBENR;
111 #ifdef AO_ADC_PIN0_PORT
112 stm_moder_set(AO_ADC_PIN0_PORT, AO_ADC_PIN0_PIN, STM_MODER_ANALOG);
114 #ifdef AO_ADC_PIN1_PORT
115 stm_moder_set(AO_ADC_PIN1_PORT, AO_ADC_PIN1_PIN, STM_MODER_ANALOG);
117 #ifdef AO_ADC_PIN2_PORT
118 stm_moder_set(AO_ADC_PIN2_PORT, AO_ADC_PIN2_PIN, STM_MODER_ANALOG);
120 #ifdef AO_ADC_PIN3_PORT
121 stm_moder_set(AO_ADC_PIN3_PORT, AO_ADC_PIN3_PIN, STM_MODER_ANALOG);
123 #ifdef AO_ADC_PIN4_PORT
124 stm_moder_set(AO_ADC_PIN4_PORT, AO_ADC_PIN4_PIN, STM_MODER_ANALOG);
126 #ifdef AO_ADC_PIN5_PORT
127 stm_moder_set(AO_ADC_PIN5_PORT, AO_ADC_PIN5_PIN, STM_MODER_ANALOG);
129 #ifdef AO_ADC_PIN6_PORT
130 stm_moder_set(AO_ADC_PIN6_PORT, AO_ADC_PIN6_PIN, STM_MODER_ANALOG);
132 #ifdef AO_ADC_PIN7_PORT
133 stm_moder_set(AO_ADC_PIN7_PORT, AO_ADC_PIN7_PIN, STM_MODER_ANALOG);
135 #ifdef AO_ADC_PIN8_PORT
136 stm_moder_set(AO_ADC_PIN8_PORT, AO_ADC_PIN8_PIN, STM_MODER_ANALOG);
138 #ifdef AO_ADC_PIN9_PORT
139 stm_moder_set(AO_ADC_PIN9_PORT, AO_ADC_PIN9_PIN, STM_MODER_ANALOG);
141 #ifdef AO_ADC_PIN10_PORT
142 stm_moder_set(AO_ADC_PIN10_PORT, AO_ADC_PIN10_PIN, STM_MODER_ANALOG);
144 #ifdef AO_ADC_PIN11_PORT
145 stm_moder_set(AO_ADC_PIN11_PORT, AO_ADC_PIN11_PIN, STM_MODER_ANALOG);
147 #ifdef AO_ADC_PIN12_PORT
148 stm_moder_set(AO_ADC_PIN12_PORT, AO_ADC_PIN12_PIN, STM_MODER_ANALOG);
150 #ifdef AO_ADC_PIN13_PORT
151 stm_moder_set(AO_ADC_PIN13_PORT, AO_ADC_PIN13_PIN, STM_MODER_ANALOG);
153 #ifdef AO_ADC_PIN14_PORT
154 stm_moder_set(AO_ADC_PIN14_PORT, AO_ADC_PIN14_PIN, STM_MODER_ANALOG);
156 #ifdef AO_ADC_PIN15_PORT
157 stm_moder_set(AO_ADC_PIN15_PORT, AO_ADC_PIN15_PIN, STM_MODER_ANALOG);
159 #ifdef AO_ADC_PIN16_PORT
160 stm_moder_set(AO_ADC_PIN16_PORT, AO_ADC_PIN16_PIN, STM_MODER_ANALOG);
162 #ifdef AO_ADC_PIN17_PORT
163 stm_moder_set(AO_ADC_PIN17_PORT, AO_ADC_PIN17_PIN, STM_MODER_ANALOG);
165 #ifdef AO_ADC_PIN18_PORT
166 stm_moder_set(AO_ADC_PIN18_PORT, AO_ADC_PIN18_PIN, STM_MODER_ANALOG);
168 #ifdef AO_ADC_PIN19_PORT
169 stm_moder_set(AO_ADC_PIN19_PORT, AO_ADC_PIN19_PIN, STM_MODER_ANALOG);
171 #ifdef AO_ADC_PIN20_PORT
172 stm_moder_set(AO_ADC_PIN20_PORT, AO_ADC_PIN20_PIN, STM_MODER_ANALOG);
174 #ifdef AO_ADC_PIN21_PORT
175 stm_moder_set(AO_ADC_PIN21_PORT, AO_ADC_PIN21_PIN, STM_MODER_ANALOG);
177 #ifdef AO_ADC_PIN22_PORT
178 stm_moder_set(AO_ADC_PIN22_PORT, AO_ADC_PIN22_PIN, STM_MODER_ANALOG);
180 #ifdef AO_ADC_PIN23_PORT
181 stm_moder_set(AO_ADC_PIN23_PORT, AO_ADC_PIN23_PIN, STM_MODER_ANALOG);
183 #ifdef AO_ADC_PIN24_PORT
184 #error "Too many ADC ports"
187 stm_rcc.apb2enr |= (1 << STM_RCC_APB2ENR_ADC1EN);
189 /* Turn off ADC during configuration */
192 stm_adc.cr1 = ((0 << STM_ADC_CR1_OVRIE ) |
193 (STM_ADC_CR1_RES_12 << STM_ADC_CR1_RES ) |
194 (0 << STM_ADC_CR1_AWDEN ) |
195 (0 << STM_ADC_CR1_JAWDEN ) |
196 (0 << STM_ADC_CR1_PDI ) |
197 (0 << STM_ADC_CR1_PDD ) |
198 (0 << STM_ADC_CR1_DISCNUM ) |
199 (0 << STM_ADC_CR1_JDISCEN ) |
200 (0 << STM_ADC_CR1_DISCEN ) |
201 (0 << STM_ADC_CR1_JAUTO ) |
202 (0 << STM_ADC_CR1_AWDSGL ) |
203 (1 << STM_ADC_CR1_SCAN ) |
204 (0 << STM_ADC_CR1_JEOCIE ) |
205 (0 << STM_ADC_CR1_AWDIE ) |
206 (0 << STM_ADC_CR1_EOCIE ) |
207 (0 << STM_ADC_CR1_AWDCH ));
209 /* 384 cycle sample time for everyone */
210 stm_adc.smpr1 = 0x3ffff;
211 stm_adc.smpr2 = 0x3fffffff;
212 stm_adc.smpr3 = 0x3fffffff;
214 stm_adc.sqr1 = ((AO_NUM_ADC - 1) << 20);
220 stm_adc.sqr5 |= (AO_ADC_SQ1 << 0);
223 stm_adc.sqr5 |= (AO_ADC_SQ2 << 5);
226 stm_adc.sqr5 |= (AO_ADC_SQ3 << 10);
229 stm_adc.sqr5 |= (AO_ADC_SQ4 << 15);
232 stm_adc.sqr5 |= (AO_ADC_SQ5 << 20);
235 stm_adc.sqr5 |= (AO_ADC_SQ6 << 25);
238 stm_adc.sqr4 |= (AO_ADC_SQ7 << 0);
241 stm_adc.sqr4 |= (AO_ADC_SQ8 << 5);
244 stm_adc.sqr4 |= (AO_ADC_SQ9 << 10);
247 stm_adc.sqr4 |= (AO_ADC_SQ10 << 15);
250 stm_adc.sqr4 |= (AO_ADC_SQ11 << 20);
253 stm_adc.sqr4 |= (AO_ADC_SQ12 << 25);
256 stm_adc.sqr3 |= (AO_ADC_SQ13 << 0);
259 stm_adc.sqr3 |= (AO_ADC_SQ14 << 5);
262 stm_adc.sqr3 |= (AO_ADC_SQ15 << 10);
265 stm_adc.sqr3 |= (AO_ADC_SQ16 << 15);
268 stm_adc.sqr3 |= (AO_ADC_SQ17 << 20);
271 stm_adc.sqr3 |= (AO_ADC_SQ18 << 25);
274 #error "need to finish stm_adc.sqr settings"
278 stm_adc.cr2 = AO_ADC_CR2_VAL;
280 /* Wait for ADC to be ready */
281 while (!(stm_adc.sr & (1 << STM_ADC_SR_ADONS)))
285 #error Please define HAS_ADC_TEMP
288 stm_adc.ccr = ((1 << STM_ADC_CCR_TSVREFE));
292 /* Clear any stale status bits */
295 ao_dma_alloc(STM_DMA_INDEX(STM_DMA_CHANNEL_ADC1));
297 ao_cmd_register(&ao_adc_cmds[0]);