2 * File: stlink-common.h
3 * Bulk import from stlink-hw.h
5 * This should contain all the common top level stlink interfaces, regardless
6 * of how the backend does the work....
9 #ifndef STLINK_COMMON_H
10 #define STLINK_COMMON_H
18 // Max data transfer size.
19 // 6kB = max mem32_read block, 8kB sram
20 //#define Q_BUF_LEN 96
21 #define Q_BUF_LEN (1024 * 100)
23 // st-link vendor cmd's
24 #define USB_ST_VID 0x0483
25 #define USB_STLINK_PID 0x3744
26 #define USB_STLINK_32L_PID 0x3748
27 #define USB_STLINK_NUCLEO_PID 0x374b
29 // STLINK_DEBUG_RESETSYS, etc:
30 #define STLINK_OK 0x80
31 #define STLINK_FALSE 0x81
32 #define STLINK_CORE_RUNNING 0x80
33 #define STLINK_CORE_HALTED 0x81
34 #define STLINK_CORE_STAT_UNKNOWN -1
36 #define STLINK_GET_VERSION 0xf1
37 #define STLINK_GET_CURRENT_MODE 0xf5
38 #define STLINK_GET_TARGET_VOLTAGE 0xF7
40 #define STLINK_DEBUG_COMMAND 0xF2
41 #define STLINK_DFU_COMMAND 0xF3
42 #define STLINK_DFU_EXIT 0x07
43 // enter dfu could be 0x08?
45 // STLINK_GET_CURRENT_MODE
46 #define STLINK_DEV_DFU_MODE 0x00
47 #define STLINK_DEV_MASS_MODE 0x01
48 #define STLINK_DEV_DEBUG_MODE 0x02
49 #define STLINK_DEV_UNKNOWN_MODE -1
52 #define STLINK_DEBUG_ENTER 0x20
53 #define STLINK_DEBUG_EXIT 0x21
54 #define STLINK_DEBUG_READCOREID 0x22
55 #define STLINK_DEBUG_GETSTATUS 0x01
56 #define STLINK_DEBUG_FORCEDEBUG 0x02
57 #define STLINK_DEBUG_RESETSYS 0x03
58 #define STLINK_DEBUG_READALLREGS 0x04
59 #define STLINK_DEBUG_READREG 0x05
60 #define STLINK_DEBUG_WRITEREG 0x06
61 #define STLINK_DEBUG_READMEM_32BIT 0x07
62 #define STLINK_DEBUG_WRITEMEM_32BIT 0x08
63 #define STLINK_DEBUG_RUNCORE 0x09
64 #define STLINK_DEBUG_STEPCORE 0x0a
65 #define STLINK_DEBUG_SETFP 0x0b
66 #define STLINK_DEBUG_WRITEMEM_8BIT 0x0d
67 #define STLINK_DEBUG_CLEARFP 0x0e
68 #define STLINK_DEBUG_WRITEDEBUGREG 0x0f
69 #define STLINK_DEBUG_ENTER_SWD 0xa3
70 #define STLINK_DEBUG_ENTER_JTAG 0x00
72 // TODO - possible poor names...
73 #define STLINK_SWD_ENTER 0x30
74 #define STLINK_SWD_READCOREID 0x32 // TBD
75 #define STLINK_JTAG_WRITEDEBUG_32BIT 0x35
76 #define STLINK_JTAG_READDEBUG_32BIT 0x36
77 #define STLINK_JTAG_DRIVE_NRST 0x3c
78 #define STLINK_JTAG_DRIVE_NRST 0x3c
80 // cortex m3 technical reference manual
81 #define CM3_REG_CPUID 0xE000ED00
82 #define CM3_REG_FP_CTRL 0xE0002000
83 #define CM3_REG_FP_COMP0 0xE0002008
86 // TODO clean this up...
87 #define STM32VL_CORE_ID 0x1ba01477
88 #define STM32L_CORE_ID 0x2ba01477
89 #define STM32F3_CORE_ID 0x2ba01477
90 #define STM32F4_CORE_ID 0x2ba01477
91 #define STM32F0_CORE_ID 0xbb11477
92 #define CORE_M3_R1 0x1BA00477
93 #define CORE_M3_R2 0x4BA00477
94 #define CORE_M4_R0 0x2BA01477
97 * Chip IDs are explained in the appropriate programming manual for the
98 * DBGMCU_IDCODE register (0xE0042000)
100 // stm32 chipids, only lower 12 bits..
101 #define STM32_CHIPID_F1_MEDIUM 0x410
102 #define STM32_CHIPID_F2 0x411
103 #define STM32_CHIPID_F1_LOW 0x412
104 #define STM32_CHIPID_F3 0x422
105 #define STM32_CHIPID_F37x 0x432
106 #define STM32_CHIPID_F4 0x413
107 #define STM32_CHIPID_F4_HD 0x419
108 #define STM32_CHIPID_F4_LP 0x423
109 #define STM32_CHIPID_F1_HIGH 0x414
110 #define STM32_CHIPID_L1_MEDIUM 0x416
111 #define STM32_CHIPID_L1_MEDIUM_PLUS 0x427
113 * 0x436 is actually assigned to some L1 chips that are called "Medium-Plus"
114 * and some that are called "High". 0x427 is assigned to the other "Medium-
115 * plus" chips. To make it a bit simpler we just call 427 MEDIUM_PLUS and
118 #define STM32_CHIPID_L1_HIGH 0x436
119 #define STM32_CHIPID_F1_CONN 0x418
120 #define STM32_CHIPID_F1_VL_MEDIUM 0x420
121 #define STM32_CHIPID_F1_VL_HIGH 0x428
122 #define STM32_CHIPID_F1_XL 0x430
123 #define STM32_CHIPID_F0 0x440
124 #define STM32_CHIPID_F0_SMALL 0x444
126 // Constant STM32 memory map figures
127 #define STM32_FLASH_BASE 0x08000000
128 #define STM32_SRAM_BASE 0x20000000
130 /* Cortex™-M3 Technical Reference Manual */
131 /* Debug Halting Control and Status Register */
132 #define DHCSR 0xe000edf0
133 #define DCRSR 0xe000edf4
134 #define DCRDR 0xe000edf8
135 #define DBGKEY 0xa05f0000
137 /* Enough space to hold both a V2 command or a V1 command packaged as generic scsi*/
140 typedef struct chip_params_ {
143 uint32_t flash_size_reg;
144 uint32_t flash_pagesize;
146 uint32_t bootrom_base, bootrom_size;
150 // These maps are from a combination of the Programming Manuals, and
151 // also the Reference manuals. (flash size reg is normally in ref man)
152 static const chip_params_t devices[] = {
154 .chip_id = STM32_CHIPID_F1_MEDIUM,
155 .description = "F1 Medium-density device",
156 .flash_size_reg = 0x1ffff7e0,
157 .flash_pagesize = 0x400,
159 .bootrom_base = 0x1ffff000,
160 .bootrom_size = 0x800
163 .chip_id = STM32_CHIPID_F2,
164 .description = "F2 device",
165 .flash_size_reg = 0x1fff7a22, /* As in RM0033 Rev 5*/
166 .flash_pagesize = 0x20000,
167 .sram_size = 0x20000,
168 .bootrom_base = 0x1fff0000,
169 .bootrom_size = 0x7800
172 .chip_id = STM32_CHIPID_F1_LOW,
173 .description = "F1 Low-density device",
174 .flash_size_reg = 0x1ffff7e0,
175 .flash_pagesize = 0x400,
177 .bootrom_base = 0x1ffff000,
178 .bootrom_size = 0x800
181 .chip_id = STM32_CHIPID_F4,
182 .description = "F4 device",
183 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
184 .flash_pagesize = 0x4000,
185 .sram_size = 0x30000,
186 .bootrom_base = 0x1fff0000,
187 .bootrom_size = 0x7800
190 .chip_id = STM32_CHIPID_F4_HD,
191 .description = "F42x and F43x device",
192 .flash_size_reg = 0x1FFF7A22, /* As in rm0090 since Rev 2*/
193 .flash_pagesize = 0x4000,
194 .sram_size = 0x30000,
195 .bootrom_base = 0x1fff0000,
196 .bootrom_size = 0x7800
199 .chip_id = STM32_CHIPID_F4_LP,
200 .description = "F4 device (low power)",
201 .flash_size_reg = 0x1FFF7A22,
202 .flash_pagesize = 0x4000,
203 .sram_size = 0x10000,
204 .bootrom_base = 0x1fff0000,
205 .bootrom_size = 0x7800
208 .chip_id = STM32_CHIPID_F1_HIGH,
209 .description = "F1 High-density device",
210 .flash_size_reg = 0x1ffff7e0,
211 .flash_pagesize = 0x800,
212 .sram_size = 0x10000,
213 .bootrom_base = 0x1ffff000,
214 .bootrom_size = 0x800
217 // This ignores the EEPROM! (and uses the page erase size,
218 // not the sector write protection...)
219 .chip_id = STM32_CHIPID_L1_MEDIUM,
220 .description = "L1 Med-density device",
221 .flash_size_reg = 0x1ff8004c,
222 .flash_pagesize = 0x100,
224 .bootrom_base = 0x1ff00000,
225 .bootrom_size = 0x1000
228 .chip_id = STM32_CHIPID_L1_MEDIUM_PLUS,
229 .description = "L1 Medium-Plus-density device",
230 .flash_size_reg = 0x1ff800cc,
231 .flash_pagesize = 0x100,
232 .sram_size = 0x8000,/*Not completely clear if there are some with 48K*/
233 .bootrom_base = 0x1ff00000,
234 .bootrom_size = 0x1000
237 .chip_id = STM32_CHIPID_L1_HIGH,
238 .description = "L1 High-density device",
239 .flash_size_reg = 0x1ff800cc,
240 .flash_pagesize = 0x100,
241 .sram_size = 0xC000, /*Not completely clear if there are some with 32K*/
242 .bootrom_base = 0x1ff00000,
243 .bootrom_size = 0x1000
247 .chip_id = STM32_CHIPID_F1_CONN,
248 .description = "F1 Connectivity line device",
249 .flash_size_reg = 0x1ffff7e0,
250 .flash_pagesize = 0x800,
251 .sram_size = 0x10000,
252 .bootrom_base = 0x1fffb000,
253 .bootrom_size = 0x4800
256 .chip_id = STM32_CHIPID_F1_VL_MEDIUM,
257 .description = "F1 Medium-density Value Line device",
258 .flash_size_reg = 0x1ffff7e0,
259 .flash_pagesize = 0x400,
261 .bootrom_base = 0x1ffff000,
262 .bootrom_size = 0x800
265 // This is STK32F303VCT6 device from STM32 F3 Discovery board.
266 // Support based on DM00043574.pdf (RM0316) document.
267 .chip_id = STM32_CHIPID_F3,
268 .description = "F3 device",
269 .flash_size_reg = 0x1ffff7cc,
270 .flash_pagesize = 0x800,
272 .bootrom_base = 0x1ffff000,
273 .bootrom_size = 0x800
276 // This is STK32F373VCT6 device from STM32 F373 eval board
277 // Support based on 303 above (37x and 30x have same memory map)
278 .chip_id = STM32_CHIPID_F37x,
279 .description = "F3 device",
280 .flash_size_reg = 0x1ffff7cc,
281 .flash_pagesize = 0x800,
283 .bootrom_base = 0x1ffff000,
284 .bootrom_size = 0x800
287 .chip_id = STM32_CHIPID_F1_VL_HIGH,
288 .description = "F1 High-density value line device",
289 .flash_size_reg = 0x1ffff7e0,
290 .flash_pagesize = 0x800,
292 .bootrom_base = 0x1ffff000,
293 .bootrom_size = 0x800
296 .chip_id = STM32_CHIPID_F1_XL,
297 .description = "F1 XL-density device",
298 .flash_size_reg = 0x1ffff7e0,
299 .flash_pagesize = 0x800,
300 .sram_size = 0x18000,
301 .bootrom_base = 0x1fffe000,
302 .bootrom_size = 0x1800
305 //Use this as an example for mapping future chips:
306 //RM0091 document was used to find these paramaters
307 .chip_id = STM32_CHIPID_F0,
308 .description = "F0 device",
309 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
310 .flash_pagesize = 0x400, // Page sizes listed in Table 4
311 .sram_size = 0x2000, // "SRAM" byte size in hex from Table 2
312 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
313 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
316 //Use this as an example for mapping future chips:
317 //RM0091 document was used to find these paramaters
318 .chip_id = STM32_CHIPID_F0_SMALL,
319 .description = "F0 small device",
320 .flash_size_reg = 0x1ffff7cc, // "Flash size data register" (pg735)
321 .flash_pagesize = 0x400, // Page sizes listed in Table 4
322 .sram_size = 0x1000, // "SRAM" byte size in hex from Table 2
323 .bootrom_base = 0x1fffec00, // "System memory" starting address from Table 2
324 .bootrom_size = 0xC00 // "System memory" byte size in hex from Table 2
344 typedef uint32_t stm32_addr_t;
346 typedef struct _cortex_m3_cpuid_ {
347 uint16_t implementer_id;
353 typedef struct stlink_version_ {
361 typedef struct flash_loader {
362 stm32_addr_t loader_addr; /* loader sram adddr */
363 stm32_addr_t buf_addr; /* buffer sram address */
366 enum transport_type {
367 TRANSPORT_TYPE_ZERO = 0,
368 TRANSPORT_TYPE_LIBSG,
369 TRANSPORT_TYPE_LIBUSB,
370 TRANSPORT_TYPE_INVALID
373 typedef struct _stlink stlink_t;
375 typedef struct _stlink_backend {
376 void (*close) (stlink_t * sl);
377 void (*exit_debug_mode) (stlink_t * sl);
378 void (*enter_swd_mode) (stlink_t * sl);
379 void (*enter_jtag_mode) (stlink_t * stl);
380 void (*exit_dfu_mode) (stlink_t * stl);
381 void (*core_id) (stlink_t * stl);
382 void (*reset) (stlink_t * stl);
383 void (*jtag_reset) (stlink_t * stl, int value);
384 void (*run) (stlink_t * stl);
385 void (*status) (stlink_t * stl);
386 void (*version) (stlink_t *sl);
387 uint32_t (*read_debug32) (stlink_t *sl, uint32_t addr);
388 void (*read_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
389 void (*write_debug32) (stlink_t *sl, uint32_t addr, uint32_t data);
390 void (*write_mem32) (stlink_t *sl, uint32_t addr, uint16_t len);
391 void (*write_mem8) (stlink_t *sl, uint32_t addr, uint16_t len);
392 void (*read_all_regs) (stlink_t *sl, reg * regp);
393 void (*read_reg) (stlink_t *sl, int r_idx, reg * regp);
394 void (*read_all_unsupported_regs) (stlink_t *sl, reg *regp);
395 void (*read_unsupported_reg) (stlink_t *sl, int r_idx, reg *regp);
396 void (*write_unsupported_reg) (stlink_t *sl, uint32_t value, int idx, reg *regp);
397 void (*write_reg) (stlink_t *sl, uint32_t reg, int idx);
398 void (*step) (stlink_t * stl);
399 int (*current_mode) (stlink_t * stl);
400 void (*force_debug) (stlink_t *sl);
401 int32_t (*target_voltage) (stlink_t *sl);
405 struct _stlink_backend *backend;
408 // Room for the command header
409 unsigned char c_buf[C_BUF_LEN];
410 // Data transferred from or to device
411 unsigned char q_buf[Q_BUF_LEN];
414 // transport layer verboseness: 0 for no debug info, 10 for lots
420 #define STM32_FLASH_PGSZ 1024
421 #define STM32L_FLASH_PGSZ 256
423 #define STM32F4_FLASH_PGSZ 16384
424 #define STM32F4_FLASH_SIZE (128 * 1024 * 8)
426 stm32_addr_t flash_base;
431 #define STM32_SRAM_SIZE (8 * 1024)
432 #define STM32L_SRAM_SIZE (16 * 1024)
433 stm32_addr_t sram_base;
437 stm32_addr_t sys_base;
440 struct stlink_version_ version;
443 //stlink_t* stlink_quirk_open(const char *dev_name, const int verbose);
445 // delegated functions...
446 void stlink_enter_swd_mode(stlink_t *sl);
447 void stlink_enter_jtag_mode(stlink_t *sl);
448 void stlink_exit_debug_mode(stlink_t *sl);
449 void stlink_exit_dfu_mode(stlink_t *sl);
450 void stlink_close(stlink_t *sl);
451 uint32_t stlink_core_id(stlink_t *sl);
452 void stlink_reset(stlink_t *sl);
453 void stlink_jtag_reset(stlink_t *sl, int value);
454 void stlink_run(stlink_t *sl);
455 void stlink_status(stlink_t *sl);
456 void stlink_version(stlink_t *sl);
457 uint32_t stlink_read_debug32(stlink_t *sl, uint32_t addr);
458 void stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
459 void stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data);
460 void stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len);
461 void stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len);
462 void stlink_read_all_regs(stlink_t *sl, reg *regp);
463 void stlink_read_all_unsupported_regs(stlink_t *sl, reg *regp);
464 void stlink_read_reg(stlink_t *sl, int r_idx, reg *regp);
465 void stlink_read_unsupported_reg(stlink_t *sl, int r_idx, reg *regp);
466 void stlink_write_unsupported_reg(stlink_t *sl, uint32_t value, int r_idx, reg *regp);
467 void stlink_write_reg(stlink_t *sl, uint32_t reg, int idx);
468 void stlink_step(stlink_t *sl);
469 int stlink_current_mode(stlink_t *sl);
470 void stlink_force_debug(stlink_t *sl);
471 int stlink_target_voltage(stlink_t *sl);
475 int stlink_erase_flash_mass(stlink_t* sl);
476 int stlink_write_flash(stlink_t* sl, stm32_addr_t address, uint8_t* data, uint32_t length);
477 int stlink_fwrite_flash(stlink_t *sl, const char* path, stm32_addr_t addr);
478 int stlink_fwrite_sram(stlink_t *sl, const char* path, stm32_addr_t addr);
479 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, uint32_t length);
482 uint32_t stlink_chip_id(stlink_t *sl);
483 void stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid);
485 // privates, publics, the rest....
486 // TODO sort what is private, and what is not
487 int stlink_erase_flash_page(stlink_t* sl, stm32_addr_t flashaddr);
488 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr);
489 uint16_t read_uint16(const unsigned char *c, const int pt);
490 void stlink_core_stat(stlink_t *sl);
491 void stlink_print_data(stlink_t *sl);
492 unsigned int is_bigendian(void);
493 uint32_t read_uint32(const unsigned char *c, const int pt);
494 void write_uint32(unsigned char* buf, uint32_t ui);
495 void write_uint16(unsigned char* buf, uint16_t ui);
496 unsigned int is_core_halted(stlink_t *sl);
497 int write_buffer_to_sram(stlink_t *sl, flash_loader_t* fl, const uint8_t* buf, size_t size);
498 int write_loader_to_sram(stlink_t *sl, stm32_addr_t* addr, size_t* size);
499 int stlink_fread(stlink_t* sl, const char* path, stm32_addr_t addr, size_t size);
500 int run_flash_loader(stlink_t *sl, flash_loader_t* fl, stm32_addr_t target, const uint8_t* buf, size_t size);
501 int stlink_load_device_params(stlink_t *sl);
505 #include "stlink-sg.h"
506 #include "stlink-usb.h"
514 #endif /* STLINK_COMMON_H */