2 * Copyright © 2013 Keith Packard <keithp@keithp.com>
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
24 typedef volatile uint32_t vuint32_t;
25 typedef volatile uint16_t vuint16_t;
26 typedef volatile uint8_t vuint8_t;
27 typedef volatile void * vvoid_t;
60 vuint32_t pio1_0; /* 0x60 */
70 vuint32_t pio1_8; /* 0x80 */
80 vuint32_t pio1_16; /* 0xa0 */
90 vuint32_t pio1_24; /* 0xc0 */
101 extern struct lpc_ioconf lpc_ioconf;
102 #define lpc_ioconf (*(struct lpc_ioconf *) 0x40044000)
104 #define LPC_IOCONF_FUNC 0
107 #define LPC_IOCONF_FUNC_RESET 0
108 #define LPC_IOCONF_FUNC_PIO0_0 1
111 #define LPC_IOCONF_FUNC_PIO0_1 0
112 #define LPC_IOCONF_FUNC_CLKOUT 1
113 #define LPC_IOCONF_FUNC_PIO0_1_CT32B0_MAT2 2
114 #define LPC_IOCONF_FUNC_USB_FTOGGLE 3
117 #define LPC_IOCONF_FUNC_PIO0_2 0
118 #define LPC_IOCONF_FUNC_SSEL0 1
119 #define LPC_IOCONF_FUNC_PIO0_2_CT16B0_CAP0 2
122 #define LPC_IOCONF_FUNC_PIO0_3 0
123 #define LPC_IOCONF_FUNC_USB_VBUS 1
126 #define LPC_IOCONF_FUNC_PIO0_4 0
127 #define LPC_IOCONF_FUNC_I2C_SCL 1
130 #define LPC_IOCONF_FUNC_PIO0_5 0
131 #define LPC_IOCONF_FUNC_I2C_SDA 1
134 #define LPC_IOCONF_FUNC_PIO0_6 0
135 #define LPC_IOCONF_FUNC_USB_CONNECT 1
136 #define LPC_IOCONF_FUNC_PIO0_6_SCK0 2
139 #define LPC_IOCONF_FUNC_PIO0_7 0
140 #define LPC_IOCONF_FUNC_CTS 1
143 #define LPC_IOCONF_FUNC_PIO0_8 0
144 #define LPC_IOCONF_FUNC_MISO0 1
145 #define LPC_IOCONF_FUNC_PIO0_8_CT16B0_MAT0 2
148 #define LPC_IOCONF_FUNC_PIO0_9 0
149 #define LPC_IOCONF_FUNC_MOSI0 1
150 #define LPC_IOCONF_FUNC_PIO0_9_CT16B0_MAT1 2
153 #define LPC_IOCONF_FUNC_SWCLK 0
154 #define LPC_IOCONF_FUNC_PIO0_10 1
155 #define LPC_IOCONF_FUNC_PIO0_10_SCK0 2
156 #define LPC_IOCONF_FUNC_PIO0_10_CT16B0_MAT2 3
159 #define LPC_IOCONF_FUNC_TDI 0
160 #define LPC_IOCONF_FUNC_PIO0_11 1
161 #define LPC_IOCONF_FUNC_AD0 2
162 #define LPC_IOCONF_FUNC_PIO0_11_CT32B0_MAT3 3
165 #define LPC_IOCONF_FUNC_TMS 0
166 #define LPC_IOCONF_FUNC_PIO0_12 1
167 #define LPC_IOCONF_FUNC_AD1 2
168 #define LPC_IOCONF_FUNC_PIO0_12_CT32B1_CAP0 3
171 #define LPC_IOCONF_FUNC_TD0 0
172 #define LPC_IOCONF_FUNC_PIO0_13 1
173 #define LPC_IOCONF_FUNC_AD2 2
174 #define LPC_IOCONF_FUNC_PIO0_13_CT32B1_MAT0 3
177 #define LPC_IOCONF_FUNC_TRST 0
178 #define LPC_IOCONF_FUNC_PIO0_14 1
179 #define LPC_IOCONF_FUNC_AD3 2
180 #define LPC_IOCONF_FUNC_PIO0_14_CT32B1_MAT1 3
183 #define LPC_IOCONF_FUNC_SWDIO 0
184 #define LPC_IOCONF_FUNC_PIO0_15 1
185 #define LPC_IOCONF_FUNC_AD4 2
186 #define LPC_IOCONF_FUNC_PIO0_15_CT32B1_MAT2 3
189 #define LPC_IOCONF_FUNC_PIO0_16 0
190 #define LPC_IOCONF_FUNC_AD5 1
191 #define LPC_IOCONF_FUNC_PIO0_16_CT32B1_MAT3 2
194 #define LPC_IOCONF_FUNC_PIO0_17 0
195 #define LPC_IOCONF_FUNC_RTS 1
196 #define LPC_IOCONF_FUNC_CT32B0_CAP0 2
197 #define LPC_IOCONF_FUNC_SCLK 3
200 #define LPC_IOCONF_FUNC_PIO0_18 0
201 #define LPC_IOCONF_FUNC_PIO0_18_RXD 1
202 #define LPC_IOCONF_FUNC_PIO0_18_CT32B0_MAT0 2
205 #define LPC_IOCONF_FUNC_PIO0_19 0
206 #define LPC_IOCONF_FUNC_PIO0_19_TXD 1
207 #define LPC_IOCONF_FUNC_PIO0_19_CT32B0_MAT1 2
210 #define LPC_IOCONF_FUNC_PIO0_20 0
211 #define LPC_IOCONF_FUNC_PIO0_20_CT16B1_CAP0 1
214 #define LPC_IOCONF_FUNC_PIO0_21 0
215 #define LPC_IOCONF_FUNC_PIO0_21_CT16B1_MAT0 1
216 #define LPC_IOCONF_FUNC_PIO0_21_MOSI1 2
219 #define LPC_IOCONF_FUNC_PIO0_22 0
220 #define LPC_IOCONF_FUNC_AD6 1
221 #define LPC_IOCONF_FUNC_PIO0_22_CT16B1_MAT1 2
222 #define LPC_IOCONF_FUNC_PIO0_22_MISO1 3
225 #define LPC_IOCONF_FUNC_PIO0_23 0
226 #define LPC_IOCONF_FUNC_AD7 1
229 #define LPC_IOCONF_FUNC_PIO1_0 0
230 #define LPC_IOCONF_FUNC_PIO1_0_CT32B1_MAT1 1
233 #define LPC_IOCONF_FUNC_PIO1_1 0
234 #define LPC_IOCONF_FUNC_PIO1_1_CT32B1_MAT1 1
237 #define LPC_IOCONF_FUNC_PIO1_2 0
238 #define LPC_IOCONF_FUNC_PIO1_2_CT32B1_MAT2 1
241 #define LPC_IOCONF_FUNC_PIO1_3 0
242 #define LPC_IOCONF_FUNC_PIO1_3_CT32B1_MAT3 1
245 #define LPC_IOCONF_FUNC_PIO1_4 0
246 #define LPC_IOCONF_FUNC_PIO1_4_CT32B1_CAP0 1
249 #define LPC_IOCONF_FUNC_PIO1_5 0
250 #define LPC_IOCONF_FUNC_PIO1_5_CT32B1_CAP1 1
253 #define LPC_IOCONF_FUNC_PIO1_6 0
256 #define LPC_IOCONF_FUNC_PIO1_7 0
259 #define LPC_IOCONF_FUNC_PIO1_8 0
262 #define LPC_IOCONF_FUNC_PIO1_9 0
265 #define LPC_IOCONF_FUNC_PIO1_10 0
268 #define LPC_IOCONF_FUNC_PIO1_11 0
271 #define LPC_IOCONF_FUNC_PIO1_12 0
274 #define LPC_IOCONF_FUNC_PIO1_13 0
275 #define LPC_IOCONF_FUNC_DTR 1
276 #define LPC_IOCONF_FUNC_PIO1_13_CT16B0_MAT0 2
277 #define LPC_IOCONF_FUNC_PIO1_13_TXD 3
280 #define LPC_IOCONF_FUNC_PIO1_14 0
281 #define LPC_IOCONF_FUNC_DSR 1
282 #define LPC_IOCONF_FUNC_PIO1_14_CT16B0_MAT1 2
283 #define LPC_IOCONF_FUNC_PIO1_13_RXD 3
286 #define LPC_IOCONF_FUNC_PIO1_15 0
287 #define LPC_IOCONF_FUNC_DCD 1
288 #define LPC_IOCONF_FUNC_PIO1_15_CT16B0_MAT2 2
289 #define LPC_IOCONF_FUNC_PIO1_15_SCK1 3
292 #define LPC_IOCONF_FUNC_PIO1_16 0
293 #define LPC_IOCONF_FUNC_RI 1
294 #define LPC_IOCONF_FUNC_PIO1_16_CT16B0_CAP0 2
297 #define LPC_IOCONF_FUNC_PIO1_17 0
298 #define LPC_IOCONF_FUNC_PIO1_17_CT16B0_CAP1 1
299 #define LPC_IOCONF_FUNC_PIO1_17_RXD 2
302 #define LPC_IOCONF_FUNC_PIO1_18 0
303 #define LPC_IOCONF_FUNC_PIO1_18_CT16B1_CAP1 1
304 #define LPC_IOCONF_FUNC_PIO1_18_TXD 2
307 #define LPC_IOCONF_FUNC_PIO1_19 0
308 #define LPC_IOCONF_FUNC_DTR 1
309 #define LPC_IOCONF_FUNC_SSEL1 2
312 #define LPC_IOCONF_FUNC_PIO1_20 0
313 #define LPC_IOCONF_FUNC_DSR 1
314 #define LPC_IOCONF_FUNC_PIO1_20_SCK1 2
317 #define LPC_IOCONF_FUNC_PIO1_21 0
318 #define LPC_IOCONF_FUNC_DCD 1
319 #define LPC_IOCONF_FUNC_PIO1_21_MISO1 2
322 #define LPC_IOCONF_FUNC_PIO1_22 0
323 #define LPC_IOCONF_FUNC_RI 1
324 #define LPC_IOCONF_FUNC_PIO1_22_MOSI1 2
327 #define LPC_IOCONF_FUNC_PIO1_23 0
328 #define LPC_IOCONF_FUNC_PIO1_23_CT16B1_MAT1 1
329 #define LPC_IOCONF_FUNC_SSEL1 2
332 #define LPC_IOCONF_FUNC_PIO1_24 0
333 #define LPC_IOCONF_FUNC_PIO1_24_CT32B0_MAT0 1
336 #define LPC_IOCONF_FUNC_PIO1_25 0
337 #define LPC_IOCONF_FUNC_PIO1_25_CT32B0_MAT1 1
340 #define LPC_IOCONF_FUNC_PIO1_26 0
341 #define LPC_IOCONF_FUNC_PIO1_26_CT32B0_MAT2 1
342 #define LPC_IOCONF_FUNC_PIO1_26_RXD 2
345 #define LPC_IOCONF_FUNC_PIO1_27 0
346 #define LPC_IOCONF_FUNC_PIO1_27_CT32B0_MAT3 1
347 #define LPC_IOCONF_FUNC_PIO1_27_TXD 2
350 #define LPC_IOCONF_FUNC_PIO1_28 0
351 #define LPC_IOCONF_FUNC_PIO1_28_CT32B0_CAP0 1
352 #define LPC_IOCONF_FUNC_PIO1_28_SCLK 2
355 #define LPC_IOCONF_FUNC_PIO1_29 0
356 #define LPC_IOCONF_FUNC_PIO1_29_SCK0 1
357 #define LPC_IOCONF_FUNC_PIO1_29_CT32B0_CAP1 2
360 #define LPC_IOCONF_FUNC_PIO1_31 0
362 #define LPC_IOCONF_FUNC_MASK 0x7UL
364 #define ao_lpc_alternate(func) (((func) << LPC_IOCONF_FUNC) | \
365 (LPC_IOCONF_MODE_INACTIVE << LPC_IOCONF_MODE) | \
366 (0 << LPC_IOCONF_HYS) | \
367 (0 << LPC_IOCONF_INV) | \
368 (0 << LPC_IOCONF_OD) | \
371 #define LPC_IOCONF_MODE 3
372 #define LPC_IOCONF_MODE_INACTIVE 0
373 #define LPC_IOCONF_MODE_PULL_DOWN 1
374 #define LPC_IOCONF_MODE_PULL_UP 2
375 #define LPC_IOCONF_MODE_REPEATER 3
376 #define LPC_IOCONF_MODE_MASK 3UL
378 #define LPC_IOCONF_HYS 5
380 #define LPC_IOCONF_INV 6
381 #define LPC_IOCONF_ADMODE 7
382 #define LPC_IOCONF_FILTR 8
383 #define LPC_IOCONF_OD 10
386 vuint32_t sysmemremap; /* 0x00 */
387 vuint32_t presetctrl;
388 vuint32_t syspllctrl;
389 vuint32_t syspllstat;
391 vuint32_t usbpllctrl; /* 0x10 */
392 vuint32_t usbpllstat;
396 vuint32_t sysoscctrl; /* 0x20 */
397 vuint32_t wdtoscctrl;
401 vuint32_t sysrststat; /* 0x30 */
406 vuint32_t syspllclksel; /* 0x40 */
407 vuint32_t syspllclkuen;
408 vuint32_t usbpllclksel;
409 vuint32_t usbpllclkuen;
413 vuint32_t mainclksel; /* 0x70 */
414 vuint32_t mainclkuen;
415 vuint32_t sysahbclkdiv;
418 vuint32_t sysahbclkctrl; /* 0x80 */
421 uint32_t r90; /* 0x90 */
422 vuint32_t ssp0clkdiv;
423 vuint32_t uartclkdiv;
424 vuint32_t ssp1clkdiv;
428 vuint32_t usbclksel; /* 0xc0 */
435 vuint32_t clkoutsel; /* 0xe0 */
440 uint32_t rf0[4]; /* 0xf0 */
442 vuint32_t pioporcap0; /* 0x100 */
443 vuint32_t pioporcap1;
446 uint32_t r110[4]; /* 0x110 */
447 uint32_t r120[4]; /* 0x120 */
448 uint32_t r130[4]; /* 0x130 */
449 uint32_t r140[4]; /* 0x140 */
451 vuint32_t bodctrl; /* 0x150 */
455 uint32_t r160[4]; /* 0x160 */
457 vuint32_t irqlatency; /* 0x170 */
459 vuint32_t pintsel[8];
461 vuint32_t usbclkctrl; /* 0x198 */
464 uint32_t r1a0[6*4]; /* 0x1a0 */
466 uint32_t r200; /* 0x200 */
470 uint32_t r210; /* 0x210 */
474 uint32_t r220[4]; /* 0x220 */
476 vuint32_t pdsleepcfg; /* 0x230 */
477 vuint32_t pdawakecfg;
481 uint32_t r240[12 * 4]; /* 0x240 */
483 uint32_t r300[15 * 4]; /* 0x300 */
485 uint32_t r3f0; /* 0x3f0 */
489 extern struct lpc_scb lpc_scb;
490 #define lpc_scb (*(struct lpc_scb *) 0x40048000)
492 #define LPC_SCB_SYSMEMREMAP_MAP 0
493 # define LPC_SCB_SYSMEMREMAP_MAP_BOOT_LOADER 0
494 # define LPC_SCB_SYSMEMREMAP_MAP_RAM 1
495 # define LPC_SCB_SYSMEMREMAP_MAP_FLASH 2
497 #define LPC_SCB_PRESETCTRL_SSP0_RST_N 0
498 #define LPC_SCB_PRESETCTRL_I2C_RST_N 1
499 #define LPC_SCB_PRESETCTRL_SSP1_RST_N 2
501 #define LPC_SCB_SYSPLLCTRL_MSEL 0
502 #define LPC_SCB_SYSPLLCTRL_PSEL 5
503 #define LPC_SCB_SYSPLLCTRL_PSEL_1 0
504 #define LPC_SCB_SYSPLLCTRL_PSEL_2 1
505 #define LPC_SCB_SYSPLLCTRL_PSEL_4 2
506 #define LPC_SCB_SYSPLLCTRL_PSEL_8 3
507 #define LPC_SCB_SYSPLLCTRL_PSEL_MASK 3UL
509 #define LPC_SCB_SYSPLLSTAT_LOCK 0
511 #define LPC_SCB_USBPLLCTRL_MSEL 0
512 #define LPC_SCB_USBPLLCTRL_PSEL 5
513 #define LPC_SCB_USBPLLCTRL_PSEL_1 0
514 #define LPC_SCB_USBPLLCTRL_PSEL_2 1
515 #define LPC_SCB_USBPLLCTRL_PSEL_4 2
516 #define LPC_SCB_USBPLLCTRL_PSEL_8 3
517 #define LPC_SCB_USBPLLCTRL_PSEL_MASK 3UL
519 #define LPC_SCB_USBPLLSTAT_LOCK 0
521 #define LPC_SCB_SYSOSCCTRL_BYPASS 0
522 #define LPC_SCB_SYSOSCCTRL_FREQRANGE 1
523 #define LPC_SCB_SYSOSCCTRL_FREQRANGE_1_20 0
524 #define LPC_SCB_SYSOSCCTRL_FREQRANGE_15_25 1
526 #define LPC_SCB_WDTOSCCTRL_DIVSEL 0
527 #define LPC_SCB_WDTOSCCTRL_DIVSEL_MASK 0x1fUL
528 #define LPC_SCB_WDTOSCCTRL_FREQSEL 5
529 #define LPC_SCB_WDTOSCCTRL_FREQSEL_0_6 1
530 #define LPC_SCB_WDTOSCCTRL_FREQSEL_1_05 2
531 #define LPC_SCB_WDTOSCCTRL_FREQSEL_1_4 3
532 #define LPC_SCB_WDTOSCCTRL_FREQSEL_1_75 4
533 #define LPC_SCB_WDTOSCCTRL_FREQSEL_2_1 5
534 #define LPC_SCB_WDTOSCCTRL_FREQSEL_2_4 6
535 #define LPC_SCB_WDTOSCCTRL_FREQSEL_2_7 7
536 #define LPC_SCB_WDTOSCCTRL_FREQSEL_3_0 8
537 #define LPC_SCB_WDTOSCCTRL_FREQSEL_3_25 9
538 #define LPC_SCB_WDTOSCCTRL_FREQSEL_3_5 0x0a
539 #define LPC_SCB_WDTOSCCTRL_FREQSEL_3_75 0x0b
540 #define LPC_SCB_WDTOSCCTRL_FREQSEL_4_0 0x0c
541 #define LPC_SCB_WDTOSCCTRL_FREQSEL_4_2 0x0d
542 #define LPC_SCB_WDTOSCCTRL_FREQSEL_4_4 0x0e
543 #define LPC_SCB_WDTOSCCTRL_FREQSEL_4_6 0x0f
544 #define LPC_SCB_WDTOSCCTRL_FREQSEL_MASK 0x0fUL
546 #define LPC_SCB_SYSRSTSTAT_POR 0
547 #define LPC_SCB_SYSRSTSTAT_EXTRST 1
548 #define LPC_SCB_SYSRSTSTAT_WDT 2
549 #define LPC_SCB_SYSRSTSTAT_BOD 3
550 #define LPC_SCB_SYSRSTSTAT_SYSRST 4
552 #define LPC_SCB_SYSPLLCLKSEL_SEL 0
553 #define LPC_SCB_SYSPLLCLKSEL_SEL_IRC 0
554 #define LPC_SCB_SYSPLLCLKSEL_SEL_SYSOSC 1
555 #define LPC_SCB_SYSPLLCLKSEL_SEL_MASK 3UL
557 #define LPC_SCB_SYSPLLCLKUEN_ENA 0
559 #define LPC_SCB_USBPLLCLKSEL_SEL 0
560 #define LPC_SCB_USBPLLCLKSEL_SEL_IRC 0
561 #define LPC_SCB_USBPLLCLKSEL_SEL_SYSOSC 1
562 #define LPC_SCB_USBPLLCLKSEL_SEL_MASK 3UL
564 #define LPC_SCB_USBPLLCLKUEN_ENA 0
566 #define LPC_SCB_MAINCLKSEL_SEL 0
567 #define LPC_SCB_MAINCLKSEL_SEL_IRC 0
568 #define LPC_SCB_MAINCLKSEL_SEL_PLL_INPUT 1
569 #define LPC_SCB_MAINCLKSEL_SEL_WATCHDOG 2
570 #define LPC_SCB_MAINCLKSEL_SEL_PLL_OUTPUT 3
571 #define LPC_SCB_MAINCLKSEL_SEL_MASK 3UL
573 #define LPC_SCB_MAINCLKUEN_ENA 0
575 #define LPC_SCB_SYSAHBCLKDIV_DIV 0
577 #define LPC_SCB_SYSAHBCLKCTRL_SYS 0
578 #define LPC_SCB_SYSAHBCLKCTRL_ROM 1
579 #define LPC_SCB_SYSAHBCLKCTRL_RAM0 2
580 #define LPC_SCB_SYSAHBCLKCTRL_FLASHREG 3
581 #define LPC_SCB_SYSAHBCLKCTRL_FLASHARRAY 4
582 #define LPC_SCB_SYSAHBCLKCTRL_I2C 5
583 #define LPC_SCB_SYSAHBCLKCTRL_GPIO 6
584 #define LPC_SCB_SYSAHBCLKCTRL_CT16B0 7
585 #define LPC_SCB_SYSAHBCLKCTRL_CT16B1 8
586 #define LPC_SCB_SYSAHBCLKCTRL_CT32B0 9
587 #define LPC_SCB_SYSAHBCLKCTRL_CT32B1 10
588 #define LPC_SCB_SYSAHBCLKCTRL_SSP0 11
589 #define LPC_SCB_SYSAHBCLKCTRL_USART 12
590 #define LPC_SCB_SYSAHBCLKCTRL_ADC 13
591 #define LPC_SCB_SYSAHBCLKCTRL_USB 14
592 #define LPC_SCB_SYSAHBCLKCTRL_WWDT 15
593 #define LPC_SCB_SYSAHBCLKCTRL_IOCON 16
594 #define LPC_SCB_SYSAHBCLKCTRL_SSP1 18
595 #define LPC_SCB_SYSAHBCLKCTRL_PINT 19
596 #define LPC_SCB_SYSAHBCLKCTRL_GROUP0INT 23
597 #define LPC_SCB_SYSAHBCLKCTRL_GROUP1INT 24
598 #define LPC_SCB_SYSAHBCLKCTRL_RAM1 26
599 #define LPC_SCB_SYSAHBCLKCTRL_USBRAM 27
601 #define LPC_SCB_SSP0CLKDIV_
602 #define LPC_SCB_UARTCLKDIV_
603 #define LPC_SCB_SSP1CLKDIV_
605 #define LPC_SCB_USBCLKSEL_SEL 0
606 #define LPC_SCB_USBCLKSEL_SEL_USB_PLL 0
607 #define LPC_SCB_USBCLKSEL_SEL_MAIN_CLOCK 1
609 #define LPC_SCB_USBCLKUEN_ENA 0
610 #define LPC_SCB_USBCLKDIV_DIV 0
612 #define LPC_SCB_CLKOUTSEL_SEL 0
613 #define LPC_SCB_CLKOUTSEL_SEL_IRC 0
614 #define LPC_SCB_CLKOUTSEL_SEL_SYSOSC 1
615 #define LPC_SCB_CLKOUTSEL_SEL_LF 2
616 #define LPC_SCB_CLKOUTSEL_SEL_MAIN_CLOCK 3
618 #define LPC_SCB_CLKOUTUEN_ENA 0
620 #define LPC_SCB_BOD_BODRSTLEV 0
621 # define LPC_SCB_BOD_BODRSTLEV_1_46 0
622 # define LPC_SCB_BOD_BODRSTLEV_2_06 1
623 # define LPC_SCB_BOD_BODRSTLEV_2_35 2
624 # define LPC_SCB_BOD_BODRSTLEV_2_63 3
625 #define LPC_SCB_BOD_BODINTVAL 2
626 # define LPC_SCB_BOD_BODINTVAL_RESERVED 0
627 # define LPC_SCB_BOD_BODINTVAL_2_22 1
628 # define LPC_SCB_BOD_BODINTVAL_2_52 2
629 # define LPC_SCB_BOD_BODINTVAL_2_80 3
630 #define LPC_SCB_BOD_BODRSTENA 4
632 #define LPC_SCB_PDRUNCFG_IRCOUT_PD 0
633 #define LPC_SCB_PDRUNCFG_IRC_PD 1
634 #define LPC_SCB_PDRUNCFG_FLASH_PD 2
635 #define LPC_SCB_PDRUNCFG_BOD_PD 3
636 #define LPC_SCB_PDRUNCFG_ADC_PD 4
637 #define LPC_SCB_PDRUNCFG_SYSOSC_PD 5
638 #define LPC_SCB_PDRUNCFG_WDTOSC_PD 6
639 #define LPC_SCB_PDRUNCFG_SYSPLL_PD 7
640 #define LPC_SCB_PDRUNCFG_USBPLL_PD 8
641 #define LPC_SCB_PDRUNCFG_USBPAD_PD 10
644 uint32_t r0[4]; /* 0x0 */
646 vuint32_t flashcfg; /* 0x10 */
649 extern struct lpc_flash lpc_flash;
650 #define lpc_flash (*(struct lpc_flash *) 0x4003c000)
652 struct lpc_gpio_pin {
653 vuint32_t isel; /* 0x00 */
658 vuint32_t ienf; /* 0x10 */
663 vuint32_t fall; /* 0x20 */
667 extern struct lpc_gpio_pin lpc_gpio_pin;
668 #define lpc_gpio_pin (*(struct lpc_gpio_pin *) 0x4004c000)
670 struct lpc_gpio_group0 {
673 extern struct lpc_gpio_group0 lpc_gpio_group0;
675 struct lpc_gpio_group1 {
678 extern struct lpc_gpio_group1 lpc_gpio_group1;
681 vuint8_t byte[0x40]; /* 0x0000 */
683 uint8_t r0030[0x1000 - 0x40];
685 vuint32_t word[0x40]; /* 0x1000 */
687 uint8_t r1100[0x2000 - 0x1100];
689 vuint32_t dir[2]; /* 0x2000 */
691 uint8_t r2008[0x2080 - 0x2008];
693 vuint32_t mask[2]; /* 0x2080 */
695 uint8_t r2088[0x2100 - 0x2088];
697 vuint32_t pin[2]; /* 0x2100 */
699 uint8_t r2108[0x2200 - 0x2108];
701 vuint32_t set[2]; /* 0x2200 */
703 uint8_t r2208[0x2280 - 0x2208];
705 vuint32_t clr[2]; /* 0x2280 */
707 uint8_t r2288[0x2300 - 0x2288];
709 vuint32_t not[2]; /* 0x2300 */
712 extern struct lpc_gpio lpc_gpio;
713 #define lpc_gpio (*(struct lpc_gpio *) 0x50000000)
716 uint8_t r0000[0x10]; /* 0x0000 */
718 vuint32_t csr; /* 0x0010 */
724 extern struct lpc_systick lpc_systick;
725 #define lpc_systick (*(struct lpc_systick *) 0xe000e000)
727 #define LPC_SYSTICK_CSR_ENABLE 0
728 #define LPC_SYSTICK_CSR_TICKINT 1
729 #define LPC_SYSTICK_CSR_CLKSOURCE 2
730 #define LPC_SYSTICK_CSR_CLKSOURCE_CPU_OVER_2 0
731 #define LPC_SYSTICK_CSR_CLKSOURCE_CPU 1
732 #define LPC_SYSTICK_CSR_COUNTFLAG 16
735 vuint32_t rbr_thr; /* 0x0000 */
740 vuint32_t mcr; /* 0x0010 */
745 vuint32_t acr; /* 0x0020 */
750 vuint32_t ter; /* 0x0030 */
753 vuint32_t hden; /* 0x0040 */
758 vuint32_t rs485addrmatch; /* 0x0050 */
763 extern struct lpc_usart lpc_usart;
764 #define lpc_usart (*(struct lpc_usart *) 0x40008000)
766 #define LPC_USART_IER_RBRINTEN 0
767 #define LPC_USART_IER_THREINTEN 1
768 #define LPC_USART_IER_RSLINTEN 2
769 #define LPC_USART_IER_MSINTEN 3
770 #define LPC_USART_IER_ABEOINTEN 8
771 #define LPC_USART_IER_ABTOINTEN 9
773 #define LPC_USART_IIR_INTSTATUS 0
774 #define LPC_USART_IIR_INTID 1
775 #define LPC_USART_IIR_INTID_RLS 3
776 #define LPC_USART_IIR_INTID_RDA 2
777 #define LPC_USART_IIR_INTID_CTI 6
778 #define LPC_USART_IIR_INTID_THRE 1
779 #define LPC_USART_IIR_INTID_MS 0
780 #define LPC_USART_IIR_INTID_MASK 7UL
781 #define LPC_USART_IIR_FIFOEN 6
782 #define LPC_USART_IIR_ABEOINT 8
783 #define LPC_USART_IIR_ABTOINT 9
785 #define LPC_USART_FCR_FIFOEN 0
786 #define LPC_USART_FCR_RXFIFORES 1
787 #define LPC_USART_FCR_TXFIFORES 2
788 #define LPC_USART_FCR_RXTL 6
789 #define LPC_USART_FCR_RXTL_1 0
790 #define LPC_USART_FCR_RXTL_4 1
791 #define LPC_USART_FCR_RXTL_8 2
792 #define LPC_USART_FCR_RXTL_14 3
794 #define LPC_USART_LCR_WLS 0
795 #define LPC_USART_LCR_WLS_5 0
796 #define LPC_USART_LCR_WLS_6 1
797 #define LPC_USART_LCR_WLS_7 2
798 #define LPC_USART_LCR_WLS_8 3
799 #define LPC_USART_LCR_WLS_MASK 3UL
800 #define LPC_USART_LCR_SBS 2
801 #define LPC_USART_LCR_SBS_1 0
802 #define LPC_USART_LCR_SBS_2 1
803 #define LPC_USART_LCR_SBS_MASK 1UL
804 #define LPC_USART_LCR_PE 3
805 #define LPC_USART_LCR_PS 4
806 #define LPC_USART_LCR_PS_ODD 0
807 #define LPC_USART_LCR_PS_EVEN 1
808 #define LPC_USART_LCR_PS_ONE 2
809 #define LPC_USART_LCR_PS_ZERO 3
810 #define LPC_USART_LCR_PS_MASK 3UL
811 #define LPC_USART_LCR_BC 6
812 #define LPC_USART_LCR_DLAB 7
814 #define LPC_USART_MCR_DTRCTRL 0
815 #define LPC_USART_MCR_RTSCTRL 1
816 #define LPC_USART_MCR_LMS 4
817 #define LPC_USART_MCR_RTSEN 6
818 #define LPC_USART_MCR_CTSEN 7
820 #define LPC_USART_LSR_RDR 0
821 #define LPC_USART_LSR_OE 1
822 #define LPC_USART_LSR_PE 2
823 #define LPC_USART_LSR_FE 3
824 #define LPC_USART_LSR_BI 4
825 #define LPC_USART_LSR_THRE 5
826 #define LPC_USART_LSR_TEMT 6
827 #define LPC_USART_LSR_RXFE 7
828 #define LPC_USART_LSR_TXERR 8
830 #define LPC_USART_MSR_DCTS 0
831 #define LPC_USART_MSR_DDSR 1
832 #define LPC_USART_MSR_TERI 2
833 #define LPC_USART_MSR_DDCD 3
834 #define LPC_USART_MSR_CTS 4
835 #define LPC_USART_MSR_DSR 5
836 #define LPC_USART_MSR_RI 6
837 #define LPC_USART_MSR_DCD 7
839 #define LPC_USART_ACR_START 0
840 #define LPC_USART_ACR_MODE 1
841 #define LPC_USART_ACR_AUTORESTART 2
842 #define LPC_USART_ACR_ABEOINTCLR 8
843 #define LPC_USART_ACR_ABTOINTCLR 9
845 #define LPC_USART_FDR_DIVADDVAL 0
846 #define LPC_USART_FDR_MULVAL 4
848 #define LPC_USART_OSR_OSFRAC 1
849 #define LPC_USART_OSR_OSINT 4
850 #define LPC_USART_OSR_FDINT 8
852 #define LPC_USART_TER_TXEN 7
854 #define LPC_USART_HDEN_HDEN 0
857 vuint32_t devcmdstat;
859 vuint32_t epliststart;
860 vuint32_t databufstart;
867 vuint32_t intsetstat;
868 vuint32_t introuting;
873 extern struct lpc_usb lpc_usb;
874 #define lpc_usb (*(struct lpc_usb *) 0x40080000)
876 #define LPC_USB_DEVCMDSTAT_DEV_ADDR 0
877 #define LPC_USB_DEVCMDSTAT_DEV_ADDR_MASK 0x7fUL
878 #define LPC_USB_DEVCMDSTAT_DEV_EN 7
879 #define LPC_USB_DEVCMDSTAT_SETUP 8
880 #define LPC_USB_DEVCMDSTAT_PLL_ON 9
881 #define LPC_USB_DEVCMDSTAT_LPM_SUP 11
882 #define LPC_USB_DEVCMDSTAT_INTONNAK_AO 12
883 #define LPC_USB_DEVCMDSTAT_INTONNAK_AI 13
884 #define LPC_USB_DEVCMDSTAT_INTONNAK_CO 14
885 #define LPC_USB_DEVCMDSTAT_INTONNAK_CI 15
886 #define LPC_USB_DEVCMDSTAT_DCON 16
887 #define LPC_USB_DEVCMDSTAT_DSUS 17
888 #define LPC_USB_DEVCMDSTAT_LPM_SUS 19
889 #define LPC_USB_DEVCMDSTAT_LPM_REWP 20
890 #define LPC_USB_DEVCMDSTAT_DCON_C 24
891 #define LPC_USB_DEVCMDSTAT_DSUS_C 25
892 #define LPC_USB_DEVCMDSTAT_DRES_C 26
893 #define LPC_USB_DEVCMDSTAT_VBUSDEBOUNCED 28
895 #define LPC_USB_INFO_FRAME_NR 0
896 #define LPC_USB_INFO_FRAME_NR_MASK 0x3ffUL
897 #define LPC_USB_INFO_ERR_CODE 11
898 #define LPC_USB_INFO_ERR_CODE_NO_ERROR 0
899 #define LPC_USB_INFO_ERR_CODE_PID_ENCODING_ERROR 1
900 #define LPC_USB_INFO_ERR_CODE_PID_UNKNOWN 2
901 #define LPC_USB_INFO_ERR_CODE_PACKET_UNEXPECTED 3
902 #define LPC_USB_INFO_ERR_CODE_TOKEN_CRC_ERROR 4
903 #define LPC_USB_INFO_ERR_CODE_DATA_CRC_ERROR 5
904 #define LPC_USB_INFO_ERR_CODE_TIME_OUT 6
905 #define LPC_USB_INFO_ERR_CODE_BABBLE 7
906 #define LPC_USB_INFO_ERR_CODE_TRUNCATED_EOP 8
907 #define LPC_USB_INFO_ERR_CODE_SENT_RECEIVED_NAK 9
908 #define LPC_USB_INFO_ERR_CODE_SENT_STALL 0xa
909 #define LPC_USB_INFO_ERR_CODE_OVERRUN 0xb
910 #define LPC_USB_INFO_ERR_CODE_SENT_EMPTY_PACKET 0xc
911 #define LPC_USB_INFO_ERR_CODE_BITSTUFF_ERROR 0xd
912 #define LPC_USB_INFO_ERR_CODE_SYNC_ERROR 0xe
913 #define LPC_USB_INFO_ERR_CODE_WRONG_DATA_TOGGLE 0xf
914 #define LPC_USB_INFO_ERR_CODE_MASK 0xfUL
916 #define LPC_USB_EPLISTSTART_EP_LIST 0
918 #define LPC_USB_DATABUFSTART_DA_BUF 0
920 #define LPC_USB_LPM_HIRD_HW 0
921 #define LPC_USB_LPM_HIRD_HW_MASK 0xfUL
922 #define LPC_USB_LPM_HIRD_SW 4
923 #define LPC_USB_LPM_HIRD_SW_MASK 0xfUL
924 #define LPC_USB_LPM_DATA_PENDING 8
926 #define LPC_USB_EPSKIP_SKIP 0
928 #define LPC_USB_EPINUSE_BUF(ep) (ep)
930 #define LPC_USB_EPBUFCFG_BUF_SB(ep) (ep)
932 #define LPC_USB_INT_EPOUT(ep) ((ep) << 1)
933 #define LPC_USB_INT_EPIN(ep) (((ep) << 1) + 1)
935 #define LPC_USB_INT_FRAME 30
936 #define LPC_USB_INT_DEV 31
938 #define LPC_USB_INTIN_EP_INT_EN(ep) (ep)
939 #define LPC_USB_INTIN_FRAME_INT_EN 30
940 #define LPC_USB_INTIN_DEV_INT_EN 31
942 #define LPC_USB_INTSETSTAT_EP_SET_INT(ep) (ep)
943 #define LPC_USB_INTSETSTAT_FRAME_SET_INT 30
944 #define LPC_USB_INTSETSTAT_DEV_SET_INT 31
946 #define LPC_USB_INTROUTING_ROUTE_INT(ep) (ep)
947 #define LPC_USB_INTROUTING_INT30 30
948 #define LPC_USB_INTROUTING_INT31 31
950 #define LPC_USB_EPTOGGLE_TOGGLE(ep) (ep)
957 struct lpc_usb_endpoint {
961 vuint32_t reserved_0c;
962 struct lpc_usb_epn epn[4];
964 #define lpc_usb_endpoint (*(struct lpc_usb_endpoint *) 0x20004700)
966 /* Assigned in registers.ld to point at the base
970 extern uint8_t lpc_usb_sram[];
971 #define lpc_usb_sram ((uint8_t*) 0x20004000)
973 #define LPC_USB_EP_ACTIVE 31
974 #define LPC_USB_EP_DISABLED 30
975 #define LPC_USB_EP_STALL 29
976 #define LPC_USB_EP_TOGGLE_RESET 28
977 #define LPC_USB_EP_RATE_FEEDBACK 27
978 #define LPC_USB_EP_ENDPOINT_ISO 26
979 #define LPC_USB_EP_NBYTES 16
980 #define LPC_USB_EP_NBYTES_MASK 0x3ffUL
981 #define LPC_USB_EP_OFFSET 0
983 #define LPC_ISR_PIN_INT0_POS 0
984 #define LPC_ISR_PIN_INT1_POS 1
985 #define LPC_ISR_PIN_INT2_POS 2
986 #define LPC_ISR_PIN_INT3_POS 3
987 #define LPC_ISR_PIN_INT4_POS 4
988 #define LPC_ISR_PIN_INT5_POS 5
989 #define LPC_ISR_PIN_INT6_POS 6
990 #define LPC_ISR_PIN_INT7_POS 7
991 #define LPC_ISR_GINT0_POS 8
992 #define LPC_ISR_GINT1_POS 9
993 #define LPC_ISR_SSP1_POS 14
994 #define LPC_ISR_I2C_POS 15
995 #define LPC_ISR_CT16B0_POS 16
996 #define LPC_ISR_CT16B1_POS 17
997 #define LPC_ISR_CT32B0_POS 18
998 #define LPC_ISR_CT32B1_POS 19
999 #define LPC_ISR_SSP0_POS 20
1000 #define LPC_ISR_USART_POS 21
1001 #define LPC_ISR_USB_IRQ_POS 22
1002 #define LPC_ISR_USB_FIQ_POS 23
1003 #define LPC_ISR_ADC_POS 24
1004 #define LPC_ISR_WWDT_POS 25
1005 #define LPC_ISR_BOD_POS 26
1006 #define LPC_ISR_FLASH_POS 27
1007 #define LPC_ISR_USB_WAKEUP_POS 30
1010 vuint32_t iser; /* 0x000 0xe000e100 Set Enable Register */
1012 uint8_t _unused020[0x080 - 0x004];
1014 vuint32_t icer; /* 0x080 0xe000e180 Clear Enable Register */
1016 uint8_t _unused0a0[0x100 - 0x084];
1018 vuint32_t ispr; /* 0x100 0xe000e200 Set Pending Register */
1020 uint8_t _unused120[0x180 - 0x104];
1022 vuint32_t icpr; /* 0x180 0xe000e280 Clear Pending Register */
1024 uint8_t _unused1a0[0x300 - 0x184];
1026 vuint32_t ipr[8]; /* 0x300 0xe000e400 Priority Register */
1029 extern struct lpc_nvic lpc_nvic;
1030 #define lpc_nvic (*(struct lpc_nvic *) 0xe000e100)
1033 lpc_nvic_set_enable(int irq) {
1034 lpc_nvic.iser = (1 << irq);
1038 lpc_nvic_clear_enable(int irq) {
1039 lpc_nvic.icer = (1 << irq);
1043 lpc_nvic_enabled(int irq) {
1044 return (lpc_nvic.iser >> irq) & 1;
1049 lpc_nvic_set_pending(int irq) {
1050 lpc_nvic.ispr = (1 << irq);
1054 lpc_nvic_clear_pending(int irq) {
1055 lpc_nvic.icpr = (1 << irq);
1059 lpc_nvic_pending(int irq) {
1060 return (lpc_nvic.ispr >> irq) & 1;
1063 #define IRQ_PRIO_REG(irq) ((irq) >> 2)
1064 #define IRQ_PRIO_BIT(irq) (((irq) & 3) << 3)
1065 #define IRQ_PRIO_MASK(irq) (0xffUL << IRQ_PRIO_BIT(irq))
1068 lpc_nvic_set_priority(int irq, uint8_t prio) {
1069 int n = IRQ_PRIO_REG(irq);
1072 v = lpc_nvic.ipr[n];
1073 v &= ~IRQ_PRIO_MASK(irq);
1074 v |= (prio) << IRQ_PRIO_BIT(irq);
1075 lpc_nvic.ipr[n] = v;
1078 static inline uint8_t
1079 lpc_nvic_get_priority(int irq) {
1080 return (lpc_nvic.ipr[IRQ_PRIO_REG(irq)] >> IRQ_PRIO_BIT(irq)) & IRQ_PRIO_MASK(0);
1086 uint32_t reserved08;
1091 uint32_t reserved18;
1097 extern struct arm_scb arm_scb;
1098 #define arm_scb (*(struct arm_scb *) 0xe000ed00)
1101 vuint32_t cr0; /* 0x00 */
1106 vuint32_t cpsr; /* 0x10 */
1111 vuint32_t icr; /* 0x20 */
1114 extern struct lpc_ssp lpc_ssp0, lpc_ssp1;
1115 #define lpc_ssp0 (*(struct lpc_ssp *) 0x40040000)
1116 #define lpc_ssp1 (*(struct lpc_ssp *) 0x40058000)
1118 #define LPC_NUM_SPI 2
1120 #define LPC_SSP_FIFOSIZE 8
1122 #define LPC_SSP_CR0_DSS 0
1123 #define LPC_SSP_CR0_DSS_4 0x3
1124 #define LPC_SSP_CR0_DSS_5 0x4
1125 #define LPC_SSP_CR0_DSS_6 0x5
1126 #define LPC_SSP_CR0_DSS_7 0x6
1127 #define LPC_SSP_CR0_DSS_8 0x7
1128 #define LPC_SSP_CR0_DSS_9 0x8
1129 #define LPC_SSP_CR0_DSS_10 0x9
1130 #define LPC_SSP_CR0_DSS_11 0xa
1131 #define LPC_SSP_CR0_DSS_12 0xb
1132 #define LPC_SSP_CR0_DSS_13 0xc
1133 #define LPC_SSP_CR0_DSS_14 0xd
1134 #define LPC_SSP_CR0_DSS_15 0xe
1135 #define LPC_SSP_CR0_DSS_16 0xf
1136 #define LPC_SSP_CR0_FRF 4
1137 #define LPC_SSP_CR0_FRF_SPI 0
1138 #define LPC_SSP_CR0_FRF_TI 1
1139 #define LPC_SSP_CR0_FRF_MICROWIRE 2
1140 #define LPC_SSP_CR0_CPOL 6
1141 #define LPC_SSP_CR0_CPOL_LOW 0
1142 #define LPC_SSP_CR0_CPOL_HIGH 1
1143 #define LPC_SSP_CR0_CPHA 7
1144 #define LPC_SSP_CR0_CPHA_FIRST 0
1145 #define LPC_SSP_CR0_CPHA_SECOND 1
1146 #define LPC_SSP_CR0_SCR 8
1148 #define LPC_SSP_CR1_LBM 0
1149 #define LPC_SSP_CR1_SSE 1
1150 #define LPC_SSP_CR1_MS 2
1151 #define LPC_SSP_CR1_MS_MASTER 0
1152 #define LPC_SSP_CR1_MS_SLAVE 1
1153 #define LPC_SSP_CR1_SOD 3
1155 #define LPC_SSP_SR_TFE 0
1156 #define LPC_SSP_SR_TNF 1
1157 #define LPC_SSP_SR_RNE 2
1158 #define LPC_SSP_SR_RFF 3
1159 #define LPC_SSP_SR_BSY 4
1161 #define LPC_SSP_IMSC_RORIM 0
1162 #define LPC_SSP_IMSC_RTIM 1
1163 #define LPC_SSP_IMSC_RXIM 2
1164 #define LPC_SSP_IMSC_TXIM 3
1166 #define LPC_SSP_RIS_RORRIS 0
1167 #define LPC_SSP_RIS_RTRIS 1
1168 #define LPC_SSP_RIS_RXRIS 2
1169 #define LPC_SSP_RIS_TXRIS 3
1171 #define LPC_SSP_MIS_RORMIS 0
1172 #define LPC_SSP_MIS_RTMIS 1
1173 #define LPC_SSP_MIS_RXMIS 2
1174 #define LPC_SSP_MIS_TXMIS 3
1176 #define LPC_SSP_ICR_RORIC 0
1177 #define LPC_SSP_ICR_RTIC 1
1180 vuint32_t cr; /* 0x00 */
1185 vuint32_t dr[8]; /* 0x10 */
1187 vuint32_t stat; /* 0x30 */
1190 extern struct lpc_adc lpc_adc;
1191 #define lpc_adc (*(struct lpc_adc *) 0x4001c000)
1193 #define LPC_ADC_CR_SEL 0
1194 #define LPC_ADC_CR_CLKDIV 8
1195 #define LPC_ADC_CR_BURST 16
1196 #define LPC_ADC_CR_CLKS 17
1197 #define LPC_ADC_CR_CLKS_11 0
1198 #define LPC_ADC_CR_CLKS_10 1
1199 #define LPC_ADC_CR_CLKS_9 2
1200 #define LPC_ADC_CR_CLKS_8 3
1201 #define LPC_ADC_CR_CLKS_7 4
1202 #define LPC_ADC_CR_CLKS_6 5
1203 #define LPC_ADC_CR_CLKS_5 6
1204 #define LPC_ADC_CR_CLKS_4 7
1205 #define LPC_ADC_CR_START 24
1206 #define LPC_ADC_CR_START_NONE 0
1207 #define LPC_ADC_CR_START_NOW 1
1209 #define LPC_ADC_GDR_CHN 24
1210 #define LPC_ADC_GDR_OVERRUN 30
1211 #define LPC_ADC_GDR_DONE 31
1213 #define LPC_ADC_INTEN_ADINTEN 0
1214 #define LPC_ADC_INTEN_ADGINTEN 8
1216 #define LPC_ADC_STAT_DONE 0
1217 #define LPC_ADC_STAT_OVERRUN 8
1218 #define LPC_ADC_STAT_ADINT 16
1221 vuint32_t ir; /* 0x00 */
1226 vuint32_t pc; /* 0x10 */
1228 vuint32_t mr[4]; /* 0x18 */
1229 vuint32_t ccr; /* 0x28 */
1232 vuint32_t cr1_0; /* 0x30 (only for ct16b0 */
1233 vuint32_t cr1_1; /* 0x34 (only for ct16b1 */
1237 uint8_t r40[0x70 - 0x40];
1239 vuint32_t ctcr; /* 0x70 */
1243 extern struct lpc_ct16b lpc_ct16b0, lpc_ct16b1;
1244 #define lpc_ct16b0 (*(struct lpc_ct16b *) 0x4000c000)
1245 #define lpc_ct16b1 (*(struct lpc_ct16b *) 0x40010000)
1247 #define LPC_CT16B_IR_MR0INT 0
1248 #define LPC_CT16B_IR_MR1INT 1
1249 #define LPC_CT16B_IR_MR2INT 2
1250 #define LPC_CT16B_IR_MR3INT 3
1251 #define LPC_CT16B_IR_CR0INT 4
1252 #define LPC_CT16B0_IR_CR1INT 6
1253 #define LPC_CT16B1_IR_CR1INT 5
1255 #define LPC_CT16B_TCR_CEN 0
1256 #define LPC_CT16B_TCR_CRST 1
1258 #define LPC_CT16B_MCR_MR0I 0
1259 #define LPC_CT16B_MCR_MR0R 1
1260 #define LPC_CT16B_MCR_MR0S 2
1261 #define LPC_CT16B_MCR_MR1I 3
1262 #define LPC_CT16B_MCR_MR1R 4
1263 #define LPC_CT16B_MCR_MR1S 5
1264 #define LPC_CT16B_MCR_MR2I 6
1265 #define LPC_CT16B_MCR_MR2R 7
1266 #define LPC_CT16B_MCR_MR2S 8
1267 #define LPC_CT16B_MCR_MR3I 9
1268 #define LPC_CT16B_MCR_MR3R 10
1269 #define LPC_CT16B_MCR_MR3S 11
1271 #define LPC_CT16B_CCR_CAP0RE 0
1272 #define LPC_CT16B_CCR_CAP0FE 1
1273 #define LPC_CT16B_CCR_CAP0I 2
1274 #define LPC_CT16B0_CCR_CAP1RE 6
1275 #define LPC_CT16B0_CCR_CAP1FE 7
1276 #define LPC_CT16B0_CCR_CAP1I 8
1277 #define LPC_CT16B1_CCR_CAP1RE 3
1278 #define LPC_CT16B1_CCR_CAP1FE 4
1279 #define LPC_CT16B1_CCR_CAP1I 5
1281 #define LPC_CT16B_EMR_EM0 0
1282 #define LPC_CT16B_EMR_EM1 1
1283 #define LPC_CT16B_EMR_EM2 2
1284 #define LPC_CT16B_EMR_EM3 3
1285 #define LPC_CT16B_EMR_EMC0 4
1286 #define LPC_CT16B_EMR_EMC1 6
1287 #define LPC_CT16B_EMR_EMC2 8
1288 #define LPC_CT16B_EMR_EMC3 10
1290 #define LPC_CT16B_EMR_EMC_NOTHING 0
1291 #define LPC_CT16B_EMR_EMC_CLEAR 1
1292 #define LPC_CT16B_EMR_EMC_SET 2
1293 #define LPC_CT16B_EMR_EMC_TOGGLE 3
1295 #define LPC_CT16B_CCR_CTM 0
1296 #define LPC_CT16B_CCR_CTM_TIMER 0
1297 #define LPC_CT16B_CCR_CTM_COUNTER_RISING 1
1298 #define LPC_CT16B_CCR_CTM_COUNTER_FALLING 2
1299 #define LPC_CT16B_CCR_CTM_COUNTER_BOTH 3
1300 #define LPC_CT16B_CCR_CIS 2
1301 #define LPC_CT16B_CCR_CIS_CAP0 0
1302 #define LPC_CT16B0_CCR_CIS_CAP1 2
1303 #define LPC_CT16B1_CCR_CIS_CAP1 1
1304 #define LPC_CT16B_CCR_ENCC 4
1305 #define LPC_CT16B_CCR_SELCC 5
1306 #define LPC_CT16B_CCR_SELCC_RISING_CAP0 0
1307 #define LPC_CT16B_CCR_SELCC_FALLING_CAP0 1
1308 #define LPC_CT16B0_CCR_SELCC_RISING_CAP1 4
1309 #define LPC_CT16B0_CCR_SELCC_FALLING_CAP1 5
1310 #define LPC_CT16B1_CCR_SELCC_RISING_CAP1 2
1311 #define LPC_CT16B1_CCR_SELCC_FALLING_CAP1 3
1312 #define LPC_CT16B_CCR_
1314 #define LPC_CT16B_PWMC_PWMEN0 0
1315 #define LPC_CT16B_PWMC_PWMEN1 1
1316 #define LPC_CT16B_PWMC_PWMEN2 2
1317 #define LPC_CT16B_PWMC_PWMEN3 3
1320 vuint32_t ir; /* 0x00 */
1325 vuint32_t pc; /* 0x10 */
1327 vuint32_t mr[4]; /* 0x18 */
1328 vuint32_t ccr; /* 0x28 */
1331 vuint32_t cr1_0; /* 0x30 (only for ct32b0 */
1332 vuint32_t cr1_1; /* 0x34 (only for ct32b1 */
1338 vuint32_t ctcr; /* 0x70 */
1342 extern struct lpc_ct32b lpc_ct32b0, lpc_ct32b1;
1343 #define lpc_ct32b0 (*(struct lpc_ct32b *) 0x40014000)
1344 #define lpc_ct32b1 (*(struct lpc_ct32b *) 0x40018000)
1346 #define LPC_CT32B_TCR_CEN 0
1347 #define LPC_CT32B_TCR_CRST 1
1349 #define LPC_CT32B_MCR_MR0R 1
1351 #define LPC_CT32B_PWMC_PWMEN0 0
1352 #define LPC_CT32B_PWMC_PWMEN1 1
1353 #define LPC_CT32B_PWMC_PWMEN2 2
1354 #define LPC_CT32B_PWMC_PWMEN3 3
1356 #define LPC_CT32B_EMR_EMC0 4
1357 #define LPC_CT32B_EMR_EMC1 6
1358 #define LPC_CT32B_EMR_EMC2 8
1359 #define LPC_CT32B_EMR_EMC3 10
1361 #define LPC_CT32B_EMR_EMC_NOTHING 0
1362 #define LPC_CT32B_EMR_EMC_CLEAR 1
1363 #define LPC_CT32B_EMR_EMC_SET 2
1364 #define LPC_CT32B_EMR_EMC_TOGGLE 3
1366 #define isr_decl(name) \
1367 void lpc_ ## name ## _isr(void)
1373 isr_decl(hardfault);
1374 isr_decl(memmanage);
1376 isr_decl(usagefault);
1382 isr_decl(pin_int0); /* IRQ0 */
1386 isr_decl(pin_int4); /* IRQ4 */
1391 isr_decl(gint0); /* IRQ8 */
1396 isr_decl(ct16b0); /* IRQ16 */
1400 isr_decl(ssp0); /* IRQ20 */
1405 isr_decl(adc); /* IRQ24 */
1410 isr_decl(usb_wakeup);
1412 #endif /* _LPC_H_ */